Interconnect Delay Aware RTL Verilog Bus Architecture Generation - - PowerPoint PPT Presentation

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Interconnect Delay Aware RTL Verilog Bus Architecture Generation - - PowerPoint PPT Presentation

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Interconnect Delay Aware RTL Verilog Bus Architecture Generation for an SoC Kyeong Ryu, Alexandru Talpasanu, Vincent Mooney and Jeffrey Davis School of Electrical and Computer Engineering Georgia Institute of Technology August 2004 Outline

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SLIDE 1

Interconnect Delay Aware RTL Verilog Bus Architecture Generation for an SoC

Kyeong Ryu, Alexandru Talpasanu, Vincent Mooney and Jeffrey Davis School of Electrical and Computer Engineering Georgia Institute of Technology August 2004

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SLIDE 2

Outline

  • Introduction
  • Interconnect Delay Estimation
  • Interconnect Aware Module Generation
  • BusSynth Overview
  • Application Example
  • Conclusion
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Introduction

  • A methodology to generate a

custom bus architecture using accurate estimations of interconnect delay

– Easy and quick design of an SoC bus system – Fast design space exploration across performance influencing factors – Development of a bus synthesis tool (BusSynth) – Register-transfer level HDL

  • utput based on user options and

interconnect delay

Bus Synthesis Tool (BusSynth) Bus Synthesis Tool (BusSynth) User Options

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Related Work

  • Shin et al. (’04), “Fast Exploration of Parameterized

Bus Architecture for Communication-Centric SoC Design” [5]

– A single type of bus topology

  • Thepayasuwan et al. (’04), “Layout Conscious Bus

Architecture Synthesis for Deep Submicron Systems on Chip” [6]

– A single type of bus topology

  • BusSynth

– A variety of bus types including multiple and heterogeneous type – Interconnect delay aware bus generation

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SLIDE 5

Bus Synthesis (BusSynth) Overview

INPUT LIBRARIES

SYNTHESIZABLE VERILOG HDL CODE

User options

BusSynth

BUS GENERATION TOOL

Interconnect Delay Estimation Interconnect Delay Estimation Floorplan Design Floorplan Design

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SLIDE 6

MPC755 MPC755 PE3 PE3 SRAM SRAM SRAM SRAM MPC755 MPC755 PE1 PE1 MPC75 MPC755 PE PE 2 2 MPC755 MPC755 PE4 PE4

Memory Bus Interface (MBI) Bus Arbitrer Bus Interconnect

Legend

CPU Bus Interface (CBI)

(b) Interconnect length estimation (a) Estimated Floorplan

Interconnect Length Estimation

** TSMC 0.25 µm Design Rules

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SLIDE 7

Interconnect Model Parameters

M1 M2 M3 substrate M1 M2 M3 Ra C1 n C1 n C1 n C1 n C1 n C1 n C1 n C1 n R1/n R1/n R1/n R1/n R1/n R1/n R1/n R1/n Ra = MOSIS sheet resistance R1 Ca Ca = MOSIS fringe capacitance Cb Cb = MOSIS area capacitance Coupling capacitance effects explained in technical report [11]

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SLIDE 8

Accurate Interconnect Delay Estimation

MPC MPC755 755 PE3 PE3 SR SRAM AM SR SRAM AM MP MPC755 55 PE1 PE1 MP MPC755 C755 PE 2 PE 2 MPC MPC755 755 PE4 PE4 Memory Bus Interface (MBI) Bus Arbitrer Bus Interconnect Legend CPU Bus Interface (CBI)

Floorplan Bus Interconnect Length Calculation MOSIS Process Parameters HSPICE Code Generation Tool HSPICE simulator Interconnect Delay Calculation for Each Bus Segment

[MOSIS website]

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SLIDE 9

A Bus System Example:

General Global Bus Architecture (GGBA)

Note BAN: Bus Access Node, PE: Processing Element, CBI: CPU Bus Interface MBI: Memory Bus Interface

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Memory Bus Interface (MBI) Module Generation 1

  • One of effects of interconnect delay insertion

in an SoC: memory access cycle

  • Memory controller to adapt delay clocks due

to interconnect delay

PowerPCs

MBI (delay info.) SRAM

aack_bars ta_bars address data control signals sram_ data cs_bar we_bar sram address re_bar

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SLIDE 11

Memory Bus Interface (MBI) Module Generation 2

(a) Estimated total delay of paths between each PE and a shared memory (b) Number of clock delays in data paths

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SLIDE 12

MBI and Bus System Generation

Reference*: K. Ryu and V. Mooney, “Automated Bus Generation for Multiprocessor SoC Design,” Design, Automation and Test in Europe (DATE'03), pp. 282-287, March 2003.

  • Memory Bus Interface (MBI) module generation

(a) Sequence of MBI Generation (b) Bus System Generation*

Bus Access Node (BAN) Generation

Synthesizable Verilog HDL code Wire Library Bus System Generation

BusSynth

Bus Subsystem Generation For each Bus Subsystem # of Subsystem > 1

Y N

Module Library For each BAN Module Generation User Option Input

Input of interconnect delays Calculation of the number

  • f clocks to be inserted

Extraction of MBI module from Module Library Update of memory access delay parameters in an MBI module

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A Bus System Generation Example

User Input List

  • 1. Bus System: # of Bus Subsystems = 1
  • 2. Bus Subsystem: # of BANs = 5
  • 3. Bus Properties:
  • Bus Subsystem: address bus width = 32 and data

bus width: 64

  • 4. BAN Properties:

For Bus Subsystem

  • BAN1: CPU Type = MPC755, non-CPU Type = None

and # of global and local memories = 0

  • BAN2: CPU Type = MPC755, non-CPU Type = None

and #s of global and local memories = 0

  • BAN3: CPU Type = MPC755, non-CPU Type = None

and #s of global and local memories = 0

  • BAN4: CPU Type = MPC755, non-CPU Type = None

and #s of global and local memories = 0

  • BAN5: CPU Type = None , non-CPU Type = None,

# of global memories = 1, and # of local memories = 0

  • 5. Memory Properties:
  • BAN5: Type = SRAM, address bus width = 21 and

data bus width = 64

BAN4 BAN3 BAN2

Synthesizable Verilog HDL code Synthesizable Verilog HDL code Wire Library Bus System Generation Bus System Generation User Option Input User Option Input

BusSynth

Bus Subsystem Generation Bus Subsystem Generation For each Subsystem 1 # of Subsystem > 1

Y N

Module Library Bus Subsystem Generation Bus Subsystem Generation Bus System Generation Bus System Generation Bus System Generation Bus System Generation

MPC755 MPC755 CBI_ MPC755 CBI_ MPC755 CBI_ MPC755 CBI_ MPC755 MPC755 MPC755 MPC755 MPC755 CBI_ MPC755 CBI_ MPC755 CBI_ MPC755 CBI_ MPC755 MPC755 MPC755

BAN1 BAN5 Bus Subsystem Bus System

User Option Input User Option Input Bus Subsystem Generation Bus Subsystem Generation For each Subsystem Bus Access Node Generation Bus Access Node Generation Bus Subsystem Generation Bus Subsystem Generation # of Subsystem > 1 # of Subsystem > 1 Bus System Generation Bus System Generation

SRAM SRAM Arbiter Arbiter MBI_ SRAM MBI_ SRAM

Bus System Generation Bus System Generation Synthesizable Verilog HDL code Synthesizable Verilog HDL code

// Skipped .up_dataout(dataout_up_2[FIFO_D_WIDTH-1:0]), .up_gen_int(gen_int_up_2), .up_isr0_ctlhi(isr0_ctlhi_up_2), .up_isr0_ctllo(isr0_ctllo_up_2), .dn_datain(datain_up_3[FIFO_D_WIDTH-1:0]), .reb_dn(reb_up_3), .web_dn(web_up_3), .fifo_area_dn(fifo_area_up_3) ); endmodule module BusSystem(sysrstb, sysclk); input sysrstb; input sysclk; // Skipped SubSys_GGBA SubSystem( .sysrstb(sysrstb), .sysclk(sysclk) // Skipped ); endmodule

Bus Access Node 1 (BAN1) Generation Bus Access Node 1 (BAN1) Generation Bus Access Node 2 (BAN2) Generation Bus Access Node 2 (BAN2) Generation Bus Access Node 3 (BAN3) Generation Bus Access Node 3 (BAN3) Generation Bus Access Node 4 (BAN4) Generation Bus Access Node 4 (BAN4) Generation Bus Access Node 5 (BAN5) Generation Bus Access Node 5 (BAN5) Generation Bus Access Node Generation Bus Access Node Generation

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SLIDE 14

Application Example

  • Orthogonal Frequency Division Multiplexing

(OFDM) Transmitter, a wireless algorithm

  • Function assignment and their processing
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Experimental Setup

INPUT LIBRARIES

SYNTHESIZABLE VERILOG HDL CODE

User options

BusSynth

VCS SEAMLESS CVE XRAY GCC

USER C-CODE

BUS GENERATION TOOL SIMULATION ENVIRONMENT SYNTHESIS ENVIRONMENT

DESIGN COMPILER Note: VCS and Design Compiler from Synopsys, Seamless CVE and Xray from Mentor Graphics and GCC from GNU Interconnect Delay Estimation Interconnect Delay Estimation Floorplan Design Floorplan Design

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Three Configurations of GGBA for Performance Comparison

– GGBA I - (NO WIRE MODEL)

GGBA I is a GGBA system with no regard to interconnect delay on the bus

– GGBA II - (ACCURATE WIRE MODEL)

GGBA II is a GGBA system that works with different estimated interconnect delays on the shared bus

– GGBA III - (WORST-CASE WIRE MODEL)

GGBA III is a GGBA system that operates with a maximum estimated delay on all connections between PEs and a shared memory

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Memory Bus Interface (MBI) Module Generation 2

(a) Estimated total delay of paths between each PE and a shared memory (b) Number of clock delays in data paths

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Comparison Results

Baseline

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Comparison Results

Baseline Baseline Baseline

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Conclusion

  • Interconnect delay is a major concern as

feature size is scaled down

  • Interconnect delay estimation from floorplan
  • Memory Bus Interface (MBI) module and Bus

System generation

  • Performance improvement due to

interconnect delay aware design

  • In an OFDM transmitter example, 35.3%

reduction in execution time against GGBA III

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Any Questions ?