Incremental Layer Assignment for Critical Path Timing Derong Liu 1 , - - PowerPoint PPT Presentation

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Incremental Layer Assignment for Critical Path Timing Derong Liu 1 , - - PowerPoint PPT Presentation

Incremental Layer Assignment for Critical Path Timing Derong Liu 1 , Bei Yu 2 , Salim Chowdhury 3 , and David Z. Pan 1 1 ECE Department, University of Texas at Austin, Austin, TX, USA 2 CSE Department, Chinese University of Hong Kong, Hong Kong 3


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Incremental Layer Assignment for Critical Path Timing

Derong Liu1, Bei Yu2, Salim Chowdhury3, and David Z. Pan1

1ECE Department, University of Texas at Austin, Austin, TX, USA 2CSE Department, Chinese University of Hong Kong, Hong Kong 3Oracle Corp., Austin, TX, USA

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Introduction

t As VLSI technology scales to deep submicron

› Interconnect dominates timing issues › Global routing – integral part of timing convergence flow

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2D Global Routing Layer Assignment 3D Global Routing

Global Routing Flow

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Previous Works on GR and LA

t Example papers on global routing and layer assignment:

› Timing-driven GR [Liu et al. TCAD’13] › Via count and overflow minimization during layer assignment - NVM [Liu+, ASPDAC’11] › Delay-driven layer assignment [Yu+, ICCAD’15]

t Limitations of previous layer assignment:

› Net-by-net method may lead to sub-optimal results › Focus on sum of net delays › Lack global optimization › Linear approximation of via delays influences accuracy.

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Contributions of this Work

t A novel incremental layer assignment framework for

critical path timing with via delays

t Semidefinite programming (SDP) modeling for better

  • ptimal solutions

t Self-adaptive partitioning methodology based on K*K

partitions for speed-up

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Problem Formulation

t Critical Path Layer Assignment (CPLA)

› Given a 3-D grid graph, edge and layer information, initial layer assignment solution and set of critical nets › Minimize: critical path timing (Elmore delay) › Subject to: edge capacity constraints

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n1 n2 n3 n1 n2 n3 Non-Critical Nets: n1 n2 ; Critical Net: n3 (a) (b)

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CPLA Algorithm

t Mathematical Formulation t Constraints:

› Each segment should be assigned on one and only one layer › Edge capacity constraint: › Via capacity constraint:

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Segment costs Via costs

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Self-adaptive Quadruple Partition

t K x K division [Yu+, ICCAD’15]

› Unbalanced computation overhead

t Limit the number of segments in each partition

› Each thread deals with workload in a well-balanced manner

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Semidefinite Programming

t Input: parameter matrix T t Output: variable matrix X

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Segment costs Via costs

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Example

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t Segments S1 and S2 t 4 layers:

› Layer 1 and 3 for x-dimension › Layer 2 and 4 for y-dimension

t Post mapping strategy provides integer solutions

  • S1

S2 T(M1): 35.2

  • S1

S2 T(M3): 15.6

  • S1

S2 T(M2): 47.8

  • S1

S2 T(M4): 23.9

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Experimental Results

t Implemented the framework in C++ t ILP solver -- GUROBI t SDP solver – CSDP t Parallel implementation – OpenMP t Evaluation on ISPD’08 global routing benchmarks t Performance Metrics

› Average Critical Path Timing › Worst Critical Path Timing › # of Via capacity violation › # of Via

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Evaluation on ISPD’08 Benchmarks

t Initial global routing input:

› Generated by NCTU-GR 2.0 [Liu et al. TCAD’13]

t Initial layer assignment:

› From NVM [Liu et al. ASPDAC’11] › Targeting via number and overflow minimization

t Wire resistance and capacitance values obtained from

industry settings

t Release 0.5% critical and non-critical nets t Compared with TILA [Yu et al. ICCAD’15]

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Delay Comparison Results

t ISPD’08 Global Routing Benchmarks

› 14% improvement in Avg(Tcp) › 4% improvement in Max(Tcp)

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Via Comparison Results

t ISPD’08 Global Routing Benchmarks

› Via Overflow (#OV) decreases by 10% › Similar number of vias

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Conclusion

t Propose Incremental Layer Assignment for Critical Path

Timing (CPLA) algorithm

› Self-adaptive partition provides balanced workload for multiple threads and potential speed-up › Semidefinite programming (SDP) relaxation › Post mapping satisfies constraints

t CPLA suitable for future heterogeneous layer structures

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Overview

t Introduction t Problem Formulation t Algorithms t Experimental Results t Conclusion

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Model Description

t Elmore timing model:

› Consider both segment delay and via delay

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Sink

s3 s2 s1 s4 v1 Maximum Path Delay: t(s1) + t(s2) + t(s3) + t(s4) + t(v1)

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Partition Size Impact

t Different number of segments in each partition

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Impact on Avg(Tcp); Impact on Max(Tcp); Impact on runtime

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Mapping Algorithm

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t Provide integer solutions

› For each edge with critical nets:

Find the current highest layer j to assign segments cap(j) = allowable number

  • f segments to assign

Finish all layers? Assign these segments

  • n layer j of edge

Select cap(j) segments with highest solutions Y N Exit