IIT Bombay CDEEP Autumn 2009 Introduction to Programmable Logic - - PowerPoint PPT Presentation

IIT Bombay

EE705/707 Lectures No. 23 and 24 Prof. M. Shojaei Baghini

Introduction to Programmable Logic Design Flow

CDEEP Autumn 2009

Presented by- Anil Powai Labs Tech. Pvt. Ltd.

IIT Bombay

EE705/707 Lectures No. 23 and 24 Prof. M. Shojaei Baghini

Programmable Logic Devices

• PLAs (programmable logic array):

– Two level structures of AND and OR gates with user programmable connections – Architecture not scalable; Power consumption and delays play an important role in extending the architecture to complex designs – Implementation of larger designs leads to same difficulty as that of discrete components

IIT Bombay

EE705/707 Lectures No. 23 and 24 Prof. M. Shojaei Baghini

Programmable Logic Devices

• For high capacity

– A complex PLD (CPLD) is a collection of multiple PLDs and an interconnection structure. – FPGA (Field Programmable Logic Devices) contains a much larger number of smaller individual blocks + large interconnection structure

– Customized by end user – Implements multi-level logic function – Fast time to market and low risk

IIT Bombay

EE705/707 Lectures No. 23 and 24 Prof. M. Shojaei Baghini

FPGA – A Quick Look

• Two dimensional array of customizable logic block

placed in an interconnect array.

• Programmable at users site.
• Implements thousands of gates of logic in a single

device

– Employs logic and interconnect structure capable of implementing multi-level logic

IIT Bombay

EE705/707 Lectures No. 23 and 24 Prof. M. Shojaei Baghini

FPGA – A Detailed Look

• FPGA is a programmable logic chip that consists of an

array of multiple logic elements usually in form of RAM- controlled Look-up Tables (LUT).

• Interconnection framework comprises of wire segments

and switches; Provide a means to interconnect logic blocks.

• Circuits are partitioned to logic block size, mapped and

routed.

IIT Bombay

EE705/707 Lectures No. 23 and 24 Prof. M. Shojaei Baghini

FPGA Architecture

(Simplified Diagram)

• Basic building block

IIT Bombay

EE705/707 Lectures No. 23 and 24 Prof. M. Shojaei Baghini

In p u t s(A B CD ) O u t p u t (Z ) 1 1 1 1 1 … … .. 1 1 1 1 1 1 1 1 1

Truth Table

LUT

=

4-input logic function C

D

Z A B

Four-Input LUT

• Implements

combinatorial logic

– Any 4-input logic function – Cascaded for wide-input functions

IIT Bombay

EE705/707 Lectures No. 23 and 24 Prof. M. Shojaei Baghini

Interconnection Framework

3 types:

• Fast Direct Connections
• General Purpose connections

with Switching Matrix

• Horizontal/Vertical Long Lines

Types of lines:

• Single length
• Long lines
• Global lines

IIT Bombay

EE705/707 Lectures No. 23 and 24 Prof. M. Shojaei Baghini

Programmable Switch Matrix

IIT Bombay

EE705/707 Lectures No. 23 and 24 Prof. M. Shojaei Baghini

Detail view of inside wiring

IIT Bombay

EE705/707 Lectures No. 23 and 24 Prof. M. Shojaei Baghini

Field Programmability

• Field programmability is achieved

through switches (Transistors controlled by memory elements or fuses)

• Switches control the following aspects
• Interconnection among wire segments
• Configuration of logic blocks
• Distributed memory elements controlling

the switches and configuration of logic blocks are together called “Configuration Memory”

IIT Bombay

EE705/707 Lectures No. 23 and 24 Prof. M. Shojaei Baghini

SRAM Programming Technology

• Employs SRAM (Static RAM)

cells to control pass transistors and/or transmission gates

• SRAM cells control the

configuration of logic block as well

• Volatile

– Needs an external storage – Needs a power-on configuration mechanism – In-circuit re-programmable

• Lesser configuration time
• Occupies relatively larger area

IIT Bombay

EE705/707 Lectures No. 23 and 24 Prof. M. Shojaei Baghini

FPGA Modes

• Configuration mode:

– Power ON Mode, – Used to configure the FPGA.

• User Mode:

– Once configuration is complete, the FPGA goes into "user mode", its main mode of operation, where the programmed circuit actually starts functioning.

IIT Bombay

EE705/707 Lectures No. 23 and 24 Prof. M. Shojaei Baghini

Design Steps Involved in Designing With FPGAs

• Understand and define design

requirements

• Design description
• Behavioural simulation (Source

code interpretation)

• Synthesis
• Functional or Gate level

simulation

• Implementation
• Fitting
• Place and Route
• Timing or Post layout simulation
• Programming, Test and Debug

IIT Bombay

EE705/707 Lectures No. 23 and 24 Prof. M. Shojaei Baghini

Design Entry

• Design entry is the media through which specifications are entered into

the soft format.

• There are various ways in which the design can be entered. Some of the

popular one’s are: – Designing with the help of schematics. – Designing using HDL’S [Hardware Description Language].

• VHDL logic description

– VHDL= Very High Speed Integrated Circuit Hardware Description Language is used to describe the desired logic circuit.

• Verilog logic description .

IIT Bombay

EE705/707 Lectures No. 23 and 24 Prof. M. Shojaei Baghini

Multiplexor: Design Entry

specifications ip 1 ip 2 ip 3 ip 4 s1 s0 y d0 d1 d2 d3 d0 1 d1 1 d2 1 1 d3

IIT Bombay

EE705/707 Lectures No. 23 and 24 Prof. M. Shojaei Baghini

Synthesis

• Synthesis is a process of converting HDL code

into equivalent logic gates. Inputs to this process are

– Design description – Target technology – Constraints

• Results of the synthesis process are netlist (.ngc)

and synthesis reports.

• Tool can be directed to generate post synthesis

simulation model and RTL view.

IIT Bombay

EE705/707 Lectures No. 23 and 24 Prof. M. Shojaei Baghini

Synthesis : Xst

IIT Bombay

EE705/707 Lectures No. 23 and 24 Prof. M. Shojaei Baghini

Implementation

• Implementation includes many phases

– Translate: Merge multiple design files into a single netlist – Map: Group logical symbols from the netlist (gates) into physical components (CLBs and IOBs) – Place & Route: Place components

• nto the chip, connect them, and

extract timing data into reports.

• Timing Simulation is carried out after

place & route , gate delays and interconnect delays can be involved in this simulation.

IIT Bombay

EE705/707 Lectures No. 23 and 24 Prof. M. Shojaei Baghini

Programming

• The BIT file can be downloaded

directly to the FPGA, or can be converted into a PROM file which stores the programming information

• There are two ways to program an

FPGA – Through a PROM device

• You will need to generate a file that

the PROM programmer will understand

– Directly from the computer

• Use the iMPACT configuration tool

IIT Bombay

EE705/707 Lectures No. 23 and 24 Prof. M. Shojaei Baghini

Demonstration of Xilinx ISE tool

• Two examples are used to

demonstrates Xilinx ISE to synthesize flow.

– Multiplexor – Finite State Machine

IIT Bombay

EE705/707 Lectures No. 23 and 24 Prof. M. Shojaei Baghini

Multiplexor example

• Creating a new project

– To invoke ISE-

• $ ise &
• Xilinx Project Navigator window will open

– To create new project

• Go to menu File/New Project to open New Project

Wizard

• Provide information such as ‘Project Name’, ‘Project

Path’ & ‘Top Level Source Type’

IIT Bombay

EE705/707 Lectures No. 23 and 24 Prof. M. Shojaei Baghini

Creating a new project

IIT Bombay

EE705/707 Lectures No. 23 and 24 Prof. M. Shojaei Baghini

Assigning Target Device

IIT Bombay

EE705/707 Lectures No. 23 and 24 Prof. M. Shojaei Baghini

Adding source files

IIT Bombay

EE705/707 Lectures No. 23 and 24 Prof. M. Shojaei Baghini

Specifying Pin Locations

• Processes > User

Constraints>Assign Package Pins

IIT Bombay

EE705/707 Lectures No. 23 and 24 Prof. M. Shojaei Baghini

Synthesis/Implementation

• Running Design

Synthesis and Implementation – Processes: Synthesize- XST – Processes: Implement Design

IIT Bombay

EE705/707 Lectures No. 23 and 24 Prof. M. Shojaei Baghini

Viewing Schematic

• Viewing RTL schematic

– Processes/Synthesize-XST/View RTL Schematic.

• Viewing Technology schematic

– Processes/Synthesize-XST/View Technology Schematic.

IIT Bombay

EE705/707 Lectures No. 23 and 24 Prof. M. Shojaei Baghini

Synthesis Reports

• Viewing Device

Utilization and Timing summary. – Processes/Synthesiz e-XST/View Synthesis Report.

IIT Bombay

EE705/707 Lectures No. 23 and 24 Prof. M. Shojaei Baghini

Design verification

• Design Verification at different step
• f Xilinx ISE flow.

– RTL simulation after Design description in Hardware description language. – Post synthesis simulation – Post Place & route simulation(Timing simulation).

IIT Bombay

EE705/707 Lectures No. 23 and 24 Prof. M. Shojaei Baghini

RTL simulation

• RTL Simulation is carried out for

checking the design behaviour with respect to design specifications.

– A test-bench (it can also be described in HDL) is used to generates input stimulus to design. – Any standard simulator can be used to simulate the design under test and dumped the simulation results into a standard format (which can be viewed using waveform viewer).

IIT Bombay

EE705/707 Lectures No. 23 and 24 Prof. M. Shojaei Baghini

Simulation results

IIT Bombay

EE705/707 Lectures No. 23 and 24 Prof. M. Shojaei Baghini

Post synthesis simulation

• After completion of design synthesis process

post synthesis simulation model (HDL model) can be generated.

– Processes: Synthesis-Xst/Generate Post-synthesis Simulation Model. (Properties can be modifies for VHDL

• r Verilog representation of model).
• Model will be present in Xilinx project.

– mux/netgen/synthesis/mux_synthesis.vhd

• HDL model is used for simulation using simulator

and corresponding test bench.

IIT Bombay

EE705/707 Lectures No. 23 and 24 Prof. M. Shojaei Baghini

Post P & R simulation

• After completion of P & R process post place & Route

simulation model (HDL model) can be generated. – Processes: Implement Design/Place & Route/Generate Post-Place & Route Simulation

• Model. (Properties can be modifies for VHDL or

Verilog representation of model).

• HDL model and Standard delay format file will be

present in Xilinx project. – mux/netgen/Par/mux_timesim.vhd – mux/netgen/Par/mux_timesim.sdf

• HDL model & SDF file are used for timing simulation.

IIT Bombay

EE705/707 Lectures No. 23 and 24 Prof. M. Shojaei Baghini

Finite State Machine example

• Follow the same procedure as described before

for multiplexor example. – Create a new project – Assign Target Device and Pin Locations. – Synthesis/Implemenation

• Timing constraints can be provided to synthesis

and Implementation process.

IIT Bombay

EE705/707 Lectures No. 23 and 24 Prof. M. Shojaei Baghini

Finite State Machine example

• Timing constraints can be given as below:

– Processes> User Constraints>Create Timing Constraints

• Global constraints:

– Period – Pad to Setup – Clock to pad

• Port Constraints

– Pad to setup for inputs – Clock to pad for outputs

IIT Bombay

EE705/707 Lectures No. 23 and 24 Prof. M. Shojaei Baghini

Global Timing Constraints

IIT Bombay

EE705/707 Lectures No. 23 and 24 Prof. M. Shojaei Baghini

In put Port Constraints

IIT Bombay

EE705/707 Lectures No. 23 and 24 Prof. M. Shojaei Baghini

Out put Port Constraints

IIT Bombay

EE705/707 Lectures No. 23 and 24 Prof. M. Shojaei Baghini

Advanced analysis tools - Floorplaner

• Floor planer –

displays placed design.

• You can check

where each block of the design was placed.

IIT Bombay

EE705/707 Lectures No. 23 and 24 Prof. M. Shojaei Baghini

Advanced analysis tools – FPGA Editor

• FPGA Editor displays placed and routed design.
• Implementation of each cell can be viewed

IIT Bombay

EE705/707 Lectures No. 23 and 24 Prof. M. Shojaei Baghini

If the fanout is beyond a limit the tool will insert buffers, which will reduce the speed further.

if clk’event and clk = ‘1’ then a <= c and d; end if; if (a = “11”) then . . . if (x = a) then . . . case a is . . . When “00” => . . . when “01” => . . . x <= a and b; . . .

Synthesis Constraints: Fanout Control

IIT Bombay

EE705/707 Lectures No. 23 and 24 Prof. M. Shojaei Baghini

if clk’event and clk = ‘1’ then a <= c and d; a1 <= c and d; end if; if (a = “11”) then . . . if (x = a) then . . . case a1 is . . . When “00” => . . . when “01” => . . . x <= a and b; . . .

Synthesis Constraints : Fanout Control

Fanout control can be done at RTL level or by the tool, during synthesis

IIT Bombay

EE705/707 Lectures No. 23 and 24 Prof. M. Shojaei Baghini

Synthesis Constraints : Resource sharing

z <= a + b when x = ‘1’ else c + d;

Z MUX X MUX X

A C B D

+

MUX

+ +

A B C D

X Z

Some tools have automatic resource sharing. Operations must be mutually exclusive. temp1 <= a when x = ‘1’ else c; temp2 <= b when x = ‘1’ else d; z <= temp1 + temp2;

IIT Bombay

EE705/707 Lectures No. 23 and 24 Prof. M. Shojaei Baghini

if CONTROL = '1' then PTR := PTR1; else PTR := PTR2; end if; OFFSET := BASE - PTR; ADDR := ADDRESS - ("00000000" & OFFSET); COUNT <= ADDR + B; Here control is a late arriving signal and timing is not being met.

Synthesis Constraints : Logic duplication

IIT Bombay

EE705/707 Lectures No. 23 and 24 Prof. M. Shojaei Baghini

OFFSET1 := BASE - PTR1; OFFSET2 := BASE - PTR2; ADDR1 := ADDRESS - ("00000000" & OFFSET1); ADDR2 := ADDRESS - ("00000000" & OFFSET2); COUNT1 := ADDR1 + B; COUNT2 := ADDR2 + B; if CONTROL = '1' then COUNT <= COUNT1; else COUNT <= COUNT2; end if;

Synthesis Constraints : Logic duplication

IIT Bombay

EE705/707 Lectures No. 23 and 24 Prof. M. Shojaei Baghini

REFERENCES

• 1. XST – Xilinx Synthesis Technology User Guide.
• 2. Actel HDL Coding style guide
• 3. ISE – Quick start tutorial.

IIT Bombay

EE705/707 Lectures No. 23 and 24 Prof. M. Shojaei Baghini

Thank you