IIT Bombay CDEEP Autumn 2009 Introduction to Programmable Logic Design Flow Presented by- Anil Powai Labs Tech. Pvt. Ltd. EE705/707 Lectures No. 23 and 24 Prof. M. Shojaei Baghini
IIT Bombay Programmable Logic Devices • PLAs (programmable logic array): – Two level structures of AND and OR gates with user programmable connections – Architecture not scalable; Power consumption and delays play an important role in extending the architecture to complex designs – Implementation of larger designs leads to same difficulty as that of discrete components EE705/707 Lectures No. 23 and 24 Prof. M. Shojaei Baghini
IIT Bombay Programmable Logic Devices • For high capacity – A complex PLD (CPLD) is a collection of multiple PLDs and an interconnection structure. – FPGA (Field Programmable Logic Devices) contains a much larger number of smaller individual blocks + large interconnection structure – Customized by end user – Implements multi-level logic function – Fast time to market and low risk EE705/707 Lectures No. 23 and 24 Prof. M. Shojaei Baghini
IIT Bombay FPGA – A Quick Look • Two dimensional array of customizable logic block placed in an interconnect array. • Programmable at users site. • Implements thousands of gates of logic in a single device – Employs logic and interconnect structure capable of implementing multi-level logic EE705/707 Lectures No. 23 and 24 Prof. M. Shojaei Baghini
IIT Bombay FPGA – A Detailed Look • FPGA is a programmable logic chip that consists of an array of multiple logic elements usually in form of RAM- controlled Look-up Tables (LUT). • Interconnection framework comprises of wire segments and switches; Provide a means to interconnect logic blocks. • Circuits are partitioned to logic block size, mapped and routed. EE705/707 Lectures No. 23 and 24 Prof. M. Shojaei Baghini
IIT Bombay FPGA Architecture (Simplified Diagram) • Basic building block EE705/707 Lectures No. 23 and 24 Prof. M. Shojaei Baghini
IIT Bombay Four-Input LUT Truth Table • Implements In p u t s(A B CD ) O u t p u t (Z ) combinatorial logic 0 0 0 0 0 – Any 4-input logic 0 0 0 1 0 0 0 1 0 1 function 0 0 1 1 0 – Cascaded for wide-input … … .. functions 1 1 1 0 1 1 1 1 1 1 4-input logic function A = LUT B Z C D EE705/707 Lectures No. 23 and 24 Prof. M. Shojaei Baghini
IIT Bombay Interconnection Framework 3 types: • Fast Direct Connections • General Purpose connections with Switching Matrix • Horizontal/Vertical Long Lines Types of lines: • Single length • Long lines • Global lines EE705/707 Lectures No. 23 and 24 Prof. M. Shojaei Baghini
IIT Bombay Programmable Switch Matrix EE705/707 Lectures No. 23 and 24 Prof. M. Shojaei Baghini
IIT Bombay Detail view of inside wiring EE705/707 Lectures No. 23 and 24 Prof. M. Shojaei Baghini
IIT Bombay Field Programmability • Field programmability is achieved through switches (Transistors controlled by memory elements or fuses) • Switches control the following aspects • Interconnection among wire segments • Configuration of logic blocks • Distributed memory elements controlling the switches and configuration of logic blocks are together called “Configuration Memory” EE705/707 Lectures No. 23 and 24 Prof. M. Shojaei Baghini
IIT Bombay SRAM Programming Technology • Employs SRAM (Static RAM) cells to control pass transistors and/or transmission gates • SRAM cells control the configuration of logic block as well • Volatile – Needs an external storage – Needs a power-on configuration mechanism – In-circuit re-programmable • Lesser configuration time • Occupies relatively larger area EE705/707 Lectures No. 23 and 24 Prof. M. Shojaei Baghini
IIT Bombay FPGA Modes • Configuration mode: – Power ON Mode, – Used to configure the FPGA. • User Mode: – Once configuration is complete, the FPGA goes into "user mode", its main mode of operation, where the programmed circuit actually starts functioning. EE705/707 Lectures No. 23 and 24 Prof. M. Shojaei Baghini
IIT Bombay Design Steps Involved in Designing With FPGAs Understand and define design requirements Design description Behavioural simulation (Source code interpretation) Synthesis Functional or Gate level simulation Implementation Fitting Place and Route Timing or Post layout simulation Programming, Test and Debug EE705/707 Lectures No. 23 and 24 Prof. M. Shojaei Baghini
IIT Bombay Design Entry • Design entry is the media through which specifications are entered into the soft format. • There are various ways in which the design can be entered. Some of the popular one’s are: – Designing with the help of schematics. – Designing using HDL’S [Hardware Description Language]. • VHDL logic description – VHDL= Very High Speed Integrated Circuit Hardware Description Language is used to describe the desired logic circuit. • Verilog logic description . EE705/707 Lectures No. 23 and 24 Prof. M. Shojaei Baghini
IIT Bombay Multiplexor: Design Entry specifications ip ip ip ip s1 s0 y 1 2 3 4 0 0 d0 0 1 d1 d0 d1 d2 d3 1 0 d2 1 1 d3 EE705/707 Lectures No. 23 and 24 Prof. M. Shojaei Baghini
IIT Bombay Synthesis • Synthesis is a process of converting HDL code into equivalent logic gates. Inputs to this process are – Design description – Target technology – Constraints • Results of the synthesis process are netlist (.ngc) and synthesis reports. • Tool can be directed to generate post synthesis simulation model and RTL view. EE705/707 Lectures No. 23 and 24 Prof. M. Shojaei Baghini
IIT Bombay Synthesis : Xst EE705/707 Lectures No. 23 and 24 Prof. M. Shojaei Baghini
IIT Bombay Implementation • Implementation includes many phases – Translate: Merge multiple design files into a single netlist – Map: Group logical symbols from the netlist (gates) into physical components (CLBs and IOBs) – Place & Route: Place components onto the chip, connect them, and extract timing data into reports. • Timing Simulation is carried out after place & route , gate delays and interconnect delays can be involved in this simulation. EE705/707 Lectures No. 23 and 24 Prof. M. Shojaei Baghini
IIT Bombay Programming • The BIT file can be downloaded directly to the FPGA, or can be converted into a PROM file which stores the programming information • There are two ways to program an FPGA – Through a PROM device • You will need to generate a file that the PROM programmer will understand – Directly from the computer • Use the iMPACT configuration tool EE705/707 Lectures No. 23 and 24 Prof. M. Shojaei Baghini
IIT Bombay Demonstration of Xilinx ISE tool • Two examples are used to demonstrates Xilinx ISE to synthesize flow. – Multiplexor – Finite State Machine EE705/707 Lectures No. 23 and 24 Prof. M. Shojaei Baghini
IIT Bombay Multiplexor example • Creating a new project – To invoke ISE- • $ ise & • Xilinx Project Navigator window will open – To create new project • Go to menu File/New Project to open New Project Wizard • Provide information such as ‘Project Name’, ‘Project Path’ & ‘Top Level Source Type’ EE705/707 Lectures No. 23 and 24 Prof. M. Shojaei Baghini
IIT Bombay Creating a new project EE705/707 Lectures No. 23 and 24 Prof. M. Shojaei Baghini
IIT Bombay Assigning Target Device EE705/707 Lectures No. 23 and 24 Prof. M. Shojaei Baghini
IIT Bombay Adding source files EE705/707 Lectures No. 23 and 24 Prof. M. Shojaei Baghini
IIT Bombay Specifying Pin Locations • Processes > User Constraints>Assign Package Pins EE705/707 Lectures No. 23 and 24 Prof. M. Shojaei Baghini
IIT Bombay Synthesis/Implementation • Running Design Synthesis and Implementation – Processes: Synthesize- XST – Processes: Implement Design EE705/707 Lectures No. 23 and 24 Prof. M. Shojaei Baghini
IIT Bombay Viewing Schematic • Viewing RTL schematic – Processes/Synthesize-XST/View RTL Schematic. • Viewing Technology schematic – Processes/Synthesize-XST/View Technology Schematic. EE705/707 Lectures No. 23 and 24 Prof. M. Shojaei Baghini
IIT Bombay Synthesis Reports • Viewing Device Utilization and Timing summary. – Processes/Synthesiz e-XST/View Synthesis Report . EE705/707 Lectures No. 23 and 24 Prof. M. Shojaei Baghini
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