IIT Bombay CDEEP Autumn 2009 Logic Simulation- Part II Elements - - PowerPoint PPT Presentation

IIT Bombay

EE705/707 Lecture No. 19 Prof. Maryam Shojaei Baghini

Logic Simulation- Part II Elements of VHDL

CDEEP Autumn 2009

Presented by- Anil Powai Labs Tech. Pvt. Ltd.

IIT Bombay

EE705/707 Lecture No. 19 Prof. Maryam Shojaei Baghini

A Brief History Of VHDL

• VHDL stands for Very high speed integrated circuit

Hardware Description Language

• Funded by the US Department of Defence in the 70's and

80's

• Originally meant for design standardisation,

documentation, simulation and ease of maintenance.

• Established as IEEE standard IEEE 1076 in 1987. An

updated standard, IEEE 1164 was adopted in 1993. In 1996 IEEE 1076.3 became a VHDL synthesis standard.

• Today VHDL is widely used across the industry for design

description, simulation and synthesis.

IIT Bombay

EE705/707 Lecture No. 19 Prof. Maryam Shojaei Baghini

Basic of VHDL

• Entity

– A design’s interface signals to the external circuitry.

• Architecture

– Describes a design’s behavior and functionality.

• Configuration

– Binds an entity to an architecture when there are multiple architectures for a single entity.

• Package

– Contains frequently used declarations, constants, functions, procedures, user data types and components.

• Library

– Consists of all the compiled design units like entities, architectures, packages and configurations

IIT Bombay

EE705/707 Lecture No. 19 Prof. Maryam Shojaei Baghini

• - comment

library IEEE; use IEEE.std_logic_1164.all; entity xor_gate is generic (p_delay : time:= 2 ns); port (ip1 : in std_logic; ip2 : in std_logic;

• p1 : out std_logic

); end xor_gate; entity - defines the Interface.

XOR gate

Mode of the port :Direction of flow. Entity name –> xor_gate Port name –> ip1, ip2, op1 Port type –> std_logic

Syntax entity entity_name is [generic generic_name : data_type [:= initial value ]] [port port_name : port_direction data_type] [declarations] [begin statements] end entity_name;

Generic : for passing parameter

IIT Bombay

EE705/707 Lecture No. 19 Prof. Maryam Shojaei Baghini library IEEE; use IEEE.std_logic_1164.all; entity xor_gate is

generic (p_delay : time:= 2 ns);

port (ip1 : in std_logic; ip2 : in std_logic;

• p1 : out std_logic

); end xor_gate;

Mode of the port : It can be in, out or inout Std_logic is the type of the port. It is defined in the std_logic_1164 package (present in IEEE library) std_logic can take 9 different values. ‘0’ , ’1’ , ’L’ , ’H’ , ’Z’ , ’U’ , ’X’ , ’W’ , ’-’

XOR gate

Type ‘time’ is defined in package STANDARD in library STD which need not to be declare Before accessing any unit in a library it needs to be declared . STD and WORK need not be declared . Library syntax is :- library library_name ; use library_name.package_name.item_name ; components declared inside a library can be accessed by the ‘USE’ statement

IIT Bombay

EE705/707 Lecture No. 19 Prof. Maryam Shojaei Baghini

library IEEE; use IEEE.std_logic_1164.all; entity xor_gate is generic (p_delay : time:= 2 ns); port (ip1 : in std_logic; ip2 : in std_logic;

• p1 : out std_logic

); end xor_gate; architecture xor_gate_beh of xor_gate is begin

• p1 <= ip1 xor ip2 after p_delay;

end xor_gate_beh;

The architecture describes the

• behavior of design,
• relationship between different inputs and
• utputs of the entity.
• Interconnections between the components

(for structural design)

XOR_gate

‘xor’ is function defined in std_logic_1164 package.

architecture architecture_name of entity_name is [declarations] begin [statements] end [ architecture_name ];

IIT Bombay

EE705/707 Lecture No. 19 Prof. Maryam Shojaei Baghini

architecture xor_gate_beh1 of xor_gate is signal temp1 : std_logic; signal temp2 : std_logic; begin temp1 <= ip1 and (not ip2) after p_delay ; temp2 <= ip2 and (not ip1) after p_delay;

• p1 <= temp1 or temp2 after p_delay ;

end xor_gate_beh1;

One more architecture for entity ‘xor_gate’ using internal signals

IIT Bombay

EE705/707 Lecture No. 19 Prof. Maryam Shojaei Baghini

configuration xor_gate_C of xor_gate is for xor_gate_beh end for; end xor_gate_C; configuration xor_gate_C1 of xor_gate is for xor_gate_beh1 end for; end xor_gate_C1; A configuration statement selects one

• f several architectures for a single

entity. Components within architectures can also be chosen. Unless specified, the last compiled architecture is used for simulation

configuration configuration_name of entity_name is for architecture_name for instance_name:component_name use entity library_name.entity_name(architecture_name); end for; end for; end configuration_name;

IIT Bombay

EE705/707 Lecture No. 19 Prof. Maryam Shojaei Baghini To test a circuit we will design another circuit (test bench) which will generate the signals required to test our circuit. This new circuit is also described in VHDL.

ip1 ip2

• p

1 XOR_GATE

Test Process

XOR_GATE_TS T

Test Benches should be as simple as possible

Test Benches.

IIT Bombay

EE705/707 Lecture No. 19 Prof. Maryam Shojaei Baghini

XOR_GATE

XOR_GATE_TST Test process

ip1_s ip2_s

• p1_s

entity xor_gate_tst is end xor_gate_tst;

IIT Bombay

EE705/707 Lecture No. 19 Prof. Maryam Shojaei Baghini

entity xor_gate_tst is generic (p_delay_top : time:= 4 ns); end xor_gate_tst; architecture xor_gate_tst_A of xor_gate_tst is component xor_gate generic (p_delay : time:= 2 ns); port (ip1 : in std_logic; ip2 : in std_logic;

• p1 : out std_logic);

end component; signal ip1_s, ip2_s, op1_s : std_logic; begin U1: xor_gate generic map (p_delay => P_delay_top) port map( ip1 => ip1_s, ip2 => ip2_s,

• p1 => op1_s );

........ end xor_gate_tst_A;

XOR_GATE

XOR_GATE_TST

Test process ip1_s ip2_s

• p1_s

COMPONENT INSTANTIATIO N

IIT Bombay

EE705/707 Lecture No. 19 Prof. Maryam Shojaei Baghini

ModelSim Demonstration

• Creating Project
• Code entry and compilation
• Loading the test bench
• The object window
• Running basic simulation
• The wave window
• Simulation debugging

IIT Bombay

EE705/707 Lecture No. 19 Prof. Maryam Shojaei Baghini

REFERENCES

• 1. IEEE Standard VHDL - Language Reference Manual.
• 2. VHDL Programming by Example 4th Ed - Douglas

Perry.

• 3. The Designer's Guide to VHDL- Peter J. Ashenden

IIT Bombay

EE705/707 Lecture No. 19 Prof. Maryam Shojaei Baghini

Thank you