III-V Nanoelectronics for Energy Efficient Information Processing - - PowerPoint PPT Presentation

III-V Nanoelectronics for Energy Efficient Information Processing

PhD Students: Vinay Saripalli (Intel), Dheeraj Mohata, Bijesh R., Mike Barth, Ashkar Ali Suman Datta Electrical Engineering Materials Research Institute (MRI)

March 01, 2012

Energy Efficiency

• Near threshold voltage (NTV) computing achieves

highest energy efficiency

• Can III-V nanoelectronics be employed to enhance

transistor characteristics targeted for NTV computing

Variable precision floating point unit processor

• n 32nm CMOS (Source Intel: ISSCC 2012)

Emerging Nano Devices

• Leverage emerging Nano devices for advanced, extended

and beyond CMOS for energy efficiency

Ge / InGaAs / InSb FINFETs

Enhanced CMOS Extended CMOS Beyond CMOS State of the Art CMOS

NTV Computing Devices

1E12 1E13 10

1

10

2

10

3

Si PMOS

Hole Mobility [cm

2/Vs]

Carrier Density [/cm

2]

Ga0.6In0.4Sb QW Layers

7x

Stanford, NRL (IEDM '09)

1E12 1E13 10

1

10

2

10

3

10

4

10

5

Si NMOS

Electron Mobility [cm

2/Vs]

Carrier Density [/cm

2]

InAs1-xSbx QW Layers

60x

Penn State, NRL (IEDM '10) x=0.2-0.3

Antimonide III-V CMOS

• InAs1-xSbx QW electron mobility ~ 13,000 cm2/Vs (60x over Si)
• GaxIn1-xSb QW hole mobility ~ 850 cm2/Vs (7x over Si)
• Promising for low power, high-performance III-V CMOS logic

InGaSb QW S.I. GaAs Nucleation and Buffer Layer Al0.8Ga0.2Sb buffer (Unified Buffer for NMOS and PMOS) InAsSb QW High-κ G S D NMOS High-κ G S D PMOS Isolation

InAlSb Barrier InAlSb Barrier

InAlSb Barrier InAlSb Barrier

4o(100) Offcut Si Substrate

ILD

Shared Metamorphic Buffer

• M. Hudait, S. Datta, R. Chau et al.; US Patent No. 7429747
• Antimonide NMOS and PMOS have similar lattice constants
• Can be grown on the same buffer

Promising for III-V CMOS

Outline

• Device Layer Design
• Dielectric Integration Strategy
• Device Transport Characterization

– Long Channel Mobility – Short Channel Velocity

• Gate Stack Scalability

– Quantum Capacitance Effects

• Conclusions

Substrate Mismatch Accommodation Layer High Mobility QW Bottom Barrier Layer δ-doped Barrier Work Function Engineered S/D Metal High-k gate oxide Work Function Engineered Gate Metal Work Function Engineered S/D Metal

Device Architecture for Ultra-low VDD Logic

Quantum Well Device Layer Design

• InAs0.8Sb0.2 quantum well device layer was modified to incorporate an ultra-

thin GaSb cap layer for dielectric integration

• Any parallel channel in the device ?

GaSb Cap: 2.5 nm Al0.8In0.2Sb Barrier: 9 nm InAs0.8Sb0.2 Channel: 12 nm Al0.8Ga.2Sb Buffer 5nm Al0.8Ga.2Sb Buffer GaAs Substrate QW Device Layers

1.5 µm

Device layers grown by Brian R. Bennett, NRL

Quantitative Mobility Spectrum Analysis

• Higher conductivity peak corresponds to InAs0.8Sb0.2 QW
• No dominant parasitic channel in the device layers

10 20 30 40

• 0.8
• 0.4

0.0 0.4 0.8

EF E1 Al0.8In0.2Sb GaSb

Energy [eV] Distance [nm]

Al0.8In0.2Sb InAs0.8Sb0.2 Al0.8Ga0.2Sb

Te δ−doping

E0

0.3eV

(a)

10

• 6

10

• 4

10

• 2

10

• 6

10

• 4

10

• 2

10

2

10

3

10

4

10

5

10

6

10

• 6

10

• 4

10

• 2

electrons holes 300K 2DEG 2DEG 2DEG 200K

Conductivity [/Ω]

77K

Mobility [cm

2/Vs]

Hall Mobility and Scattering Analysis

10 100 10

4

10

5

10

6

µ

Interface Charge

µ

Model

µ

Experiment

µ

POP

µ

ADP

µ

Interface Roughness

µ

Remote Ionized Impurity

µ

Alloy

Mobility [cm

2/Vs]

Temperature [K]

• Electron mobility of 13,000 cm2/Vs at 300K (Ns=2.2 x 1012 /cm2)
• Coulomb scattering due to interface charge limits transport

Interface Charge Polar Optical Phonon Remote Ionized Impurity Acoustic Phonon Alloy Disorder Interface Roughness

10 20 30 40 50

% Contribution to 1/µ

T=300K

Ultra-thin GaSb Cap Layer on InAlSb Barrier Enables High-κ Dielectric Integration

• High Al content barrier oxidizes in air giving rise to surface pitting during surface

preparation prior to high-κ deposition

• GaSb cap layer on InAlSb barrier enables high-κ dielectric integration

Surface clean on device layers with InAlSb surface Surface clean on device layers with GaSb cap on InAlSb barrier

300 nm

0.4 0.6 0.8 1.0 1.2

75kHz to 2MHz

300K

Capacitance [µFcm

• 2]

300K

• 2 -1

1 2 0.4 0.6 0.8 1.0 1.2

250K

Gate Voltage [V]

( )

• 2 -1

1 2

250K

n-GaSb MOSCAPs

Gate (Pd/Au)

n-GaSb (Te doping) ND=1x1018 /cm3 5nm Al2O3

Low Temp Plasma Enhanced ALD

• Plasma Enhanced ALD MOSCAPs show good Fermi level modulation

High Temp ALD

p-GaSb MOSCAPs

0.4 0.6 0.8 1.0 1.2

75kHz to 2MHz

300K

Capacitance [µFcm

• 2]

300K

• 2 -1

1 2 0.4 0.6 0.8 1.0 1.2

200K

Gate Voltage [V]

• 2 -1

1 2

200K

Gate (Pd/Au)

p-GaSb (unintentional doping) NA=1x1018 /cm3 5nm Al2O3

High Temp ALD Low Temp Plasma Enhanced ALD

• Plasma Enhanced ALD MOSCAPs show good Fermi level modulation

0.0 0.2 0.4 0.6 0.8 10

12

10

13

Dit [/cm

2/eV]

E-EV [eV]

Interface State Density (Dit)

High Temp ALD Low Temp PEALD

Dit extracted from multi-temperature CV/GV analysis of n&p GaSb MOSCAPs

• Low Dit near EV of GaSb for PEALD Good Sb QW NMOS turn off
• High Dit towards midgap Likely affect drive current

Fermi Level movement at high-κ/GaSb interface for Sb QW MOSFET ON-OFF

10 20 30

• 1.0
• 0.5

0.0 0.5 1.0

GaSb Oxide

E

2

E

1

Buffer QW Barrier

E

F

E

V

Energy [eV] Distance [nm]

E

C

Sb QW MOSFET ON-State

10 20 30

• 0.5

0.0 0.5 1.0 1.5

GaSb Oxide

E

2

E

1

Buffer QW Barrier

E

F

E

V

Energy [eV] Distance [nm]

E

C

Sb QW MOSFET OFF-State

• 1

1 0.5 1.0 1.5 2.0 2.5 3.0 Capacitance [µF/cm

2]

75 kHz to 2MHz

• 1

1 Gate Voltage [V]

Pd / (5 nm HfO

2-1 nm Al2O 3) / p & n-GaSb

Scaled Gate Stack

Low Temperature ALD

0.0 0.2 0.4 0.6 0.8

10

12

10

13

ALD Al2O

3/HfO 2

TOXE=1.4 nm

EV EC

E-EV [eV] Dit [/cm

2/eV]

PEALD Al2O

3

TOXE=3.1 nm

• Al2O3 / HfO2 bilayer stack enables gate dielectric scaling

1nm Al2O3/10nm HfO2

S.I. GaAs Substrate Al0.8Ga0.2Sb Buffer : 1.5μm

InAs0.8Sb0.2 QW:12nm

GaSb : 1 nm

Al0.8In0.2Sb Barrier : 9nm

Te δ-doping

Pd/Pt/Au Drain Pd/Pt/Au Source

1nm Al2O3/10nm HfO2

S.I. GaAs Substrate Al0.8Ga0.2Sb Buffer : 1.5μm

InAs0.8Sb0.2 QW:12nm

GaSb : 1 nm

Al0.8In0.2Sb Barrier : 9nm

Te δ-doping

Pd/Pt/Au Drain Pd/Pt/Au Source Pd/Au Gate

Sb NMOSFET Device Fabrication

As Grown Device Layers

S.I. GaAs Substrate Al0.8Ga0.2Sb Buffer : 1.5μm

InAs0.8Sb0.2 QW:12nm

GaSb : 2.5nm

Al0.8In0.2Sb Barrier : 9nm

Te δ-doping

S.I. GaAs Substrate Al0.8Ga0.2Sb Buffer : 1.5μm

InAs0.8Sb0.2 QW:12nm

GaSb : 2.5nm

Al0.8In0.2Sb Barrier : 9nm

Te δ-doping

Pd/Pt/Au Drain Pd/Pt/Au Source

Pd/Pt/Au Source-Drain Contacts and Device Isolation Gate Stack Processing

(HCl based surface clean)

Gate Patterning E-beam Lithography Final Processed Device

1nm Al2O3/10nm HfO2

S.I. GaAs Substrate Al0.8Ga0.2Sb Buffer : 1.5μm

InAs0.8Sb0.2 QW:12nm

GaSb : 1 nm

Al0.8In0.2Sb Barrier : 9nm

Te δ-doping

Pd/Pt/Au Drain Pd/Pt/Au Source Pd/Au Gate

SEM Micrograph of Sb NMOSFET

• Long and short channel Sb NMOSFETs fabricated with composite high-κ gate

stack(1 nm Al2O3 / 10 nm HfO2 on GaSb)

• Gates defined using electron beam lithography LG = 150 nm–20 µm

Pd/Au Gate LG= 150 nm

Devices Fabricated at the Penn State Nanofabrication Facility

• 2
• 1

10

• 1

10 10

1

10

2

Gm at VDS=0.5 V [µS/µm]

VDS=0.1V,0.5V LG=5µm

ID & IG [µA/µm] Gate Voltage [V] 100 200

• 2
• 1

10 10

1

10

2

ID & IG [µA/µm]

VDS=0.1V,0.5V LG=450 nm

Gate Voltage [V] 200 400 600 Gm at VDS=0.5 V [µS/µm]

• 2
• 1

10 10

1

10

2

VDS=0.1V,0.5V LG=150nm

Gate Voltage [V] 200 400 600 Gm at VDS=0.5 V [µS/µm] ID & IG [µA/µm]

Transfer Characteristics of Sb NMOS

• Good ION-IOFF for long LG devices
• Gm,peak= 400 µS/µm at VDS=0.5V for LG= 450 nm (Rext limits short channel

performance)

• The sub-threshold characteristics degrade as LG is scaled due to non-
• ptimized barrier and oxide thickness (TOXE=4.6 nm)
• Need to scale the barrier, oxide and quantum well thickness

0.0 0.5 1.0 100 200 300 400 500 600 VGS Start=0.5V Step=-0.25V LG=150nm ID[µA/µm] Drain Voltage [V] 0.0 0.5 1.0 100 200 300 400 500 ID[µA/µm] VGS Start=0.5V Step=-0.25V LG=450nm Drain Voltage [V]

0.0 0.5 1.0 50 100 150 200 VGS Start=0.5V Step=-0.25V LG=5µm ID[µA/µm] Drain Voltage [V]

Output Characteristics of Sb NMOS

• Excellent saturation (at low VG) in the output characteristics for long LG

device

• IDSAT of 450 µA/µm at 0.75 V VDS for 150 nm LG device
• Short channel ION limited by contact resistance

Long Channel Transport

• Record high electron drift mobility of 6,000 cm2/Vs at 2x1012 /cm2 of Ns
• Drift mobility lower than measured Hall mobility of QW layers by 2.2x
• Measured C-V overestimates the charge density due to Dit
• Scattering from high-κ phonons or surface charge at oxide interface

1011 1012 103 104

In0.53Ga0.47As MOSFET InAsSb QW MOSFET

Drift Mobility [cm

2/Vs]

Carrier Density [/cm

• 2]

Hall Mobility As Grown

Si/SiO

2

• S. Takagi, IEDM 2011

15x 3x

Long Channel Transport

• Stretch-out in measured C-V compared to simulated C-V is due to Dit
• ~20% enhancement in mobility at ns=2x1012 /cm2 after correcting the sheet

charge density for trapped charge

• Pulsed I-V measurements will reduce charge trapping in the Dit
• 1.5 -1.0 -0.5 0.0

0.0 0.2 0.4 0.6 0.8 Capacitance [µF/cm

2]

Gate Voltage [V]

Measured Simulated

LG=20µm Freq.=2MHz 10

11

10

12

4000 6000 8000 10000 12000 14000 Hall Mobility

As Grown

Corrected for D

it

Extracted using Measured C-V

Drift Mobility [cm

2/Vs]

Carrier Density [/cm

• 2]

• 2
• 1

10 10

1

10

2

VDS=0.1V,0.75V LG=450 nm

ID [µA/µm] Gate Voltage [V]

, DC , Pulsed (2µs)

0.0 0.5 1.0 100 200 300 400 500

15% 35%

VG-VT=1.25V VG-VT=0.75V

Closed - Pulsed (2µs) Open - DC

ID[µA/µm] Drain Voltage [V]

VG-VT=0.25V

31%

LG=450nm

Pulsed I-V

• Expected time constant for trapping / de-trapping ~ 0.5 - 1µs
• Pulsed I-V characteristics shows significant enhancement in ION and ION/IOFF over

DC due to reduced charge trapping from Dit

• ~35% ION enhancement at 0.75 V gate overdrive

τ = Rtunnel x Cit τ ~ 0.5 – 2 µs

Gate

VG VD VS

ID

Oxide GaSb Barrier Channel Barrier

JG

• Peak extrinsic RF gm improves by 30% compared to DC Gm

RF and Pulsed Measurements

• 0.5

0.0 0.5 1.0 100 200 300 400 500

30%

DC Pulsed (2µs) RF

Extrinsic Gm [µS/µm] VG-VT[V] LG=450nm VDS=0.75V

2

21

Re[ ]

m

RF g Y

ω =

=

• Effective source injection velocity (veff) determines the performance in short

channel devices

• RF measurements are used to extract charge in short channel devices

Short Channel Device Characterization: Virtual Source Injection Velocity Extraction

• A. Khakifirooz et al., TED, 2008
• M. Lundstrom, EDL 1997

1 1 1 (0 )

eff T eff

v v E µ

+

= +

2 *

B T

k T v m π =

EC

veff ID/W = Qinj x veff

L x

VG VD VS RD RS Qinj ID

Source Gate Drain

• A simplified MOSFET small signal equivalent circuit was used to model the

measured s-parameters of Sb NMOSFET

• Excellent fit between measured and modeled data is obtained for all 4 s-

parameters obtained till 50 GHz

Short Channel Device Characterization: RF Measurements and S-parameter Modeling

LG = 150 nm, WG=2x33 µm VGS-VT=0.6 V, VDS=0.75 V

0.2 0.5 1.0 2.0 5.0

• 0.2j

0.2j

• 0.5j

0.5j

• 1.0j

1.0j

• 2.0j

2.0j

• 5.0j

5.0j

Measured Modeled

S11 2*S22 10*S12 S21

100 MHz to 50 GHz

• 150 nm LG Sb NMOS at 0.75 V VDS and 0.6 V overdrive demonstrates
• 2.7 x 107 cm/s veff
• Highest veff among III-V MOSFETs

0.01 0.1 1 1 2 3

InGaAs NMOS VDS=0.5V [2]

Sb NMOS; VDS=0.75V

Strained Si [1]

veff [x 10

7cm/s]

Gate Length [µm]

Si NMOS [1] VDS = 1.1-1.3V

Short Channel Transport

[1] D. Antoniadis et al., IEDM 2008 [2] M. Radosavljevic et al.; IEDM 2009

1.5x 4x

4x higher than Si NMOS at 1.0-1.2 V VDD 1.5x higher than InGaAs NMOS at 0.5 V VDS

E-Mode Sb NMOS

• Scaled device architecture increases the gate field to QW coupling improving

device electrostatics

• SS = 150 mV/dec for E-mode for LG=5 µm (350 mV/dec for D-mode)
• High access resistance limits the short channel device performance
• Need self-aligned device architecture
• 2
• 1

1 10

• 2

10

• 1

10 10

1

10

2

E-Mode

1 5 m V / d e c

VDS=0.05V,0.5V

LG=5µm

ID [µA/µm] Gate Voltage [V]

350mV/dec

D-Mode

• 2
• 1

1 10

• 2

10

• 1

10 10

1

10

2

E-Mode

2 5 m V / d e c

VDS=0.05V,0.5V LG=150 nm

ID [µA/µm] Gate Voltage [V]

7 m V / d e c

D-Mode

IOFF VT

• veff =2.7 x 107 cm/s for D-Mode , 1.8 x 107 cm/s for D-Mode at VDS=0.75 V
• Lower veff for E-Mode devices due to the lower Hall Mobility of as grown

samples: E-Mode : 13000 cm2/Vs at ns=2.2x1012 /cm2 , D-Mode : 5,500 cm2/Vs at ns=1.8x1012 /cm2

Short Channel Performance D-Mode vs E-Mode Sb NMOSFETs

0.01 0.1 1 1 2 3

E-Mode D-Mode

Strained Si [1]

veff [x 10

7cm/s]

Gate Length [µm]

Si NMOS [1] VDS = 1.1-1.3V

[1] D. Antoniadis et al.,IEDM 2008

Drive Current Expectation from Sb NMOSFET for 0.5V VDD Logic

Assume 5nm Sb Quantum well ION = q x ns x veff = (1.6 x 10-19 C ) x (3.5 x 1012 /cm2)x (2.7 x 107 cm/s)

Experimentally demonstrated Projected based

• n experiments

= 1.5 mA/µm ION = ? at VG-VT = 2/3 x VDD ~ 0.3V Assuming RS as in Si (~ 80 Ω.µm): ION = 960 µA/µm at VG-VT~ 0.3V Key Challenges:

• Maintaining veff for very thin channels
• Obtaining optimum RS at required footprint
• Acceptable short channel effects

Conclusions

• Demonstrated antimonide (Sb) QW MOSFETs with integrated high-k

gate dielectric for low VDD logic application Sb NMOSETs exhibit:

• Electron drift mobility of 6000 cm2/Vs at ns=2 x 1012 /cm2
• Short channel (150nm LG) source injection velocity (veff) of 2.7x107

cm/s

• Extrinsic fT - LG product of 18GHz.um at VDS=0.75 V, VG-VT=0.6 V
• Benchmarked Sb NMOSFET figures of merit to standard strained Si

NMOS

• 15x higher drift mobility at ns=2x1012 /cm2
• 4x higher veff for VD=0.75 V at comparable LG
• 2x higher fT - LG product

Energy Efficiency Computing Devices

Steep Switching in Tunnel FET

Sw itching slope in TFETs can be less than kT/ q

TFET: SS < kT/ q possible MOSFET: SS > = kT/ q

VG I OFF I OFF ID

Gate Gate

i-channel

P++ Source N+ Drain

high-k high-k

Tb TOX EFS EFD

Band-pass filter

Filled States Empty States Band-gap EFC

0.0 0.1 0.2 0.3 0.4 0.5 10-11 10-9 10-7 10-5 10-3 10-1 101 103

InSb TFET InAs TFET In0.53Ga0.47As TFET Si TFET Si MOSFET

Drain Current, IDS [µA/µm] Gate Voltage, VGS [V]

VDS=0.5V

60mV/dec

Low Ion in HomJ TFETs

Silicon

I n 0 .5 3Ga 0 .4 7As

I nAs I nSb IOFF ION

Eb Wb

Both I ON and I OFF increase w ith reducing band-gap

LG=32nm EOT=0.5nm Tb=7nm Simulations

Gate Gate

i-channel

P++ Source N+ Drain

high-k high-k

Tb TOX

Simulation

100 101 102 103 101 103 105 107 109 1011

Si MOSFET Si TFET In0.53Ga0.47As TFET InAs TFET InSb TFET

ION [µA/µm] ION/IOFF

VCC=0.5V

Can HomJ TFET beat MOSFET?

• None of the Hom J TFETs are superior at higher I ON
• Need higher I ON/ I OFF @ MOSFET like I ON

Simulations

Tunnel Junction Engineering with Staggered Hetero-junction

Maxim ize stagger to get m axim um enhancem ent in I ON

Hom J TFET Eg Eg Source channel

) ) ( (

5 . 1

exp

beff

E

T

β

α

−

High Stagger HetJ TFET ∆Ec Eg Eg Source channel

c g beff

E E E ∆ − ≈

Tunneling Device Architecture

TUD Ultrathin geometry for robust electrostatics Drain-Gate underlap to minimize ambi-polar leakage

Gate Gate

i-channel

P++ Source N+ Drain

high-k high-k

Tb TOX LG Electric Field Abrupt tunneling junction

Source Channel

λ2 λ1

III-V / high-k interface with low Dit

Source Channel Source Channel Drain

Vertical Tunnel FET

Mo i N+ Gate ILD Drain Gate III-V / high-k interface with low Dit Pillar based ultrathin Tb In situ doped Molecular Beam Epitaxially grown junctions Drain-Gate underlap structure

Vertical Nano-pillar TFET

• 3. Dry etch Mo and InGaAs
• 6. ILD and Drain Contact
• 5. Gate and Source contact
• 4. ALD high-k after wet etch
• 2. Cr/Ti hard etch mask
• 1. Blanket deposit Mo

1nmAl2O3/3.5nmHfO2

39

Tunnel Barrier Engineering

39

Reduce Eg

• Mod. Stagger

High Stagger

N+ i P++ In0.53Ga0.47As Mo high-k Pt ILD Au Pd Ti

Homo-junction and Hetero- junction Tunnel FETs

Cross-section TEM im age of the fabricated devices

350nm 450nm Ti 350nm

Large Eg HomJ High HetJ TFET

• 0.50 -0.25 0.00 0.25 0.50 0.75

10 20 30 40 50 60 Drain Current, IDS [µA/µm] Drain Voltage, VDS [V] Vgs=0V to 2.5V at steps of 0.5V

• 0.50 -0.25 0.00 0.25 0.50 0.75

20 40 60 Drain Current, IDS [µA/µm] Drain Voltage, VDS [V] Vgs=0V to 2.5V at steps of 0.5V

• 0.50 -0.25 0.00 0.25 0.50 0.75

50 100 150 200 Drain Current, IDS [µA/µm] Drain Voltage, VDS [V] Vgs=0V to 2.5V at steps of 0.5V

Measured Id-Vd @ 300K

• Mod. Stagger

(ION ↑ 2.5x)

W ith High HetJ TFET, I ON increases by 6 6 0 %

• 0.50 -0.25 0.00 0.25 0.50 0.75

5 10 15 20 25 Drain Current, IDS [µA/µm] Drain Voltage, VDS [V] Vgs=0V to 2.5V steps of 0.5V

• Mod. Stagg. HetJ

Sm all Eg Hom J Large Eg Hom J High Stagg. HetJ

Lg=100nm EOT=1.5nm Lg=100nm EOT=1.5nm Lg=150nm EOT=1.5nm Lg=150nm EOT=1.5nm

• 0.5 0.0 0.5 1.0 1.5 2.0 2.5

10-4 10-3 10-2 10-1 100 101 102 Drain Current, IDS [µA/µm] Gate Voltage, VGS [V] Vds=50mV Vds=250mV Vds=500mV

• 0.5 0.0 0.5 1.0 1.5 2.0 2.5

10-6 10-5 10-4 10-3 10-2 10-1 100 101 102 Drain Current, IDS [µA/µm] Gate Voltage, VGS [V] VDS=50mV VDS=250mV VDS=500mV

• 0.5

0.0 0.5 1.0 1.5 2.0 10-6 10-5 10-4 10-3 10-2 10-1 100 101 102 Drain Current, IDS [µA/µm] Gate Voltage, VGS [V] VDS=500mV VDS=250mV VDS=50mV

• 0.5 0.0 0.5 1.0 1.5 2.0 2.5

10-6 10-5 10-4 10-3 10-2 10-1 100 101 102 Drain Current, Id [µA/µm] Gate Voltage,VGS [V] VDS=50mV VDS=250mV VDS=500mV

Measured Id-Vg @ 300K

Experim ental I OFF is increasing w ith stagger

• Mod. Stagg. HetJ

Sm all Eg Hom J Large Eg Hom J High Stagg. HetJ

Lg=100nm EOT=1.5nm Lg=100nm EOT=1.5nm Lg=150nm EOT=1.5nm Lg=150nm EOT=1.5nm

10-8 10-6 10-4 10-2 100 102 50 100 150 200 250 300 350

60mV/dec

SS (mV/decade) Drain Current, IDS [µA/µm]

77K 300K 15.4mV/dec

• 0.5

0.0 0.5 1.0 1.5 2.0 10-10 10-8 10-6 10-4 10-2 100 102

BTBT TAT T=300K T=77K

Drain Current, IDS [µA/µm] Gate Voltage, VGS [V]

VDS=50mV,500mV SRH

Temperature Dependent Switching Slope (SS)

Measured I d-Vg Sw itching Slope

• Sw itching slope im proves at low tem perature
• Quality of high-k/ I I I -V interface needs investigation

Source Channel

• 2.0-1.5-1.0-0.50.0 0.5 1.0 1.5 2.0

0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75

f=75kHz Due to Dit 1nmAl2O3/3.5nmHfO2 CET=2.3nm

Capacitance, C [µF/cm2] Gate Voltage, VGS [V]

Ideal n-In0.53Ga0.47As

• Mid-gap states have characteristic response tim e betw een

1 m s and 1 µs

• Can w e avoid gap state assisted tunneling using pulsed I -V?

High-k/Channel Interface Quality

Measured

0.0 0.5 1.0 1.5 10-8 10-7 10-6 10-5 10-4

Simulations DC pulsed (tr=600ns) pulsed (tr=200ns)

VDS=300mV

Drain Current [A] VGS-VON [V]

Vcc +

• D

S G 50Ω

To Oscilloscope

Sw itching slope im proves w ith ram p rate and appears approaching ideal sw ing

R1 Gain=100,000 ***Pulsed IV measurements conducted at NIST (John Suehle)

Can we improve SS using Ultrafast Pulsed I-V Technique?

tr

10-9 10-8 10-7 10-6 10-5 50 100 150 200 250 300

Simulations DC Pulsed (tr=600ns) Pulsed (tr=200ns)

SS [mv/dec] Drain Current [A]

60mV/dec

VDS=0.3V

Can We Improve SS using Ultrafast Pulsed I-V Technique?

Point sw itching slope approaches kT/ q @ 3 0 0 K

***Pulsed IV measurements conducted at NIST (John Suehle) Vcc +

• D

S G 50Ω

To Oscilloscope

R1 Gain=100,000 tr

0.3 0.4 0.5 0.6 0.7 100 101 102 103

High HetJ Small Eg HomJ M

• d. Stagg. Hetj

Drain Current, IDS [µA/µm] Drain Voltage, VDS [V]

Strained Si M OSFET (VT=0.2V) Large Eg Homj

Tunnel FET vs MOSFET

For Vcc less than 3 0 0 m V, BTBT can potentially deliver MOSFET like on current

Experimental (EOT=1.5nm, Tb=200nm)

0.5 1.0 1.5 2.0 10-2 10-1 100 101 102 103

Large Eg HomJ Small Eg HomJ

• Mod. HetJ

High HetJ

Measured Simulations

Drain Current, IDS [µA/µm] VGS-VON [V]

VDS=0.5V

EOT=1.5nm TP=200nm

Modeling Measured Id-Vg

Junction

Ebeff (eV) mR (mO) In0.53Ga0.47As (Large Eg homJ) 0.74 0.023 In0.7Ga0.3As (Small Eg homJ) 0.59 0.019 GaAs0.5Sb0.5/In0.53Ga0.47As (Moderate stagger hetJ) 0.5 0.025 GaAs0.35Sb0.65/In0.7Ga0.3As (High stagger hetJ) 0.25 0.022

• Further geom etry scaling required in order to reduce Vcc

Projection

Need for Extrem ely Staggered / Nearly Broken I nAs/ GaAs0 .1Sb0 .9 tunnel junction to replace MOSFET @ Vcc= 3 0 0 m V

100 101 102 103 100 102 104 106

Strained Si MOSFET

Large Eg Nearly broken

ION/IOFF ION [µA/µm]

VCC=0.3V High HetJ Simulations (EOT=0.5nm, Tb=7nm, LG=32nm)

101 102 103 100 102 104 106 108

VCC=0.5V

ION/IOFF ION [µA/µm]

Large Eg Nearly broken High HetJ

Strained Si MOSFET

Si

New Materials Electrostatics

Planar Tri-Gate Gate-All-Around

Motivation

SiGe

1D strained QW nanowire New opportunity: 0D QD

III-V

Vout(mV) Vin(mV) 300 300

sub 500mV CMOS Logic

Vg(V) 0.1 0.2 10 Id (nA)

sub 250mV BDD Logic

Classical III-V MuQFET Fabrication

QW epitaxy Fin definition and etching (BCl3/Ar) S/D contact (Au/Ge/Ni) High-K deposition (1nm Al2O3+3.5nmHfO2) Metal gate stack (Au/Pd) S/D Contact Opening QW

52

Fabrication of MuQFETs

• 40 nm wide electron waveguides fabricated using top-down pattern and etch process
• Split Gate architecture allows going from classical FET mode to Coulomb Blockade

mode

InP 2 nm In0.52Al0.48As 2nm In0.53Ga0.47As 14nm In0.52Al0.48As 2nm δ-doping 2E12 cm-2 InAlAs virtual substrate

• L. Lu, V. Saripalli, V. Narayanan S. Datta, IEDM, Dec 2011

Gate

Classical III-V MuQFET Characterization

• SS is improved to 120mV/decade with scaling fin width

to 10nm.

WFIN decreases

WFIN =10nm WFIN =40nm WFIN =100nm WFIN =500nm

WFIN decreases

WFIN =10nm WFIN =40nm WFIN =100nm WFIN =500nm

54

Ballistic Mean Free Path

Mobility (cm2/V-sec)

• Room temperature mean free path ~ 120 nm extracted for the fabricated

structures

• Gate length dependence of extracted mobility reflects quasi-ballistic transport

Sheet charge density NS (cm-2)

300K 300K

Non-Classical (NC) MuQFET

SG 80nm 40nm

• The split gate (SG) bias determines the strength of

coupling between S/D contact and channel.

• Top control gate (CG) controlling the channel potential

may result in coulomb oscillation.

CG SG source Drain Control gate (CG) CG Split Gate (SG) High-K

Beyond CMOS

• With VDD approaching 4kBT (~100mV), the CMOS inverter gain drops
• In BDD logic, path switching function and passive transmission of

messenger do not require devices with “transfer gain” and “current drivability”

• Need to program tree with open, short paths and actual decision nodes

Binary Decision Diagram (BDD) Logic CMOS Logic

• pen

short

Beyond CMOS

• ASSIST will explore reconfigurable Single Electron Transistor device

architecture and implement low voltage combinational logic circuits with such elements

Reconfigurable SET

Demonstrated reconfigurable, split gate single electron transistor (SET) exhibiting open, short and Coulomb Blockade mode of operation

Source: L. Lu, V. Narayanan, S. Datta IEDM, Dec 2011 Supported by NSF

Summary

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 Transistor Gate Delay (normalized) Operating Voltage (V)

Planar Si MOSFET Silicon MuGFET InGaAs MuQFET III-V TFET SET

0.1 1 Switching Energy [x10-16 J]

• III-V nanoelectronics provides a promising landscape for energy

efficient information processing, but needs serious $$ investment

0.01 x10-16 J Si Planar (32nm) Si MuGFET (14/22nm) III-V MuGFET III-V Tunnel FET III-V SET

60

New Nano Facility at Penn State

www.mri.psu.edu/facilities/Nanofab

Device Research Conference, DRC 2012 June 18-20 ; Abstract Submission Deadline: March 07, 2012

61

Datta Research Group

www.mri.psu.edu/facilities/Nanofab