I njection Velocity in Thin-Channel I nAs HEMTs Tae-Woo Kim and - - PowerPoint PPT Presentation

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I njection Velocity in Thin-Channel I nAs HEMTs

Tae-Woo Kim and Jesús A. del Alamo

Microsystems Technology Laboratories MIT

Sponsors: Intel, FCRP-MSD Fabrication: MTL, NSL, SEBL at MIT Acknowledgement: Dae-Hyun Kim (Teledyne Scientific)

IPRM

May 24th, 2011

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I njection Velocity in I I I -V QW FETs

10 100 1 2 3 4

InAs, tch = 10 nm *Strain-Si (VDS = 1.1 ~ 1.3 V) *Si nFETs

n ~ 13,000 cm

2/V-s

vinj [10

7 cm/s]

Lg [nm]

VDS = 0.5 V

>2X higher at half VDD

EC vinj

Kim, IEDM 2009

EV

• Injection velocity: average velocity of electrons at virtual source
• sets ION which determines switching speed
• Recent measurements of vinj in InAs HEMTs:
• vinj(InAs) > 2vinj(Si) at less than half VDD
• Derived vinj values consistent with purely ballistic transport

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Role of channel thickness in QW-FET scalability

40 80 120 160 200 60 70 80 90

InAs HEMTs: tch = 5 nm InAs HEMTs: tch = 10 nm In0.7Ga0.3As HEMT: tch = 13 nm

Subtreshold swing [mV/dec] Lg [nm] 40 80 120 160 200 40 80 120 160

InAs HEMTs: tch = 5 nm InAs HEMTs: tch = 10 nm

DIBL [mV/V] Lg [nm]

In0.7Ga0.3As HEMTs: tch = 13 nm

• Dramatic improvement in short-channel effects in thin-channel devices
• Concern: vinj degradation in thin-channel devices?

Kim, IPRM 2010

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ID = Qi_x0  vinj 

• ID: measured drain current
• Qi_x0: sheet-charge density

Qi_x0 =  Cgi dVGS,i with Cgi @ VDS = 10 mV

• Cgi extracted from S-parameters
• RS and RD correction:

VDSi = VDS – ID  (RS + RD) VGSi = VGS – ID  RS

• VT roll-off correction
• DIBL correction

Extraction methodology for vinj

VS VG VD L x EC vx0

xo

Qi_x0 RS RD ID VS VG VD L x EC vx0

xo

Qi_x0 RS RD ID

inj

Kim, IEDM 2009

vinj = ID Qi_x0

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Thin-channel I nAs HEMTs

S

InGaAs/InAlAs

L

g

D

6 nm InP 11 nm In0.52Al0.48As Buffer : In0.52Al0.48As

tins

Oxide

tch

Lside

In0.7Ga0.3As: 1 nm InAs: 2 nm In0.7Ga0.3As: 2 nm

• Triple-step gate recess process
• Gate metal stack: Ti/Pt/Au
• Lg = 40 ~ 200 nm
• Lside = 80 nm, tins = 3, 7 nm

tch = 5 nm

Reference:

• InAs HEMT with tch = 10 nm
• n,Hall = 13,500 cm2/V-sec

n,Hall = 9,950 cm2/V-sec

Lg ~ 40 nm tins = 7 nm tch = 5 nm

Kim, IPRM 2010 Kim, IEDM 2008

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I -V Characteristics: Lg = 40 nm with tins= 3 nm

• VT = 0.11 V, S = 65 mV/dec, DIBL = 50 mV/V
• gm=1.6 mS/m, RS=275 Ohm-m

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Extraction of Qi_x0

• Cgi extracted from S-parameters @ VDS = 10 mV
• Parasitic capacitance removed
• Qi_x0 =  Cgi dVGS,i

VDS = 10 mV

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vinj of Lg= 40 nm tins= 3 nm I nAs HEMTs

0.0 0.1 0.2 0.3 0.4 1 2 3 4 VDS = 0.1 V VDS = 0.3 V VDS = 0.4 V VGSi - VT[v]

inj [10

7 cm/s]

VDS = 0.5 V

tins = 3 nm

• VDS 

 vinj  (device driven into saturation)

• VGSi-VT   vinj initially  (because Qi_xo )

 then vinj  (device driven into linear regime)

vinj=3.3x107 cm/s @ 0.5 V

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vinj vs. Lg

Lg   vinj 

0.0 0.1 0.2 0.3 0.4 1 2 3 4 Lg = 200 nm Lg = 150 nm Lg = 100 nm Lg = 70 nm vinj [10

7 cm/s]

VGSi - VT[v] Lg = 40 nm tins = 3 nm, VDS = 0.5 V

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vinj - impact of channel thickness

In thin-channel devices:

• Long Lg: vinj decreases right along with e (~23%)
• Short Lg: vinj relatively unaffected

 consistent with ballistic transport

10 100 1 2 3 4

tins = 3 nm & tch = 5 nm tins = 4 nm & tch = 10 nm Strain-Si (VDS = 1.1 ~ 1.3 V) Si nFETs

n ~ 13,000 cm

2/V-s

n ~ 9,950 cm

2/V-s

vinj [10

7 cm/s]

Lg [nm] VDS = 0.5 V

Kim, IEDM 2009

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Conclusions

• Thin-channel InAs HEMTs with tch=5 nm:
• Evidence of mobility degradation
• Small degradation in injection velocity for short Lg FETs:

vinj = 3.3  107 cm/s at Lg = 40 nm

• Great scaling potential of thin-channel FETs
• Key question:
• Can vinj be preserved if severe  degradation (~3000 cm2/V.s)?