Hit Finding Emulator Summary : Something about the module - - PowerPoint PPT Presentation

1 / 12

Hit Finding Emulator

Summary:

• Something about the module
• Integrations into DualDescriptor_weihao branch
• Results
• To Do

2 / 12

Something about the module

reset reset clock clock Hit Finding Emulator Hit Finding Emulator FIFO FIFO

Clk divider Clk divider Random integer generator Random integer generator Packet Generator & FIFO flow control Packet Generator & FIFO flow control Packet size manager Packet size manager

HFemuWrapper Data out Data out A wrapper contains the emulator and a FIFO to cross the clock domain. The hit Finding Emulator is composed by five blocks:

• A clock divider generates a clock submultiple of the external clock source;
• A random integer generator output integer numbers with uniform distribution;
• The packet size manager update the packet size without stop or mess up the

data generation.

• The packet generator & FIFO flow control outputs data packets with a

variable size and a fixed data rate if the FIFO is available to receive data.

• A CRC encoder.

CRC CRC

3 / 12

Features

• Standard FIFO interface.
• Pre synthesis settable data rate generation: input clock submultiple.
• CRC encoder for data redundancy.
• Random packet size generation with uniform distribution: pre

synthesis settable mean and variation.

Packet size [4 x Byte] Probability density function mean mean - variation mean + variation 1/(2*variation)

variation

Note: the settable generics mean and variation are expressed in number of words. number of words = 4 x number of Byte

4 / 12

Integration into DualDescriptor_weihao branch (0)

• PURPOSE: Investigate the possibility to split WIB data and Hit Finding data in

two difgerent DMA descriptors.

• ARCHITECTURES:

–

Central Router half Integration: One Hit Finding Emulator per half card is integrated at central router level. HFemu outputs are splitted toward all the hit fjnding channels. There are 2 HFemu in total.

–

Top level half integration: One Hit Finding Emulator per half card is integrated at top level. HFemu outputs are splitted toward all the hit fjnding channels. There are 2 HFemu in total.

–

Top level full integration: One Hit Finding Emulator per hit fjnding channel is integrated at top level. There are 10 HFemu in total.

5 / 12

HFemu HFemu

Integration into Dual-Descriptor-Weihao branch (1)

First Architecture: Central Router half Integration

HF HF thFMdm thFMdm thFMdm thFMdm HF HF thFMdm thFMdm thFMdm thFMdm HF HF thFMdm thFMdm thFMdm thFMdm

Channel: 0 Channel: 1 Channel: chfm_num-1

TTC TTC

Host FIFO 0 Host FIFO 0 Host FIFO 1 Host FIFO 1 WIB data flow Hit Finding data flow Note: The Hit Finding Emulator is not replicated for each link but his output data are sent to each (orange) Hit finding channel. Color legend:

Central Router

6 / 12

HFemu HFemu

Integration into Dual-Descriptor-Weihao branch (2)

Second Architecture: Top Level half Integration

thFMdm thFMdm thFMdm thFMdm thFMdm thFMdm thFMdm thFMdm thFMdm thFMdm thFMdm thFMdm thFMdm thFMdm thFMdm thFMdm thFMdm thFMdm WIB ch: 0 WIB ch: 1 WIB ch: 2 WIB ch: chfm_num

Host FIFO 0 Host FIFO 0 Host FIFO 1 Host FIFO 1

Central router

WIB data flow Hit Finding data flow Color legend:

Note:

• The Hit Finding

emulator is not reply for each Hit Finding channel.

• Only 5 hit finding

channels are added because DUNE will have

• nly five channels.

HF ch: 0 HF ch: 1 HF ch: 2 HF ch: 3 HF ch: 4

7 / 12

Integration into Dual-Descriptor-Weihao branch (3)

Third Architecture: Top Level full Integration

HFemu[1] HFemu[1]

thFMdm thFMdm

HFemu[0] HFemu[0]

thFMdm thFMdm

HFemu[2] HFemu[2]

thFMdm thFMdm

HFemu[3] HFemu[3]

thFMdm thFMdm thFMdm thFMdm thFMdm thFMdm thFMdm thFMdm thFMdm thFMdm

HFemu[4] HFemu[4]

thFMdm thFMdm WIB ch: 0 WIB ch: 1 WIB ch: 2 WIB ch: chfm_num

Host FIFO 0 Host FIFO 0 Host FIFO 1 Host FIFO 1

Central router

WIB data flow Hit Finding data flow Color legend:

Note:

• An Hit Finding

emulator reply is added for each Hit Finding channel.

• Only 5 hit finding

channels are added because DUNE will have

• nly five chennels.

HF ch: 0 HF ch: 1 HF ch: 2 HF ch: 3 HF ch: 4

8 / 12

Results

• WIB data fmow and Hit Finding data fmow run

separately towards two difgerent Wupper FIFOs.

• Central router half integration: No errors occur.
• Top level half integration: No errors occur.
• Top level full integration: Errors occur, we lose
• ne HF link in the half card 1 (Timing issues).

9 / 12

Results – more in details

resources utilization comparison

CRFM integration: Top half integration: Top full integration: No sensible variations in HW resources consumption!

10 / 12

Results – more in details

timing comparison

• All the timing fails;
• The least worst is the Top half

integration;

• The failing paths are at pcie level.

CRFM integration Top half integration Top full integration

11 / 12

Results – more in details

routing comparison

CRFM integration Top half integration Top full integration Color legend: HFwrapper-0 HFwrapper-1

Note: In both the Top level implementations, some modules of the HFwrapper-0 are mapped in the pblock 1. Viceversa happens to the HFwrapper-1. The issue doesn’t appear in the CRFM integration.

12 / 12

To Do

• Reduce the Hit Finding DMA descriptor size:

data coming from the Hit Finding have a lower rate than WIB data, possible optimization.

• Runtime settable data rate (Register Map).
• Change FIFO type: From standard FIFO to AXI4 FIFO.
• Emulate the Hit Frame Format (if needed).