Hit Finding Emulator Summary : ● Something about the module ● Integrations into DualDescriptor_weihao branch ● Results ● To Do 1 / 12
Something about the module A wrapper contains the emulator and a FIFO to cross the clock domain. The hit Finding Emulator is composed by five blocks: ● A clock divider generates a clock submultiple of the external clock source; ● A random integer generator output integer numbers with uniform distribution; ● The packet size manager update the packet size without stop or mess up the data generation. ● The packet generator & FIFO flow control outputs data packets with a variable size and a fixed data rate if the FIFO is available to receive data. ● A CRC encoder . HFemuWrapper Packet Generator Packet Generator Clk Clk clock CRC & CRC & clock divider divider FIFO flow control FIFO flow control Data out Data out Hit Finding Emulator FIFO Hit Finding Emulator FIFO reset reset Random integer Packet size Random integer Packet size generator manager generator manager 2 / 12
Features Standard FIFO interface. ● Pre synthesis settable data rate generation: input clock submultiple. ● CRC encoder for data redundancy. ● Random packet size generation with uniform distribution: pre ● synthesis settable mean and variation. Probability density Note : function the settable generics mean and variation are expressed in number of words . 1/(2*variation) variation number of words = 4 x number of Byte mean - mean + mean Packet size variation variation [4 x Byte] 3 / 12
Integration into DualDescriptor_weihao branch (0) PURPOSE : Investigate the possibility to split WIB data and Hit Finding data in ● two difgerent DMA descriptors . ARCHITECTURES : ● Central Router half Integration : One Hit Finding Emulator per half card – is integrated at central router level. HFemu outputs are splitted toward all the hit fjnding channels. There are 2 HFemu in total. Top level half integration : One Hit Finding Emulator per half card is – integrated at top level. HFemu outputs are splitted toward all the hit fjnding channels. There are 2 HFemu in total. Top level full integration : One Hit Finding Emulator per hit fjnding – channel is integrated at top level. There are 10 HFemu in total. 4 / 12
Integration into Dual-Descriptor-Weihao branch (1) First Architecture: Central Router half Integration Central Router Color legend: Channel: 0 WIB data flow thFMdm thFMdm Hit Finding data flow HF HF thFMdm thFMdm Channel: 1 thFMdm thFMdm Host FIFO 0 Host FIFO 0 HF HF thFMdm thFMdm HFemu HFemu Host FIFO 1 Host FIFO 1 Channel: chfm_num-1 thFMdm thFMdm Note : HF HF The Hit Finding Emulator is thFMdm thFMdm not replicated for each link but his output data are sent to each (orange) Hit finding TTC TTC channel. 5 / 12
Integration into Dual-Descriptor-Weihao branch (2) Second Architecture: Top Level half Integration Central router Color legend: WIB ch: 0 WIB data flow thFMdm thFMdm Hit Finding data WIB ch: 1 flow thFMdm thFMdm WIB ch: 2 thFMdm thFMdm Host FIFO 0 Host FIFO 0 Note : WIB ch: chfm_num ● The Hit Finding thFMdm thFMdm emulator is not reply for each Hit HF ch: 0 Finding channel. thFMdm thFMdm ● Only 5 hit finding HF ch: 1 thFMdm channels are thFMdm added because HF ch: 2 HFemu HFemu Host FIFO 1 thFMdm Host FIFO 1 thFMdm DUNE will have HF ch: 3 only five channels. thFMdm thFMdm HF ch: 4 thFMdm thFMdm 6 / 12
Integration into Dual-Descriptor-Weihao branch (3) Third Architecture: Top Level full Integration Central router Color legend: WIB ch: 0 thFMdm WIB data flow thFMdm Hit Finding data WIB ch: 1 flow thFMdm thFMdm WIB ch: 2 thFMdm Host FIFO 0 thFMdm Host FIFO 0 Note : WIB ch: chfm_num ● An Hit Finding thFMdm thFMdm emulator reply is added for each Hit HF ch: 0 HFemu[0] HFemu[0] thFMdm Finding channel. thFMdm ● Only 5 hit finding HF ch: 1 HFemu[1] HFemu[1] thFMdm thFMdm channels are added because HF ch: 2 HFemu[2] HFemu[2] Host FIFO 1 thFMdm Host FIFO 1 thFMdm DUNE will have HF ch: 3 only five chennels. HFemu[3] HFemu[3] thFMdm thFMdm HF ch: 4 HFemu[4] HFemu[4] thFMdm thFMdm 7 / 12
Results ● WIB data fmow and Hit Finding data fmow run separately towards two difgerent Wupper FIFOs. ● Central router half integration: No errors occur. ● Top level half integration: No errors occur. ● Top level full integration: Errors occur, we lose one HF link in the half card 1 (Timing issues). 8 / 12
Results – more in details resources utilization comparison CRFM integration: Top half integration: Top full integration: No sensible variations in HW resources consumption! 9 / 12
Results – more in details timing comparison Top half integration CRFM integration All the timing fails; ● Top full integration The least worst is the Top half ● integration; The failing paths are at pcie level. ● 10 / 12
Results – more in details routing comparison CRFM integration Top half integration Top full integration Color legend : HFwrapper-0 HFwrapper-1 Note : In both the Top level implementations, some modules of the HFwrapper-0 are mapped in the pblock 1. Viceversa happens to the HFwrapper-1. The issue doesn’t appear in the CRFM integration. 11 / 12
To Do ● Reduce the Hit Finding DMA descriptor size: data coming from the Hit Finding have a lower rate than WIB data, possible optimization. ● Runtime settable data rate (Register Map). ● Change FIFO type: From standard FIFO to AXI4 FIFO. ● Emulate the Hit Frame Format (if needed). 12 / 12
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