Highly integrated power electronic converters using active devices - - PowerPoint PPT Presentation

Highly integrated power electronic converters using active devices embedded in printed-circuit board

Chenjiang YU1, Cyril BUTTAY2, Éric LABOURÉ1, Vincent BLEY3, Céline COMBETTES3

1GEEPS (LGEP), Paris, France 2Laboratoire Ampère, Lyon, France 3 LAPLACE, Toulouse, France

17/4/15

1 / 23

Outline Introduction Review of PCB-based packaging Proposed Embedding Technique Summary and Conclusion

2 / 23

Outline Introduction Review of PCB-based packaging Proposed Embedding Technique Summary and Conclusion

3 / 23

Advantages of die embedding

The Printed-Circuit-Board technology (PCB) enables:

◮ higher interconnect density

◮ multi-layer ◮ small pitch (down to 25 µm linewidth)

◮ Low inductance [1]

◮ small size ◮ laminated busbar structure

◮ batch-processed manufacturing

◮ all interconnects are processed at once

• E. Hoene, “Ultra Low Inductance Package for SiC” ECPE

workshop on power boards, 2012

4 / 23

Advantages of die embedding

The Printed-Circuit-Board technology (PCB) enables:

◮ higher interconnect density

◮ multi-layer ◮ small pitch (down to 25 µm linewidth)

◮ Low inductance [1]

◮ small size ◮ laminated busbar structure

◮ batch-processed manufacturing

◮ all interconnects are processed at once

• E. Hoene, “Ultra Low Inductance Package for SiC” ECPE

workshop on power boards, 2012

4 / 23

Advantages of die embedding

The Printed-Circuit-Board technology (PCB) enables:

◮ higher interconnect density

◮ multi-layer ◮ small pitch (down to 25 µm linewidth)

◮ Low inductance [1]

◮ small size ◮ laminated busbar structure

◮ batch-processed manufacturing

◮ all interconnects are processed at once

• E. Hoene, “Ultra Low Inductance Package for SiC” ECPE

workshop on power boards, 2012

4 / 23

Outline Introduction Review of PCB-based packaging Proposed Embedding Technique Summary and Conclusion

5 / 23

Literature Review – Converter on a flex substrate

Delft TU “folded” converter [2, 3]

images from ECPE Seminar “Power PCBs and Busbars”, Delft, 2008

◮ Use of a flex substrate to form windings, ◮ wrapping around the larger components ◮ thermal management might prove difficult

6 / 23

Literature Review – Flex PCB interconnects

[4]

◮ Flex PCB instead of wirebonds ◮ Die top contact with solder/sintering

◮ requires suitable finish

◮ backside attached to a DBC ◮ commercially available from Semikron ◮ advantages:

◮ low profile, low inductance ◮ higher interconnect density

• S. Dieckerhoff et al., “Electric Characteristics of Planar Interconnect Technologies for

Power MOSFETs” PESC 2007

7 / 23

Literature Review – Flex PCB interconnects

[4] [5]

◮ Flex PCB instead of wirebonds ◮ Die top contact with solder/sintering

◮ requires suitable finish

◮ backside attached to a DBC ◮ commercially available from Semikron ◮ advantages:

◮ low profile, low inductance ◮ higher interconnect density

• T. Stockmeier et al. “SKiN: Double side sintering technology for new packages”, ISPD

2011

7 / 23

Literature Review – Flex PCB interconnects

[4] [5] [6]

◮ Flex PCB instead of wirebonds ◮ Die top contact with solder/sintering

◮ requires suitable finish

◮ backside attached to a DBC ◮ commercially available from Semikron ◮ advantages:

◮ low profile, low inductance ◮ higher interconnect density

• Y. Xiao et al., “Integrated flip-chip flex-circuit packaging for power electronics

applications”, IEEE trans on Power Electronics vol. 19, 2004

7 / 23

Literature Review – “PCB-like” 3D structures

P . Ning et al. “A novel high-temperature planar package for SiC multichip phase-leg power module”, IEEE Trans on PE vol 25, 2010, 25, 2059

Silver-sintered interconnects and Epoxy/Kapton insulation [7]

8 / 23

Literature Review – “PCB-like” 3D structures

P . Ning et al. “A novel high-temperature planar package for SiC multichip phase-leg power module”, IEEE Trans on PE vol 25, 2010, 25, 2059

Silver-sintered interconnects and Epoxy/Kapton insulation [7]

Weidner, et al. “Planar Interconnect Technology for Power Module System Integration”, CIPS 2012

SiPLIT Copper electroplating, laminated isolation laser-structured in-situ [8]

8 / 23

Literature Review – Passives embedding in PCB

Andresakis, J. “Embedded Capacitors” Oak-Mitsui Technologies, 2005

Embedding of capacitive layer [9]

◮ Established tech. in consumer electronics ◮ Mostly targeted at low-voltage ◮ Capacitance values: 10 pF – 5nF/cm2

9 / 23

Literature Review – Passives embedding in PCB

Embedding of capacitive layer [9]

◮ Established tech. in consumer electronics ◮ Mostly targeted at low-voltage ◮ Capacitance values: 10 pF – 5nF/cm2

Integration of passives [10]

◮ Capacitive layers ◮ Magnetic layers ◮ Embedded Passives Integrated Circuit

(emPIC)

• E. Waffenschmidt et al. “Design Method and Material Technologies for

Passives in Printed Circuit Board Embedded Circuits” IEEE Trans. on PE, vol 20, 2005

9 / 23

Literature Review – Die embedding in PCB – 1

Patents on chip embedding [11]

• A. Ostmann, “Leistungselektronik in der Leiterplatte” AT&S Technologieforum, 2013

◮ Very active area in recent years ◮ Many applications to high interconnect density ◮ Several industrial developments (A&T, Schweizer, etc.)

10 / 23

Literature Review – Die embedding in PCB – 2

Low-inductance packaging for SiC [1]

◮ Half bridge module ◮ 0.8 nH loop inductance ◮ Embedding die using stud bumps

• E. Hoene, “Ultra Low Inductance Package for SiC” ECPE workshop on power

boards, 2012

❤tt♣✿✴✴✇✇✇✳♣❝❞❛♥❞❢✳❝♦♠✴♣❝❞❡s✐❣♥✴✐♥❞❡①✳♣❤♣✴❡❞✐t♦r✐❛❧✴♠❡♥✉✲❢❡❛t✉r❡s✴✾✷✺✼✲❝♦♠♣♦♥❡♥t✲♣❛❝❦❛❣✐♥❣✲✶✹✵✺

11 / 23

Literature Review – Die embedding in PCB – 2

Low-inductance packaging for SiC [1]

◮ Half bridge module ◮ 0.8 nH loop inductance ◮ Embedding die using stud bumps

• E. Hoene, “Ultra Low Inductance Package for SiC” ECPE workshop on power

boards, 2012

◮ Power module development through german

project Hi-LEVEL [12]

◮ 10 kW and 50 kW demonstrators ◮ Thick copper or DBC for thermal management

❤tt♣✿✴✴✇✇✇✳♣❝❞❛♥❞❢✳❝♦♠✴♣❝❞❡s✐❣♥✴✐♥❞❡①✳♣❤♣✴❡❞✐t♦r✐❛❧✴♠❡♥✉✲❢❡❛t✉r❡s✴✾✷✺✼✲❝♦♠♣♦♥❡♥t✲♣❛❝❦❛❣✐♥❣✲✶✹✵✺

11 / 23

Literature Review – Considerations on CAD tools

CAD tools with embedding capability [13]

◮ Automatic placement of parts ◮ Design rules (cavity size, height check, etc.) ◮ Generation of the manufacturing data

◮ Position of dies, cavities, laser drilling, etc.

source: M. Brizoux et al. “Development of a Design & Manufacturing Environment for Reliable and Cost-Effective PCB Embedding Technology” IPC Apex, 2011

12 / 23

Outline Introduction Review of PCB-based packaging Proposed Embedding Technique Summary and Conclusion

13 / 23

Overview of the process

◮ Start with a DBC substrate ◮ Die attach (silver sintering) ◮ PCB stacking ◮ PCB lamination ◮ Topside copper etching ◮ Laser ablation ◮ Copper electroplating

14 / 23

Overview of the process

◮ Start with a DBC substrate ◮ Die attach (silver sintering) ◮ PCB stacking ◮ PCB lamination ◮ Topside copper etching ◮ Laser ablation ◮ Copper electroplating

14 / 23

Overview of the process

◮ Start with a DBC substrate ◮ Die attach (silver sintering) ◮ PCB stacking ◮ PCB lamination ◮ Topside copper etching ◮ Laser ablation ◮ Copper electroplating

14 / 23

Overview of the process

◮ Start with a DBC substrate ◮ Die attach (silver sintering) ◮ PCB stacking ◮ PCB lamination ◮ Topside copper etching ◮ Laser ablation ◮ Copper electroplating

14 / 23

Overview of the process

◮ Start with a DBC substrate ◮ Die attach (silver sintering) ◮ PCB stacking ◮ PCB lamination ◮ Topside copper etching ◮ Laser ablation ◮ Copper electroplating

14 / 23

Overview of the process

◮ Start with a DBC substrate ◮ Die attach (silver sintering) ◮ PCB stacking ◮ PCB lamination ◮ Topside copper etching ◮ Laser ablation ◮ Copper electroplating

14 / 23

Overview of the process

◮ Start with a DBC substrate ◮ Die attach (silver sintering) ◮ PCB stacking ◮ PCB lamination ◮ Topside copper etching ◮ Laser ablation ◮ Copper electroplating

14 / 23

Overview of the process – significant points

◮ Backside die attach with silver sintering:

◮ The die does not move during assembly ◮ Accurate positioning

◮ Ablation using a CO2 laser

◮ Very good selectivity (metal layers insensitive to laser light) ◮ Use of the copper layer as an alignment mask

◮ Prototype-scale equipment used

◮ Can manufacture prototypes from 4x4 cm2 up to 21x28 cm2 ◮ Affordable, useful for process development. 15 / 23

Overview of the process – significant points

◮ Backside die attach with silver sintering:

◮ The die does not move during assembly ◮ Accurate positioning

◮ Ablation using a CO2 laser

◮ Very good selectivity (metal layers insensitive to laser light) ◮ Use of the copper layer as an alignment mask

◮ Prototype-scale equipment used

◮ Can manufacture prototypes from 4x4 cm2 up to 21x28 cm2 ◮ Affordable, useful for process development. 15 / 23

Overview of the process – significant points

◮ Backside die attach with silver sintering:

◮ The die does not move during assembly ◮ Accurate positioning

◮ Ablation using a CO2 laser

◮ Very good selectivity (metal layers insensitive to laser light) ◮ Use of the copper layer as an alignment mask

◮ Prototype-scale equipment used

◮ Can manufacture prototypes from 4x4 cm2 up to 21x28 cm2 ◮ Affordable, useful for process development. 15 / 23

Effect of die finish

Die Mask PVD Two die finishes evaluated

◮ standard Al topside ◮ Ti/Cu PVD with a shadow

mask

0.0 0.5 1.0 1.5 2.0 2.5 3.0 Displacement [mm] −5 5 10 15 20 25 30 Height [µm]

initial 10 mins electroplating on Cu 10 mins electroplating

16 / 23

Cross section

5 min electroplating on Al-finished die

◮ vertical walls in epoxy layers ◮ good self-alignment ◮ electroplated copper too thin

17 / 23

Electrical Characterization

0.0 0.5 1.0 1.5 2.0 Forward Voltage [V] 10 20 30 40 50 60 Forward Current [A]

Die with Al finish, 20 min electroplating

−1200 −1000 −800 −600 −400 −200 Reverse voltage [V] 10−8 10−7 10−6 10−5 Reverse current [A]

◮ Tests performed in air, without additional passivation ◮ die finish and electroplating time have a strong effect on

characteristic

18 / 23

Electrical Characterization

0.0 0.5 1.0 1.5 2.0 Forward Voltage [V] 10 20 30 40 50 60 Forward Current [A]

Die with Al finish, 20 min electroplating Die with Cu finish, 20 min electroplating Die with Al finish, 5 min electroplating

−1200 −1000 −800 −600 −400 −200 Reverse voltage [V] 10−8 10−7 10−6 10−5 Reverse current [A]

◮ Tests performed in air, without additional passivation ◮ die finish and electroplating time have a strong effect on

characteristic

18 / 23

Outline Introduction Review of PCB-based packaging Proposed Embedding Technique Summary and Conclusion

19 / 23

Summary and Conclusion

◮ Active developments on PCB-embedding

◮ Scalable technology ◮ Allows for more compact systems ◮ Attractive for fast, wide-bandgap devices

◮ Presentation of a prototype-scale process

◮ Full details in the paper! ◮ First results on large-die diode embedding

◮ Developments to come: embedding of an IGBT/diode half

bridge:

◮ Simple generation of all files from CAD (prepreg cutouts,

dies opening. . . )

◮ Validation of alignment accuracy with the gate of the IGBT ◮ Patterning of topside, mounting of SMT components 20 / 23

Summary and Conclusion

◮ Active developments on PCB-embedding

◮ Scalable technology ◮ Allows for more compact systems ◮ Attractive for fast, wide-bandgap devices

◮ Presentation of a prototype-scale process

◮ Full details in the paper! ◮ First results on large-die diode embedding

◮ Developments to come: embedding of an IGBT/diode half

bridge:

◮ Simple generation of all files from CAD (prepreg cutouts,

dies opening. . . )

◮ Validation of alignment accuracy with the gate of the IGBT ◮ Patterning of topside, mounting of SMT components 20 / 23

Summary and Conclusion

◮ Active developments on PCB-embedding

◮ Scalable technology ◮ Allows for more compact systems ◮ Attractive for fast, wide-bandgap devices

◮ Presentation of a prototype-scale process

◮ Full details in the paper! ◮ First results on large-die diode embedding

◮ Developments to come: embedding of an IGBT/diode half

bridge:

◮ Simple generation of all files from CAD (prepreg cutouts,

dies opening. . . )

◮ Validation of alignment accuracy with the gate of the IGBT ◮ Patterning of topside, mounting of SMT components 20 / 23

Summary and Conclusion

◮ Active developments on PCB-embedding

◮ Scalable technology ◮ Allows for more compact systems ◮ Attractive for fast, wide-bandgap devices

◮ Presentation of a prototype-scale process

◮ Full details in the paper! ◮ First results on large-die diode embedding

◮ Developments to come: embedding of an IGBT/diode half

bridge:

◮ Simple generation of all files from CAD (prepreg cutouts,

dies opening. . . )

◮ Validation of alignment accuracy with the gate of the IGBT ◮ Patterning of topside, mounting of SMT components 20 / 23

Summary and Conclusion

◮ Active developments on PCB-embedding

◮ Scalable technology ◮ Allows for more compact systems ◮ Attractive for fast, wide-bandgap devices

◮ Presentation of a prototype-scale process

◮ Full details in the paper! ◮ First results on large-die diode embedding

◮ Developments to come: embedding of an IGBT/diode half

bridge:

◮ Simple generation of all files from CAD (prepreg cutouts,

dies opening. . . )

◮ Validation of alignment accuracy with the gate of the IGBT ◮ Patterning of topside, mounting of SMT components 20 / 23

Summary and Conclusion

◮ Active developments on PCB-embedding

◮ Scalable technology ◮ Allows for more compact systems ◮ Attractive for fast, wide-bandgap devices

◮ Presentation of a prototype-scale process

◮ Full details in the paper! ◮ First results on large-die diode embedding

◮ Developments to come: embedding of an IGBT/diode half

bridge:

◮ Simple generation of all files from CAD (prepreg cutouts,

dies opening. . . )

◮ Validation of alignment accuracy with the gate of the IGBT ◮ Patterning of topside, mounting of SMT components 20 / 23

Bibliography I

• E. Hoene, “Ultra Low Inductance Package for SiC,” in ECPE workshop on power

boards, ECPE, 2012.

• E. de Jong, E. de Jong, B. Ferreira, and P

. Bauer, “Toward the Next Level of PCB Usage in Power Electronic Converters,” Power Electronics, IEEE Transactions on,

• vol. 23, no. 6, pp. 3151–3163, 2008.
• B. Ferreira, “PCB Integration Technology Overview,” in ECPE Seminar “Power

PCBs and Busbars”, (Delft), 2008.

• S. Dieckerhoff, T. Kirfe, T. Wernicke, C. Kallmayer, A. Ostmann, E. Jung,
• B. Wunderle, and H. Reichl, “Electric Characteristics of Planar Interconnect

Technologies for Power MOSFETs,” in Power Electronics Specialists Conference,

• 2007. PESC 2007. IEEE, pp. 1036 –1042, jun 2007.
• T. Stockmeier, P

. Beckedahl, C. Gobl, and T. Malzer, “SKiN: Double side sintering technology for new packages,” in Power Semiconductor Devices and ICs (ISPSD), 2011 IEEE 23rd International Symposium on, pp. 324–327, May 2011.

• Y. Xiao, H. Shah, R. Natarajan, E. J. Rymaszewski, T. Chow, and R. Gutmann,

“Integrated flip-chip flex-circuit packaging for power electronics applications,” Power Electronics, IEEE Transactions on, vol. 19, pp. 515–522, March 2004.

21 / 23

Bibliography II

P . Ning, T. G. Lei, F . Wang, G.-Q. Lu, K. D. Ngo, and K. Rajashekara, “A novel high-temperature planar package for SiC multichip phase-leg power module,” Power Electronics, IEEE Transactions on, vol. 25, no. 8, pp. 2059–2067, 2010.

• K. Weidner, M. Kaspar, and N. Seliger, “Planar Interconnect Technology for

Power Module System Integration,” in Integrated Power Electronics Systems (CIPS), 2012 7th International Conference on, pp. 1–5, IEEE, 2012.

• J. Andresakis, “Embedded Capacitors,” presentation, Oak-Mitsui Technologies,

nov 2005.

• E. Waffenschmidt, B. Ackermann, and J. A. Ferreira, “Design Method and

Material Technologies for Passives in Printed Circuit Board Embedded Circuits,” IEEE Transactions on Power Electronics, vol. 20, pp. 576–584, may 2005.

• A. Ostmann, “Leistungselektronik in der Leiterplatte,” in AT&S Technologieforum,

2013.

• A. Ostmann, L. Boettcher, D. Manessis, S. Karaszkiewicz, and K.-D. Lang,

“Power modules with embedded components,” in Microelectronics Packaging Conference (EMPC) , 2013 European, pp. 1–4, Sept 2013.

• M. Brizoux, A. Grivon, W. Maia Filho, et al., “Development of a Design &

Manufacturing Environment for Reliable and Cost-Effective PCB Embedding Technology,” in IPC Apex Expo conference, 2011.

22 / 23

Thank you for your attention

cyril.buttay@insa-lyon.fr This work was funded by the French National Research Agency (ANR) under the grant name ETHAER. The authors thank Mr Gilles BRILLAT for his technical help.

23 / 23