HCAL uTCA Readout Crate Ethernet GBT links from front-ends 12 AMC - - PowerPoint PPT Presentation

hcal utca readout crate
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HCAL uTCA Readout Crate Ethernet GBT links from front-ends 12 AMC - - PowerPoint PPT Presentation

HCAL uTCA Readout Crate Ethernet GBT links from front-ends 12 AMC Slots Power 1 H C M Commercial MCH uHTR uHTR uHTR uHTR uHTR uHTR uHTR uHTR uHTR uHTR uHTR uHTR Management Ethernet Power AMC13 AMC13 Clocks Fast controls


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SLIDE 1

2012-05-22

  • E. Hazen -- Upgrade Week

2

HCAL uTCA Readout Crate

uHTR uHTR uHTR uHTR uHTR uHTR uHTR uHTR uHTR uHTR uHTR uHTR

TTS / Local Trigger GBT links from front-ends Fiber links to trigger

M C H 1

Ethernet

AMC13

Power Power

Legacy TTC DAQ optical fibers 12 AMC Slots Commercial MCH Management Ethernet AMC13 Clocks Fast controls DAQ

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SLIDE 2

2012-05-22

  • E. Hazen -- Upgrade Week

4

MicroTCA Interface to CMS

(Interim)

SFP+

New DAQ receiver card to S-Link, Myrinet, etc

SFP+ SFP+ SFP+ SFP TTCex

OptRx OptRx OptRx FPGA

RJ-45 To FMM

FMM Adapter TTC System Central CMS DAQ

AMC13 MCH

Gigabit Ethernet(s) DCS Controls Data to DAQ 5 Gb/s 1 or 2 links per crate 160 Mb/s In: TTC Out: TTS

Local Trigger

16 AMC13 produced One in DAQ lab since early 2012 Prototype exists in CDAQ group Prototype under development at BU

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SLIDE 3

Teststand at University of Minnesota

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SLIDE 4
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SLIDE 5

2012-05-22

  • E. Hazen -- Upgrade Week

11

µTCA Dual-Star Backplane

MCH 1 Commercial /Std MCH 2 aka “AMC13” Custom design for CMS

Bi-directional serial (up to 10Gb/sec) point-to-point links from each AMC to MCH (redundant links to each MCH) CMS Use Fabric A (1 link) DAQ @ 2-4 Gb/s Fabric B (1 link) LVDS TTC Fabric D-G (4 links) Spare CLK1 MLVDS LHC clock Note: Interconnections can be customized by the backplane manufacturer inexpensively. Fabric A (1 link) Gigabit Ethernet Fabric B (1 link) Spare Fabric D-G Spare CLK1 Spare

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SLIDE 6

HCAL Development Requirements

  • Expect to setup a uTCA at Fermilab which will

handle both data and control functions

  • It will serve as a working testbench for FE

Modules and the readout system

– Characterize our analog ASICs ‐ QIE10s (Charge Integration Encoder)

  • DC charge calibration ‐> slope, offset

– Read/Write to local registers – Exercise L1 and L2 buffers – Exercise optical links