GAELS Project Progress Wei Song 19/04/2012 Advanced Processor - PowerPoint PPT Presentation

GAELS Project Progress Wei Song 19/04/2012 Advanced Processor Technologies Group 2012/4/16 The School of Computer Science

Current Status • Verilog Parser – Designing a Verilog parser which can parse synchronous RTL designs. – Now support: • Able to read in all synthesisable features (except functions) – Ongoing • Syntax checking, elaboration and design linking Advanced Processor Technologies Group 2012/4/16 The School of Computer Science

What’s next • Circuit analyses – Data-flow analyses – Find the optimal boundary for sync/async partition • How to find? – Convert some part to sync/async elastic circuits. • Is sync elastic circuit able to seamlessly connect with sync circuits? • How to find the right sub-circuits to be converted? Advanced Processor Technologies Group 2012/4/16 The School of Computer Science

Parser structure • Scanner – Flexer (lex) • Lex analyser – Bison (yacc) • Data structures – C++0x, STL, boost, GNU MPL • Remain unknowns – Database format, preprocessor Advanced Processor Technologies Group 2012/4/16 The School of Computer Science

Tool flow RTL Verilog HDL Cell Library VCD waveform Timing info Pipeline usage AVerilog synthesiser Major issue: Multiple smaller Async interfaces How to find the sub-circuits RTL Verilog HDL where synchronous elastic or designs asynchronous implementations Sync elastic pipelines are better. blackboxes Commercial dont_touch tools Advanced Processor Technologies Group 2012/4/16 The School of Computer Science