GAELS Project Progress Wei Song 19/04/2012 Advanced Processor - - PowerPoint PPT Presentation

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GAELS Project Progress Wei Song 19/04/2012 Advanced Processor Technologies Group 2012/4/16 The School of Computer Science Current Status Verilog Parser Designing a Verilog parser which can parse synchronous RTL designs. Now

SLIDE 1

2012/4/16 Advanced Processor Technologies Group The School of Computer Science

GAELS Project Progress

Wei Song 19/04/2012

SLIDE 2

Current Status

Verilog Parser

– Designing a Verilog parser which can parse synchronous RTL designs. – Now support:

Able to read in all synthesisable features (except

functions)

– Ongoing

Syntax checking, elaboration and design linking

2012/4/16 Advanced Processor Technologies Group The School of Computer Science

SLIDE 3

What’s next

Circuit analyses

– Data-flow analyses – Find the optimal boundary for sync/async partition

How to find?

– Convert some part to sync/async elastic circuits.

Is sync elastic circuit able to seamlessly connect

with sync circuits?

How to find the right sub-circuits to be converted?

2012/4/16 Advanced Processor Technologies Group The School of Computer Science

SLIDE 4

Parser structure

Scanner

– Flexer (lex)

Lex analyser

– Bison (yacc)

Data structures

– C++0x, STL, boost, GNU MPL

Remain unknowns

– Database format, preprocessor

2012/4/16 Advanced Processor Technologies Group The School of Computer Science

SLIDE 5

Tool flow

2012/4/16 Advanced Processor Technologies Group The School of Computer Science RTL Verilog HDL Cell Library VCD waveform AVerilog synthesiser

Timing info Pipeline usage

Multiple smaller RTL Verilog HDL designs Async interfaces Sync elastic pipelines Commercial tools

blackboxes dont_touch

Major issue: How to find the sub-circuits where synchronous elastic or asynchronous implementations are better.