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GAELS Project Meeting Automatic Data Path Extraction Wei Song - - PowerPoint PPT Presentation

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GAELS Project Meeting Automatic Data Path Extraction Wei Song 15/11/2013 Advanced Processor Technologies Group The School of Computer Science Content Tool Flow Progress Updated Type Calculation Detailed FSM classification

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15/11/2013

GAELS Project Meeting Automatic Data Path Extraction

Wei Song

Advanced Processor Technologies Group The School of Computer Science

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Content

  • Tool Flow
  • Progress

– Updated Type Calculation – Detailed FSM classification – Automatic Data Path Extraction – Preliminary Partition Analysis

  • Future Works
  • Conclusion

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System Partitions

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BUS FSM FSM FSM FSM FSM RAM

A large RTL system can be partitioned into multi sub-design connected by data channels with variable data-rates.

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SLIDE 4

Tool Flow

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RTL Verilog Files Cell Library Waveforms

Timing info Pipeline usage

Async interfaces Asynchronous Verilog Synthesizer Asynchronous Interfaces Multiple Verilog Sub-designs Commercial Tools

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SLIDE 5

Flow inside Async Synthesizer

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RTL Verilog RTL Verilog RTL Verilog Verilog Parser Elaborator SDFG Generation FSM Extraction Data Path Extraction GALS Partition Async Pipeline Insertion Netlist Writer Constraint Generation RTL Verilog RTL Verilog Async Netlist Constraint Cell Libs 05/2012 09/2012 11/2012 02/2013 10/2013

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Progress from Last Meeting

  • Automatic FSM classification

– Add more types in SDFG – Automatic identify FSMs, counters and flags.

  • Automatic data path extraction

– Removing control arcs – Trim the SDFG afterwards

  • Preliminary partition analysis

– All data outputs have variable data rate

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SLIDE 7

Signal-Level Data Flow Graph

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always @(posedge clk or negedge rstn) if(~rstn) state <= R; else state <= state_nxt; always @(state or cnt) // next state if(cnt == 0) case(state) R: state_nxt = YR; YR: state_nxt = G; G: state_nxt = YG; default: state_nxt = R; endcase // case (state) else state_nxt = state; always @(posedge clk or negedge rstn) if(~rstn) cnt <= 0; else if(cnt == 0) case(state) R: cnt <= 2; YR: cnt <= 49; G: cnt <= 4; default: cnt <= 49; endcase // case (state) else cnt <= cnt - 1; assign red = state == R ? 1 : 0; assign green = state == G ? 1 : 0; assign yellow = (state == YR || state == YG) ? 1 : 0;

I I FF FF O O O state cnt state_nxt yellow green red rstn clk I FF O i_port

  • _port

combi_block seq_block reset clock control data

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Register Relation Graph

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I I FF FF O O O state cnt green red rstn clk

I I FF FF O O O state cnt state_nxt yellow green red rstn clk

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SLIDE 9

Add Extra Arc Types

  • Old typing systems

– Data – Control – Clock; Reset

  • New typing system

– Self-loop; Calculation; Assign; Data* – Compare; Equate; Logic; Address; Control* – Clock; Reset

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Recognition Criteria

  • State machine

– Self (equate); Out(equate); In(!data)

  • Counter

– Self(Calculate); Out(equate|compare|logic); In(!data)

  • Address

– Self(default); Out(address); In(!data)

  • Flag

– Self(All); Out(logic); In(!data)

  • Other

– Self(All); Out(control); in(!data)

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FSM report

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  • SUMMARY:
  • In this extraction, 2074 nodes has been scanned, in which 120 nodes are registers.
  • In total 30 FSM controllers has been found in 101 potential FSM

registers.

  • The extracted FSMs are listed below:
  • [1] dwb_biu/aborted_r FLAG
  • [2] dwb_biu/valid_div CNT|FLAG
  • [3] iwb_biu/aborted_r FLAG
  • [4] iwb_biu/previous_complete FLAG
  • [5] iwb_biu/valid_div CNT|FLAG
  • [6] or1200_cpu/or1200_ctrl/sig_syscall FLAG
  • [7] or1200_cpu/or1200_ctrl/sig_trap FLAG
  • [8] or1200_cpu/or1200_except/delayed_iee FLAG
  • [9] or1200_cpu/or1200_except/ex_dslot FLAG
  • [10] or1200_cpu/or1200_except/except_type FSM|ADR
  • [11] or1200_cpu/or1200_except/extend_flush FSM|FLAG
  • [12] or1200_cpu/or1200_except/state FSM|FLAG
  • [13] or1200_cpu/or1200_if/saved FLAG
  • [14] or1200_cpu/or1200_mult_mac/div_free FLAG
  • [15] or1200_cpu/or1200_operandmuxes/saved_a FLAG
  • [16] or1200_cpu/or1200_operandmuxes/saved_b FLAG
  • [17] or1200_dc_top/or1200_dc_fsm/cache_inhibit FLAG
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Data Path Extraction

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RTL RTL RTL Parser Abstract Syntax Tree Signal-Level DFG Remove Control Arcs Graph Trimming Data Paths Data path extraction

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Greatest Common Divisor

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I I I I I FF FF O O

Load_P Load A_P A B_P B Clock_P Clock Reset_P Reset A_Hold A_lessthan_B A_New Y Done Done_P Y_P

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Remove Control Arcs

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I I I I I FF FF O O

Load_P Load A_P A B_P B Clock_P Clock Reset_P Reset A_Hold A_lessthan_B A_New Y Done Done_P Y_P

I I I I I FF FF O O

Load_P Load A_P A B_P B Clock_P Clock Reset_P Reset A_Hold B_Hold A_lessthan_B A_New Y Done Done_P Y_P

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Trim the SDFG

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I I I I I FF FF O O

Load_P Load A_P A B_P B Clock_P Clock Reset_P Reset A_Hold B_Hold A_lessthan_B A_New Y Done Done_P Y_P

I I FF FF O

A_P A B_P B A_Hold B_Hold A_New Y Y_P

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Permutation Module (SHA-3)

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I FF O

in_P in i

  • ut_P

MODULE

rconst rc

MODULE

round round_in round_out

FF

  • ut

FF

  • ne

round round const counter

in

  • ut
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Large Scale Designs

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Performance

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Partition Detection

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FSM FSM Through Wire pipeline pipeline Variable data FSM Control FSM

Classify each output port as fixed rate (through wire or pipeline) or variable rate (variable data, FSM control, FSM) A Module with most output ports with variable rate is considered a potential partition.

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Partition Detection Report

pixel_generator (module vga_pgen) with rate 0.470588 < 0.8: hsync_o 0 [pixel_generator/hsync_o:data-pipeline] cc0_adr_o 0 [through wire] cc1_adr_o 0 [through wire] stat_acmp 1 [pixel_generator/stat_acmp:self-fsm:ctl- fsm(pixel_generator/stat_acmp)] blank_o 0 [pixel_generator/blank_o:data-pipeline] wbm/clut_sw_fifo (module vga_fifo_aw4_dw1) with rate 1 >= 0.8: aempty 1 [wbm_ack_i_P:data- pipeline][pixel_generator/color_proc/vdat_buffer_rreq:ctl- fsm(pixel_generator/rgb_fifo/nword] full 1 [wbm/clut_sw_fifo/full:ctl- fsm(wbm/stb_o,wbm/clut_sw_fifo/rp,wbm/clut_sw_fifo/wp)] empty 1 [wbm/clut_sw_fifo/empty:ctl- fsm(wbm/stb_o,wbm/clut_sw_fifo/rp,wbm/clut_sw_fifo/wp)] nword 1 [wbm/clut_sw_fifo/nword:ctl-fsm(wbm/stb_o)] afull 1 [wbm_ack_i_P:data- pipeline][pixel_generator/color_proc/vdat_buffer_rreq:ctl- fsm(pixel_generator/rgb_fifo/nword,pixel_generator/color_proc/colcnt]

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Future Works

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  • Partition Detection

– Rather than evaluate all output ports, evaluate

  • nly data output ports.

– Replace the pattern detection with data rate estimation (possibly need state space analyses) – Back-annotate data rate to data path graph – Interface recognition (mem, FIFO, handshake, bus, etc)

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Conclusion

  • Utilizing signal-level data flow graph, the sync

Verilog synthesizer is able to:

– Detect and classify controllers – Detect data paths – Detect potential partitions (preliminary)

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