Future Scaling of Processor- Memory Interfaces Jung Ho Ahn , Norman - - PowerPoint PPT Presentation

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Future Scaling of Processor- Memory Interfaces Jung Ho Ahn , Norman P. Jouppi , Christos Kozyrakis , Jacob Leverich , Robert S. Schreiber HP Labs, Stanford University, Seoul National University Executive summary

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Future Scaling of Processor- Memory Interfaces

Jung Ho Ahn†§, Norman P. Jouppi †, Christos Kozyrakis‡, Jacob Leverich‡, Robert S. Schreiber†

†HP Labs, ‡Stanford University, §Seoul National University

SLIDE 2

Nov 19, 2009 2

Executive summary memory system

Challenges Solutions Holistic assessments

performance reliability energy efficiency Multicore DIMM rank subsetting efficiency/latency/ throughput tradeoffs system-wide multithreaded/consolidated chipkill capacity vs. efficiency

Main

SC09 – Future Scaling of Processor-Memory Interfaces

SLIDE 3

Issues on DRAM based main memory

Chip Multiprocessors (CMPs) demand

High capacity High bandwidth

Global wires improve slowly

Energy efficiency challenges = DRAM power matters! Performance/power variation by access patterns

Hard/soft errors

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SLIDE 4

How DRAM works

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wl bit

DRAM – 1T1C cell

bank 7 bank 1 request data Row decoder Sense amplifier Column decoder DRAM Memory array bank 0 16,384 r

8,192 columns

SLIDE 5

Performance/power variations

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SLIDE 6

DIMM = Dual Inline Memory Module

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Overfetching problem DRAM row size = 8kb, 8 or 16 DRAMs per DIMM Cache line size = 512b Over 99% of bits are unused if row/col = 1

SLIDE 7

Solution = Multicore DIMM

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MCDIMM features VMD = Virtual Memory Device : rank subsetting Demux register Over 99% of bits are unused if row/col = 1

SLIDE 8

Demux register

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SLIDE 9

Alternative solution = mini-rank

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MCDIMM vs. mini-rank Register for data path vs. control path Timing constraint due to access interference Load balancing between rank subsets

SLIDE 10

Governing equations

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D : # of DRAM chips per subset S : # of subsets per rank R : # of ranks per channel SP : static power of a DRAM chip ERW : energy needed to read/write a bit BWRW : read/write bandwidth per memory channel EAP : energy to activate/precharge a row fAP : frequency of activate/precharge per memory channel

Total main memory power = D · S · R · SP + ERW · BWRW + D · EAP · fAP

SLIDE 11

Governing equations

11 Nov 19, 2009 SC09 – Future Scaling of Processor-Memory Interfaces

BWRW : read/write bandwidth per memory channel fAP : frequency of activate/precharge per memory channel fCM : frequency of cache miss CL : line size of last-level cache : row/col (bank conflict ratio)

fAP = · fCM = · = · fAP fCM fAP fCM BWRW CL BWRW CL

SLIDE 12

n multicore applications

12 Nov 19, 2009 SC09 – Future Scaling of Processor-Memory Interfaces

SLIDE 13

MCDIMM reliability issues

SECDED

Single error correction, double error detection Typically, (64 + 8) ECC solution is enough.

SCCDCD

Single chip-error correction, double chip-error detection Chipkill Implementations

Interleaving SECDED over multiple ranks
Employing stronger error correcting code

2b + l additional bits to correct b bits of bursty error + to detect l bits of bursty error

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SLIDE 14

Multicore configuration

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DIMM MT Core L1$ MT Core L1$ MT Core L1$ MC MC MC MC L2$ Dir Dir L2$ Dir L2$ L2$ Dir MT Core L1$

SLIDE 15

Experimental setup

System architecture

32nm, 2GHz in-order CMT, max IPC = 16, 64 threads 64B $ line, 4 1MB L2 $ hierarchical MESI, reverse directory

Simulator/modeling

Intel Pin based in-house simulator CACTI

Applications

SPLASH-2/PARSEC/SPEC2006

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SLIDE 16

Energy-delay product & system power with 1 rank per memory channel

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SLIDE 17

Energy-delay product & system power with 1 rank per memory channel

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SPLASH-2 SPEC CPU 2006 PARSEC

SLIDE 18

Energy-delay product & system power with 4 ranks per memory channel

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SLIDE 19

Energy-delay product & system power with 4 ranks per memory channel

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SPLASH-2 SPEC CPU 2006 PARSEC

SLIDE 20

Energy-delay product & system power with Chipkill enabled

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SLIDE 21

Energy-delay product & system power with Chipkill enabled

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SPLASH-2 SPEC CPU 2006 PARSEC

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Nov 19, 2009 22

Conclusion

Multicore DIMM Instantiation of rank subsetting Gain energy efficiency & concurrency Sacrifice serialization latency Advantage in EDP (energy-delay product) with proper subsetting Energy-efficient, capacity-inefficient reliability solution Challenges on main memory systems Performance/capacity demands Energy-efficiency goals Reliability constraints

SC09 – Future Scaling of Processor-Memory Interfaces