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From Spaghetti wires to Noc Marcello Coppola MPSOC05 STMicroelectronics On-chip communication Infrastructure The on-chip communication Infrastructure is a fundamental tool for composing large, complex SoC SOC Architecture Camera I/F SOC


  1. From Spaghetti wires to Noc Marcello Coppola MPSOC05 STMicroelectronics

  2. On-chip communication Infrastructure The on-chip communication Infrastructure is a fundamental tool for composing large, complex SoC SOC Architecture Camera I/F SOC Architecture Storage Camera I/F Display Storage Display - SIMD Audio OLED - SIMD Audio OLED - VLIW DVD Screen TFT - VLIW Screen Image TFT Image - HW coprocessor I/F LCD - HW coprocessor I/F processing LCD processing Wires => Bus =>network Wires => Bus =>network Content Content Systeme Video Audio Systeme Video Audio protection protection Set-Top Box Digital TV CMG - Imaging Division company confidential Company confidential ADVANCED SYSTEM TECHNOLOGY

  3. On chip communication: Evolution B Bus B Custom Bridged Bus B B Multi Layer Bus NoC Pipelined Crossbar Company confidential ADVANCED SYSTEM TECHNOLOGY

  4. NoC definition A flexible and scalable packet-based on-chip micro-network designed according to a layered methodology Methodology view: NoC is a communication-centric platform Architecture view: NoC is a packet-based micro-network Convergence of multiple disciplines: (On-chip communication, Parallel computing, Networking) NoC must be a TRADE-OFF synthesis Company confidential ADVANCED SYSTEM TECHNOLOGY

  5. Industry Solutions Multi Layer bus Pipelined Crossbar AMBA Arteris AXI ….. CORECONNECT STBUS ………. NoC Athereal CrossBow Technologies STNOC ….. Company confidential ADVANCED SYSTEM TECHNOLOGY

  6. Source M. Laiolo NEC Company confidential ADVANCED SYSTEM TECHNOLOGY

  7. Micro Trends DSM and global wires Global wire delay • Global wire delay increases • Multiple clock latency • Synchronization issue Power dissipation • For interconnection do not scale Signal integrity Interconnect is rapidly dominating the delay, power, and area of ICs From Digital Integrated Circuits – J.M. Rabay Company confidential ADVANCED SYSTEM TECHNOLOGY

  8. STNoC Ring Spidergon STNoC topology range (degree 2-3) STNoC , the ST Network on Chip Solve today SoC integration issues Anticipate next complex architectures integration challenge Leverage on ST key technology and methodology Company confidential ADVANCED SYSTEM TECHNOLOGY

  9. Draining the Swamp If you can escape from the Spaghetti interconnection Jungle, you can get a long- term commitment in Platform Reuse and Time to Market STNoC challenge bring NoC innovative technology to silicon in the near future Company confidential ADVANCED SYSTEM TECHNOLOGY

  10. Thanks for listening! To get in touch: Marcello Coppola Marcello.Coppola@st.com Company confidential ADVANCED SYSTEM TECHNOLOGY

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