From Spaghetti wires to Noc Marcello Coppola MPSOC05 - - PowerPoint PPT Presentation

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Dec 26, 2023 322 likes •445 views

From Spaghetti wires to Noc Marcello Coppola MPSOC05 STMicroelectronics On-chip communication Infrastructure The on-chip communication Infrastructure is a fundamental tool for composing large, complex SoC SOC Architecture Camera I/F SOC

SLIDE 1

STMicroelectronics

From Spaghetti wires to Noc

Marcello Coppola MPSOC05

SLIDE 2

ADVANCED SYSTEM TECHNOLOGY CMG - Imaging Division company confidential Company confidential

On-chip communication Infrastructure

Camera I/F Camera I/F Image processing Image processing Display OLED TFT LCD Display OLED TFT LCD Storage Audio Screen I/F Storage Audio Screen I/F

SOC Architecture

SIMD
VLIW
HW coprocessor

SOC Architecture

SIMD
VLIW
HW coprocessor

Wires => Bus =>network Wires => Bus =>network

Systeme Systeme Audio Audio Video Video Content protection Content protection

DVD Digital TV

Set-Top Box

The on-chip communication Infrastructure is a fundamental tool for composing large, complex SoC

SLIDE 3

ADVANCED SYSTEM TECHNOLOGY Company confidential

On chip communication: Evolution

B B

Custom Bus Bridged Bus NoC

B B

Multi Layer Bus Pipelined Crossbar

SLIDE 4

ADVANCED SYSTEM TECHNOLOGY Company confidential

NoC definition

A flexible and scalable packet-based on-chip micro-network designed according to a layered methodology

Methodology view: NoC is a communication-centric platform Architecture view: NoC is a packet-based micro-network Convergence of multiple disciplines: (On-chip communication, Parallel computing, Networking)

NoC must be a TRADE-OFF synthesis

SLIDE 5

ADVANCED SYSTEM TECHNOLOGY Company confidential

Industry Solutions

Multi Layer bus

AMBA AXI CORECONNECT STBUS ……….

Pipelined Crossbar

Arteris …..

NoC

Athereal CrossBow Technologies STNOC …..

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ADVANCED SYSTEM TECHNOLOGY Company confidential

Source M. Laiolo NEC

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ADVANCED SYSTEM TECHNOLOGY Company confidential

DSM and global wires

Global wire delay

Global wire delay increases
Multiple clock latency
Synchronization issue

Power dissipation

For interconnection do not scale

Signal integrity

From Digital Integrated Circuits – J.M. Rabay

Interconnect is rapidly dominating the delay, power, and area of ICs

Micro Trends

SLIDE 8

ADVANCED SYSTEM TECHNOLOGY Company confidential

STNoC

Ring Spidergon STNoC topology range (degree 2-3)

STNoC, the ST Network on Chip Solve today SoC integration issues Anticipate next complex architectures integration challenge Leverage on ST key technology and methodology

SLIDE 9

ADVANCED SYSTEM TECHNOLOGY Company confidential

Draining the Swamp

If you can escape from the Spaghetti interconnection Jungle, you can get a long- term commitment in Platform Reuse and Time to Market

STNoC challenge

bring NoC innovative technology to silicon in the near future

SLIDE 10

ADVANCED SYSTEM TECHNOLOGY Company confidential

Thanks for listening!

To get in touch: Marcello Coppola Marcello.Coppola@st.com