From CoPop to CoWare: What are the challenges? Paul Pop Embedded - - PDF document

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1 December 12, 2001

From CoPop to CoWare: What are the challenges?

Paul Pop

Embedded Systems Laboratory Computer and Information Science Dept. Linköpings universitet

Codesign Graduate Course Paul Pop 2 December 12, 2001

Codesign Environments

Application domain

Architecture, communication

Internal representation, underlying model Input & Output Design flow

Problems solved Tools Interfaces

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Simulation Hardware/Software partitioning, mapping Synthesis Transformational codesign approach User guided partitioning Incremental design process

Scheduling Communication synthesis Mapping Architecture selection

Design Flow Data model

Processes, ports, protocols, threads, terminals, channels

Communication: Remote Procedure Call SOLAR Simple architecture model Conditional process graphs Simple architecture model Internal Representation Heterogeneous systems

• n a chip

Distributed and communicating systems, library of protocols Automotive electronics, communication: time triggered protocol Application Domain

• D. Verkest et al.,

IMEC, CoWare

http://www.coware.com

A.A.Jerraya et al., System-Level Synthesis Group, TIMA, France Paul Pop et al., Embedded Systems Lab, Liköpings universitet General Information

CoWare COSMOS CoPop

Tools: At a Glance

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CoPop

General information

Paul Pop et al., Embedded Systems Lab, Liköpings universitet

http://www.ida.liu.se/~paupo

Application domain

Automotive electronics, communication: time triggered protocol

Internal representation

Conditional process graphs Simple architecture model

Design flow: Incremental design process

Scheduling Communication synthesis Mapping Architecture selection

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Design Flow

System Specification Architecture Selection Scheduling Integration Hardware Synthesis Partitioning Software Synthesis

• Scheduling…

Scheduling of processes and messages for distributed hard real-time applications with control and data dependencies in the context of a given communication protocol.

• Communication synthesis…

Optimization of the parameters of the communication protocol so that the overall system performance is increased and the imposed timing constraints are satisfied.

• Mapping…

Incremental Design Process

• Architecture modelling, selection…

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Design Flow: System Specification using UML

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Design Flow: UML to Java

public void run() { Message[] msgs = receive("cem&&ecm&&tcm&&abs&&ccont"); // .. Extracting messages from array msgs boolean lowBattery = cemMsg.vbatt < 9; boolean atglpNotDrive = tcmMsg.atglp != Signals.DRIVE && tcmMsg.atglp != Signals.DRIVE_L; boolean allQualit iesGood = tcmMsg.atglpqf == Signals.GOOD && absMsg.vsqf == Signals.GOOD &&tcmMsg.vsaqf == Signals.GOOD; boolean vsVsaDiffHigh = Math.abs(absMsg.vs -tcmMsg.vsa)/absMsg.vs > 0.05; boolean wrongSpeed = absMsg.vs < 35 || absMsg.vs > 200; if (!ccont || lowBattery || atglpNotDrive || !allQualit iesGood || vsVsaDiffHigh || wrongSpeed || cemMsg.cccanc || ecmMsg.bpa) { send("cca_error", null); } else { send("cca_is_button_pressed", cemMsg); } Message[] mmsgs = receive("cca_error||cca_is_button_pressed"); cca = (Boolean) getDataFromMessageArray(mmsgs, "cca_error"); if (cca == null) { cca = (Boolean) getDataFromMessageArray(mmsgs, "cca_is_button_pressed"); } send("ccf", cca); send("ccsp", cca); } Codesign Graduate Course Paul Pop 8 December 12, 2001

Design Flow: Java to CPG

Vehicle cruise controller. Modelled with a CPG of 32 processes and two conditions. Mapped on 5 nodes: CEM, ABS, ETM, ECM, TCM.

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CPG Viewer/Editor

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Conditional Process Graph (CPG)

P4 P4 P5 P5 P7 P7 P13 P13 P15 P15 First processor Second processor ASIC C C D D P0 P18 P1 P1 P2 P2 P3 P3 P6 P6 P8 P8 P9 P9 P10 P10 P11 P11 P12 P12 P14 P14 P16 P16 P17 P17 C K K

P0 P18 P1 P2 P3 P6 P8 P9 P10 P11 P12 P14 P16 P17

Subgraph corresponding to D∨C∨K

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Distributed Real-Time Systems

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Event-Triggered vs. Time-Triggered

Event-triggered: activation of processes and transmission of messages is done at the occurrence of significant events. Time-triggered: activation of processes and transmission of messages is done at predefined points in time. processes messages event-triggered time-triggered

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Hardware Architecture

I/O Interface TTP Controller CPU RAM ROM ASIC Node

Hard real-time distributed systems. Nodes interconnected by a broadcast communication channel. Nodes consisting of: TTP controller, CPU, RAM, ROM, I/O interface, (maybe) ASIC. Communication between nodes is based on the time-triggered protocol. S0 S1 S2 S3 S0 S1 S2 S3 TDMA Round Cycle of two rounds Slot Bus access scheme: time-division multiple-access (TDMA). Schedule table located in each TTP controller: message descriptor list (MEDL).

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Problem Formulation: Scheduling

Input

• Safety-critical application with several operating modes.
• Each operating mode is modelled by a CPG.
• The system architecture and mapping of processes to nodes are given.
• The worst case delay of each process is known.

Output

• Local schedule tables for each node and the MEDL for the TTP

controllers.

• Delay on the system execution time for each operating mode,

so that this delay is as small as possible.

Note

• Processes scheduled with static cyclic non-preemptive scheduling,

and messages according to the TTP.

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Design Flow: Scheduler

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Scheduling and Communication Synthesis

P1 P1 P4 P4 P2 P2 P3 P3 m1 m2 m3 m4

S1 S0 Round 1 Round 2 Round 3 Round 4 Round 5 P1 P4 P2 m1 m2 m3 m4 P3

24 ms

Round 1 P1 Round 2 Round 3 Round 4 S1 S0 m1 m2 m3 m4 P2 P3 P4

22 ms

Round 1 Round 2 Round 3 S1 S0 P2 P3 P4 P1 m1 m2 m3 m4

20 ms

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S1 S0 Round 1 Round 2 Round 3 Round 4 Round 5 P1 P4 P2 m1 m2 m3 m4 P3

P1 P4 P2 P3

N1 N2 N1 N2 Bus

“Classic” Mapping and Scheduling

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Problem Formulation: Mapping

Input

A set of existing applications modelled using process graphs. A current application to be mapped modelled using process graphs. Each process graph in the application has its own period and deadline. Each process has a potential set of nodes to be mapped to and a WCET. The system architecture is given.

Output

A mapping and scheduling of the current application, so that: Requirement a: constraints of the current application are satisfied and minimal modifications are performed to the existing applications. Requirement b: new future applications can be mapped

• n the resulted system.

Notes

Hard real-time applications Static cyclic scheduling of processes and messages Time-triggered protocol, TDMA

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Incremental Design Process

No modifications are performed to the existing applications.

Existing applications

N-1

Map and schedule so that the future applications will have a chance to fit.

Current applications

N

Do not exist yet at Version N!

Future applications

Version N+1

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COSMOS

General information

A.A.Jerraya et al., System-Level Synthesis Group, TIMA, France

http://tima.imag.fr/SLS/

Application domain

Distributed and communicating systems, library of protocols

Internal representation

SDL -> SOLAR -> C/VHDL Simple architecture model

Design flow: transformational codesign approach

User guided partitioning

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Problems with Automation

To be successful, very restrictive. Lack of a universal estimation method, no realistic evaluation procedure No correspondence (to the user, no explanation) between the initial specification and the resulting architecture. The designer already has a good solution in mind when it starts working. The design is of complex systems is iterative.

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Design Flow

Traditional codesign flow Transformational codesign flow

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User-Guided Transformational Partitioning

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SOLAR

Transformations work on the SOLAR model Internal design representation

Extended Finite State Machines for behaviour Remote procedure call for communication

High level communication concepts Channels Shared global variables Can model complex communication protocols

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SOLAR, Cont.

Basic concepts: State table, Design unit, Channel unit

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Transformations: Step 1

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Transformations: Step 2

Functional decomposition (partitioning)

Transform behaviours (state tables) Split, Merge, Move, Flat

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Transformations: Step 3

Structural reorganization (mapping, allocation)

Distributes the behaviours to design units (processors) Split, Merge, Move, Map, Flat

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Transformations: Step 4

Communication transformation (communication synthesis)

From high level primitives to protocols from a library Map, Merge

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Example: Robot Arm Controller

Transfor mations Transfor mations

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Example: Answering Machine

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Functional Decomposition: Split

Split

Decomposes a sequential machine into a set of submachines. Each resulting machine can be placed into a different partition. Control signals and wait states have to be added.

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Functional Decomposition: Merge

Merge

Groups a set of sequential machines into a unique machine. Sharing of resources.

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Functional Decomposition: Move

Move

Transforms the hierarchy. Can be used to move code from a software partition to a hardware partition.

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Structural Reorganization: Split

Split

• Works on the behaviour of parallel processes (state tables) to split them into

a set of independent modules (design units).

• Shared data converted to abstract channels.

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Structural Reorganization, Cont.

Merge

Groups a set of modules into a new design unit. Clusters the modules that will be assigned to the same processor.

Move

Moves a design unit in the hierarchy. Used to prepare a merge operation.

Map

Decides the hardware or software implementation.

Flat

Structural flattening operation on the hierarchy.

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Communication Transformation

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Structural Reorganization: Split

Split

• Works on the behaviour of parallel processes (state tables) to split them into

a set of independent modules (design units).

• Shared data converted to abstract channels.

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CoWare

General information

• D. Verkest et al., IMEC, CoWare

http://www.coware.com

Application domain

Heterogeneous systems on a chip

Internal representation

Data model

Processes, ports, protocols, threads, terminals, channels

Communication: Remote Procedure Call

Design flow

Simulation Hardware/Software partitioning, mapping Synthesis

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Design Flow

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Internal Representation

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Example: Spread-Spectrum Pager

Spread-spectrum pager

DSP

Codesign

Conceptual specification Partitioning and mapping Communication selection Implementation of components Interface synthesis

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Example: Functional Specification

Each component corresponds to a process implementing a specific function of the pager. This functional decomposition determines the initial partitioning. The arrows in between the processes indicate communication via RPC.

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Example: Architectural Description

Interconnection of processes Processes are processor implementations Structural VHDL

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Example: Partitioning

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Implementation of Components

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What are the challenges?

What is it needed to make the tools useful?

Usable (user interface) Interoperability End-user modifiability Collaboration Support the cognitive processes of the user

Visual representations of models Workflow Help systems Computational design critics