From CoPop to CoWare: What are the challenges? Paul Pop Embedded Systems Laboratory Computer and Information Science Dept. Linköpings universitet 1 December 12, 2001 Codesign Environments � Application domain � Architecture, communication � Internal representation, underlying model � Input & Output � Design flow � Problems solved � Tools � Interfaces Codesign Graduate Course 2 Paul Pop December 12, 2001 1
Tools: At a Glance CoPop COSMOS CoWare Paul Pop et al., Embedded A.A.Jerraya et al., D. Verkest et al., General Systems Lab, System-Level Synthesis IMEC, CoWare Information Liköpings universitet Group, TIMA, France http://www.coware.com Automotive electronics, Application Heterogeneous systems Distributed and communication: Domain on a chip communicating systems, time triggered protocol library of protocols Data model SOLAR Processes, ports, protocols, Internal Conditional process graphs threads, terminals, channels Simple architecture Representation Simple architecture model Communication: model Remote Procedure Call Incremental design process Simulation Transformational Scheduling Hardware/Software codesign approach Design Flow Communication synthesis partitioning, mapping Mapping User guided partitioning Synthesis Architecture selection Codesign Graduate Course 3 Paul Pop December 12, 2001 CoPop � General information � Paul Pop et al., Embedded Systems Lab, Liköpings universitet � http://www.ida.liu.se/~paupo � Application domain � Automotive electronics, communication: time triggered protocol � Internal representation � Conditional process graphs � Simple architecture model � Design flow: Incremental design process � Scheduling � Communication synthesis � Mapping � Architecture selection Codesign Graduate Course 4 Paul Pop December 12, 2001 2
Design Flow System Specification Scheduling… � Scheduling of processes and messages for distributed hard Architecture real-time applications with control and data dependencies Selection in the context of a given communication protocol. Communication synthesis… � Partitioning Optimization of the parameters of the communication protocol so that the overall system performance is increased and the imposed timing constraints are satisfied. Scheduling � Mapping… Hardware Software Synthesis Synthesis Incremental Design Process � Architecture modelling, selection… Integration Codesign Graduate Course 5 Paul Pop December 12, 2001 Design Flow: System Specification using UML Codesign Graduate Course 6 Paul Pop December 12, 2001 3
Design Flow: UML to Java public void run() { Message[] msgs = receive("cem&&ecm&&tcm&&abs&&ccont"); // .. Extracting messages from array msgs boolean lowBattery = cemMsg.vbatt < 9; boolean atglpNotDrive = tcmMsg.atglp != Signals.DRIVE && tcmMsg.atglp != Signals.DRIVE_L; boolean allQualit iesGood = tcmMsg.atglpqf == Signals.GOOD && absMsg.vsqf == Signals.GOOD &&tcmMsg.vsaqf == Signals.GOOD; boolean vsVsaDiffHigh = Math.abs(absMsg.vs -tcmMsg.vsa)/absMsg.vs > 0.05; boolean wrongSpeed = absMsg.vs < 35 || absMsg.vs > 200; if (!ccont || lowBattery || atglpNotDrive || !allQualit iesGood || vsVsaDiffHigh || wrongSpeed || cemMsg.cccanc || ecmMsg.bpa) { send("cca_error", null); } else { send("cca_is_button_pressed", cemMsg); } Message[] mmsgs = receive("cca_error||cca_is_button_pressed"); cca = (Boolean) getDataFromMessageArray(mmsgs, "cca_error"); if (cca == null) { cca = (Boolean) getDataFromMessageArray(mmsgs, "cca_is_button_pressed"); } send("ccf", cca); send("ccsp", cca); } Codesign Graduate Course 7 Paul Pop December 12, 2001 Design Flow: Java to CPG � Vehicle cruise controller. � Modelled with a CPG of 32 processes and two conditions. � Mapped on 5 nodes: CEM, ABS, ETM, ECM, TCM. Codesign Graduate Course 8 Paul Pop December 12, 2001 4
CPG Viewer/Editor Codesign Graduate Course 9 Paul Pop December 12, 2001 Conditional Process Graph (CPG) Subgraph corresponding to P 0 P 0 D ∨ C ∨ K P 1 P 1 P 11 P 11 P 1 P 11 D D P 2 P 2 P 3 P 3 P 2 P 3 C C C P 12 P 12 P 13 P 12 P 13 P 6 P 6 P 6 K K P 4 P 5 P 4 P 5 P 14 P 14 P 16 P 16 P 14 P 16 P 8 P 8 P 9 P 9 P 15 P 8 P 9 P 15 P 7 P 7 P 17 P 17 P 17 P 10 P 10 P 10 � First processor � Second processor � ASIC P 18 P 18 Codesign Graduate Course 10 Paul Pop December 12, 2001 5
Distributed Real-Time Systems Codesign Graduate Course 11 Paul Pop December 12, 2001 Event-Triggered vs. Time-Triggered � Event-triggered : activation of processes and transmission of messages is done at the occurrence of significant events. � Time-triggered : activation of processes and transmission of messages is done at predefined points in time. processes messages event-triggered time-triggered Codesign Graduate Course 12 Paul Pop December 12, 2001 6
Hardware Architecture I/O Interface � Hard real-time distributed systems. RAM � Nodes interconnected by a broadcast ROM CPU communication channel. ASIC � Nodes consisting of: TTP controller, CPU, TTP Controller RAM, ROM, I/O interface, (maybe) ASIC. � Communication between nodes is based on Node the time-triggered protocol. � Bus access scheme: time-division multiple-access (TDMA). S 0 S 1 S 2 S 3 S 0 S 1 S 2 S 3 Slot � Schedule table located in each TTP controller: message descriptor list (MEDL). TDMA Round Cycle of two rounds Codesign Graduate Course 13 Paul Pop December 12, 2001 Problem Formulation: Scheduling Input � Safety-critical application with several operating modes. � Each operating mode is modelled by a CPG. The system architecture and mapping of processes to nodes are given. � The worst case delay of each process is known. � Output � Local schedule tables for each node and the MEDL for the TTP controllers. Delay on the system execution time for each operating mode, � so that this delay is as small as possible. Note Processes scheduled with static cyclic non-preemptive scheduling , � and messages according to the TTP. Codesign Graduate Course 14 Paul Pop December 12, 2001 7
Design Flow: Scheduler Codesign Graduate Course 15 Paul Pop December 12, 2001 Scheduling and Communication Synthesis P 1 P 4 P 2 P 3 24 ms m 3 m 4 S 1 S 0 m 1 m 2 Round 1 Round 2 Round 3 Round 4 Round 5 P 1 P 1 P 1 P 4 m 1 m 2 P 3 P 2 22 ms m 3 m 4 m 1 S 0 S 1 m 2 Round 1 Round 2 Round 3 Round 4 P 2 P 3 P 2 P 3 P 4 P 1 m 3 m 4 20 ms P 2 P 3 P 4 m 3 m 4 P 4 S 0 S 1 m 1 m 2 Round 1 Round 2 Round 3 Codesign Graduate Course 16 Paul Pop December 12, 2001 8
“Classic” Mapping and Scheduling N 1 N 2 P 4 P 3 P 1 P 2 P 1 N 1 P 4 P 2 P 3 N 2 m 3 m 4 S 1 S 0 m 1 m 2 Bus Round 1 Round 2 Round 3 Round 4 Round 5 Codesign Graduate Course 17 Paul Pop December 12, 2001 Problem Formulation: Mapping Input � A set of existing applications modelled using process graphs. � A current application to be mapped modelled using process graphs. � Each process graph in the application has its own period and deadline . � Each process has a potential set of nodes to be mapped to and a WCET . � The system architecture is given. Output � A mapping and scheduling of the current application , so that: Requirement a: constraints of the current application are satisfied and minimal modifications are performed to the existing applications. Requirement b: new future applications can be mapped on the resulted system. Notes � Hard real-time applications � Static cyclic scheduling of processes and messages � Time-triggered protocol, TDMA Codesign Graduate Course 18 Paul Pop December 12, 2001 9
Incremental Design Process Do not exist yet Future at Version N! applications Map and schedule so that the Current Version N+1 future applications applications will have a chance to fit. N No modifications are performed to N-1 Existing the existing applications applications. Codesign Graduate Course 19 Paul Pop December 12, 2001 COSMOS � General information � A.A.Jerraya et al., System-Level Synthesis Group, TIMA, France � http://tima.imag.fr/SLS/ � Application domain � Distributed and communicating systems, library of protocols � Internal representation � SDL -> SOLAR -> C/VHDL � Simple architecture model � Design flow: transformational codesign approach � User guided partitioning Codesign Graduate Course 20 Paul Pop December 12, 2001 10
Problems with Automation � To be successful, very restrictive. � Lack of a universal estimation method, no realistic evaluation procedure � No correspondence (to the user, no explanation) between the initial specification and the resulting architecture. � The designer already has a good solution in mind when it starts working. � The design is of complex systems is iterative. Codesign Graduate Course 21 Paul Pop December 12, 2001 Design Flow Traditional codesign flow Transformational codesign flow Codesign Graduate Course 22 Paul Pop December 12, 2001 11
User-Guided Transformational Partitioning Codesign Graduate Course 23 Paul Pop December 12, 2001 SOLAR � Transformations work on the SOLAR model � Internal design representation � Extended Finite State Machines for behaviour � Remote procedure call for communication � High level communication concepts � Channels � Shared global variables � Can model complex communication protocols Codesign Graduate Course 24 Paul Pop December 12, 2001 12
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