FOSS FPGA Martin Hubek @hubmartin martinhubacek.cz - - PowerPoint PPT Presentation

▶
foss fpga
SMART_READER_LITE
LIVE PREVIEW

FOSS FPGA Martin Hubek @hubmartin martinhubacek.cz - - PowerPoint PPT Presentation

Jun 10, 2023 311 likes •712 views

FOSS FPGA Martin Hubek @hubmartin martinhubacek.cz youtube.com/hubmartin Q = I0 & I1 & I2 & I3 I0 - I3 Q I0 - I3 Q Combinatorial logic 0000 0 1000 0 0001 0 1001 0 0010 0 1010 0 0011 0 1011 0 0100 0 1100

slide-1
SLIDE 1

FOSS FPGA

Martin Hubáček @hubmartin martinhubacek.cz youtube.com/hubmartin

slide-2
SLIDE 2

Q = I0 & I1 & I2 & I3

slide-3
SLIDE 3
slide-4
SLIDE 4

Combinatorial logic

I0 - I3 Q 0000 0001 0010 0011 0100 0101 0110 0111

Q

I0 - I3 Q 1000 1001 1010 1011 1100 1101 1110 1111 1

slide-5
SLIDE 5

Q = I0 & I1 & I2 & I3 if(Q != Q_previous) { … } Q_previous = Q

slide-6
SLIDE 6

Sequential logic

Register Memory Counter

slide-7
SLIDE 7

FPGA fabric

IO, BRAM, PLL, DSP Hard-core/Soft-core peripherals or CPUs

slide-8
SLIDE 8

Official tools

Xilinx Vivado (ISE WebPACK) Intel Quartus (Altera) Lattice Diamond

slide-9
SLIDE 9
slide-10
SLIDE 10
slide-11
SLIDE 11
slide-12
SLIDE 12
slide-13
SLIDE 13

Official tools negatives

Complex many gigabyte tools License installations Non-effective IPs Highest FPGA lines needs licenses

slide-14
SLIDE 14

*$$$

slide-15
SLIDE 15

Generic low-cost FPGA boards

Altera MAX2 + JTAG $10 Altera Cyclone II + $15

https://joelw.id.au/FPGA/CheapFPGADevelopmentBoards

Intel (Altera) CYC1000 / MAX $40 Lattice MachXO2 (FLASH) $30 Lattice IceStick $25

Cyclone III / IV / V

slide-16
SLIDE 16

How to reverse engineer an FPGA?

No details of programming internal logic and bitstream Compare small gradual code changes (change > synthesize > compare bitstream) Fuzzing “de-synthethis”

slide-17
SLIDE 17

http://www.clifford.at/icestorm/bitdocs-1k/ https://knielsen.github.io/ice40_viewer/ice40_viewer.html

slide-18
SLIDE 18

FOSS FPGA chips/boards

IceStorm - iCE40 (ICE40, 8k, 128kb, PLL)

  • TinyFPGA BX $38
  • iCEBreaker
  • Glasgow
  • Olimex iCE40HX8K-EVB
  • ICOboard (Rpi HAT) OpenTechLab YouTube
  • Alhambra (Arduino footprint)

Trellis - ECP5

(85k, 3.7Mb BRAM, 156 18x18 DSPs, 5Gbps SERDES)

  • TinyFPGA EX
  • ULX3S

X-Ray - Xilinx 7-series

slide-19
SLIDE 19

Yosys HDL

(Verilog)

Arachne-pnr IceStorm nextpnr FPGA

JTAG/USB

Source code Synthesis Place&Route Bitstream gen.

*.blif *.pcf Berkeley Logic Interchange Format *.v *.json *.asc Timing driven

slide-20
SLIDE 20

Icestudio

slide-21
SLIDE 21

Demo 01 - Icestudio

slide-22
SLIDE 22

APIO

Apio is a multiplatform toolbox, with static pre-built packages, project configuration tools and easy command interface to verify, synthesize, simulate and upload your verilog designs.

pip install apio==0.4.0b5 tinyprog apio install system scons icestorm iverilog apio drivers --serial-enable apio [build|sim|upload]

slide-23
SLIDE 23

ATOM IDE

slide-24
SLIDE 24

Demo 02 - APIO

slide-25
SLIDE 25

WS2812B Module

Digital RGB(W) LED strips Single wire, precise timing

slide-26
SLIDE 26

Demo 03 - WS2812B

slide-27
SLIDE 27

Simulation

Testbench (*_tb.v) Test each module Icarus Verilog - simulation and synthesis tool (iverilog) Gtkview - Waveform view Verilator - Compile Verilog to C++ EDA Playground https://www.edaplayground.com/x/2bRW

slide-28
SLIDE 28

Demo 04 - Simulation

slide-29
SLIDE 29

PicoSOC

Soft-core RISC-V When is soft-core useful Compilation is faster than synthetis Riscv-none-embed-gcc toolchain Custom peripherals

$ xpm install --global @xpack-dev-tools/riscv-none-embed-gcc@latest

slide-30
SLIDE 30

Two PicoSOCs place&route

https://twitter.com/q3k/status/1024623710165237760

slide-31
SLIDE 31

Demo 05 - RISC-V

slide-32
SLIDE 32

Migen, Litex

Migen, nMigen - python nástroj pro generování komplexního hardware Nekompiluje python, pomáhá tvořit HDL kód LiteX - LiteX is a MiSoC-based SoC builder using Migen as Python DSL that can be used to create SoCs and full FPGA designs.

slide-33
SLIDE 33

HDMI2USB.tv

slide-34
SLIDE 34

Tim has to many projects - LatchUp Edition https://www.youtube.com/watch?v=v7WrTmexod0

slide-35
SLIDE 35

Future

SERDES 5G Partial reconfiguration Glasgow ...

slide-36
SLIDE 36

Registrace zdarma $7000 Prize money 22.-23.listopad Brněnské výstaviště E

https://www.hackathons.cz/

slide-37
SLIDE 37

HWDEV Podcast

Hardware Development Podcast se zaměřuje na zajímavá témata z oblasti vývoje, výroby a oživování elektroniky.

https://soundcloud.com/hwdevpodcast

slide-38
SLIDE 38

@hubmartin martinhubacek.cz www.youtube.com/hubmartin

HWDEV Podcast

Hardware Development Podcast se zaměřuje na zajímavá témata z oblasti vývoje, výroby a oživování elektroniky.

https://soundcloud.com/hwdevpodcast