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FGT T El Elec ectroma romagnetic gnetic Ca Calorim rimeter eter

Maharna arnab b Bhattach achar arjee

Indian Institute of Technology Guwahati

FGT ECAL

• FGT ECAL has three components: Forward ECAL,

Backward ECAL and the Barrel ECAL

• ECAL is required for identification of EM showers (e- / e+

and Gamma showers) & for reconstruction of neutral hadrons such as pi0

• ECAL modules are made of alternating layers of lead and

plastic scintillators

• Each of the extruded plastic scintillator bars of such

layers are readout by a WLS fibre and photon counters (MPPCs), attached at both ends

Proposed Fine-Grained-Tracker (with ECAL modules) for DUNE Near Detector T2K Near Detector (ND280) ECAL

Photon Counter and readout

• We propose to use MPPCs to readout the

scintillator bars

• MPPCs (Multi-Pixel Photon Counters) are

used in the T2K ECAL

― ~56,000 (Hamamatsu S10362-13-050C) used ― 1.3 x 1.3 mm2 active area, 667 pixels (50 μm pixel pitch), ceramic device ― Gain (7.5 x 105) with VO ~70 V ― Photon Detection Efficiency (PDE) at 550 nm: ~25 % ― Dark count rate: < 1.3 Mcps (25° C) at threshold 0.5 p.e.

• Simulation and MPPC characterization is

required to ensure MPPC model meets the design requirement

• Similar MPPCs (Hamamatsu S13360-1350CS)

can be adopted for DUNE-ECAL.

― 1.3 x 1.3 mm2 active area, 667 pixels (50 μm pixel pitch), ceramic device ― Improved Gain (1.7 x 106) at lower VO ~53 V ― better PDE at 450 nm: ~40 % (270 – 900 nm spectral range) ― Lower Dark count rate: 270 kcps (max.) at threshold 0.5 p.e.

MPPC (left) Typical schematic model (right)

Photon Counter and readout

Simulation of the MPPCs attempted to determine the electrical characteristics for comparison during characterization

Electrical model of MPPC and typical response below for certain p.e. events with afterpulse + crosstalk Quenching resistance Rq extracted from I-V curve of forward biased MPPC experimentally, similarly other parameters of MPPC such as diode & parasitic capacitances, etc. [Cd ,Cq, Rd …]

Photon Counter and readout

• Calculation of the parameters based on S.

Seifert’s (Simulation of Silicon Photomultiplier

Signals, IEEE ‘09) approach ― Total Charge, Q = (Cq + Cd) ΔV ― Fired Cells, Np = Ntot – Nf ― Cdp = Cd x Np ― Rqp = Rq / Np ― Cqp = Cq x Np ― CdTOT = N x Cd ― CqTOT = N x Cq

• From the following parameters we can
• btain the signal rise time

― τr = (Cd + Cq).Rd.Rq Rd+Rq

• Necessary in evaluating recovery times and

scintillation pulses

• Also useful to create sub circuits imitating

p.e. events for designing biasing circuit and readout electronics

Photon Counter and readout

• Off the shelf biasing and readout systems can handle a few

MPPCs at a time.

• Thousands of MPPCs require grouping into Front-End Boards

for easier control (case: TripT Front-end Board for the T2K). Similar designs with ASICs used for ATLAS, CMS, ILC, …

TFB of T2K-ND280 ECAL (above) and visible placement in design inside the ECAL Approach adopted for the T2K-ECAL TripT Front-end Board

Photon Counter and readout

• Trip-T is being used by T2K ND280
• Investigating whether we can use similar TripT design or alternatives (SPIROC, EASIROC, …)
• Simulation and testing process for each step of readout ASIC

HVPS Detector Biasing DAC + Preamplifier Shaper Analog Memory ADC …

• MPPC Power requirements

― Supply Voltage, HVO = 40 – 80 V depending on the model ― MPPC Supply Current, IO= 1.0 mA ― Setting Voltage = ± 5 V ― Setting Voltage Res. = 10 mV ― Voltage monitor error = ± 10 mV ― Current monitor error = ± 0.05 mA

• Power Supply specifications (ideal):

― Supply Voltage, VIN = 4.75 ≤ Vs ≤ 5.25V ― Output Voltage, VOUT = 40 - 80 V ― Current Consumption, IIN = 20 mA ― Output Current, IOUT = 2 mA ― Ripple, Vp-p(MAX) = 0.2 mV or better ― Fine adjustable steps res. = 1.8 mV ― Reference Hamamatsu’s C112014-01 Power Supply

HV Power Supply: Options

• AC - DC

― High noise (ripple factor), bulky (add. filter circuit, current reduction), heating issue considering multiple MPPCs

• AC - DC then DC-DC converter

― Lower noise, current and heat dissipation; with AC- DC for multiple FEBs

• Many Switching topologies (SMPS)

― Linear Regulators : *heat dissipation, loss, … ― Buck ― Boost ― Polarity Inverter Switching Regulator ― … ― MOSFETs with PWM drive SMPS using Linear Regulators; Noisy which increases over longer periods

HV Power Supply (SMPS)

• Basic Configuration for SMPS using PWM:
• Maximum Switch Current: Duty Cycle, Efficiency of Converter

(~80%), Inductor Ripple Current

• Inductor and Rectifier Diode Selection
• Output Voltage Setting
• Input, Output Capacitor Selection

HVPS simulation using PWM drive for MOSFET; with different component (L, C,) and PWM driver selections. One/two such power module per FEB supporting 16 ch., 32 ch. or more

Biasing DAC

DAC simulation (0-5V) Step size = 100 mV, Delay = 20 ms, without & with cutoff DAC simulation (0-5V) Step size = 20 mV, Delay = 50 ms, without & with cutoff

• Simulation with a μC + 8-bit DAC for 0 – 5 V biasing
• Important for step size resolution, delay and cutoff voltage
• Resolution increases with 12-bit or higher DACs

ASICs

• Compact, low power option
• To replace the functions of 4 or 16 ch.

readout module (Preamplification, Shaper, DAC, …)

• The ‘SPIROC’ was found to have suitable

specifications (possible Trip-T substitute), more study required

― 36 ch. ASIC. Each ch. charge 1 p.e – 2000 p.e ― 7.2 mm x 4.2 mm ― 5V /3.5V

OMEGA chip: SPIROC workflow

Front-end and Readout Electronics

• Attempt at designing the HVPS, HV DAC, Preamplification

stages with current/voltage sensor, temperature/humidity sensor circuits into modules each with 4 to 16 ch. with good sig- noise ration

• Characterization of the MPPCs with those readout modules
• Added amplification stages in prototype modules to be tested in

the immediate future as needed

• Comparing the tested designs/prototypes with existing ASICs

(TripT, SPIROC, EASIROC, …) with industry collaboration; improvement/development of newer ones

• FPGAs (depending on timing resolution, data transfer speed, …)

specifications study to be done in the near future

Prototyping of module for single MPPC with HVPS, DAC without the amplification stages under development

Acknowledgements to:

My Supervisor Dr. Bipul Bhuyan The Dept. of Physics, IIT-Guwahati

Thank You