Fast Transient Power Converter Using Switched Current Conversion - - PowerPoint PPT Presentation

Fast Transient Power Converter Using Switched Current Conversion Laurence McGarry Advanced Engineering Technology Manager Hong Kong & China Astec Power A Division of Emerson Network Power.

Abstract: Next generation microprocessors continue to require power supplies capable of supporting fast transient loading. Conventional approaches to solving the fast transient issue focus on the use of interleaved buck converters. This approach is fundamentally limited due to the presence of the output inductance, limiting the converter response to a load transient. This paper introduces a novel switched current converter. The converter will switch current to the load or to ground depending on the load transient requirement, providing a theoretically infinite transient response. The research investigates the practical limitations of the converter topology, using simulation to evaluate and optimize the system design. Finally, simulation models and results are presented and suggestions for further design improvements are discussed.

Common Industry Trends

• Intel CPU requirement for VRM

Intel CPU voltage and Current Roadmap

Processor trends well documented : Higher Current Requirements Lower Voltage Processors, tighter regulation range Higher Frequencies Faster Transient Response

Conventional Industry Approaches

Standard approach to resolving the challenge is to use interleaved Buck converters Response time inherently limited by the presence of the output inductor Problem compounded by interconnect and PCB parasitics Continued silicon integration, drive to higher frequencies and possibly an increased number of phases will continue to be a trend regardless of the architecture utilized Switched Current Techniques offer an alternative approach An infinite transient response possible, in theory at least

Volterra 300A/uS Module 369mm

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Conventional Buck Converter

Switched Current Concepts

Currents are switched to the load or to the return path Parallel switching Current Paths are utilized Transient can be supported in the time that it takes to turn the FET On/Off When output current follows processor demand current, significant reduction in output capacitance can be observed The constant current source is derived from a Buck Converter driving a matrix Transformer configuration

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Constant Current Source

Front end Buck converter provides the constant current source Push Pull Converter operating at 100% duty using a ‘Matrix transformer’ provides the input to the current switches at the load side Matrix Transformer: series (primary), parallel (secondary) ferrite cells forming individual isolation for each phase

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LHS source is constant current and could be remote from the end application. RHS Switches could be co- located with the processor to reduce interconnect parasitics and enhance transient response

System Overview and Simulation Model

Front End Buck Converter providing constant current source Push-Pull Converter with Matrix Transformer provides constant current parallel paths Output Current switches; switching current to the load in response to transients or to ground Simulation model: 3 Stage Conversion

• 12V input to 1V, 100A output
• 10 parallel switching paths

Constant Current Source Buck Converter

Buck Constant Current Converter Simple Hysteretic Control Implemented No Output Capacitance 2 level Threshold Control 10A-11A Synch Rectification is used to reduce power loss Switching Frequency Varies according to the Buck Output voltage, reaching maximum while Voutput Buck=0.5Vin Voltage on the output of the Buck is n X Vo

• Where n is the number of switches

turned to the load

Vref Low +5Vcc 10k R2 U18 max961 GND NQ Q LE IN+ SHDN IN- Vcc X1 MAX473 3.3k R13 10k R8 1K R14 10m R15 Ireturn DRV1s U19 max961 GND NQ Q LE IN+ SHDN IN- Vcc 10k R1 +5Vcc Vref High Q4 irf 7822 Q3 irf 7822 U17 HC74D QN Q D RST SET L2 5.6u IC=10.5 12 V15 E3 1 E4 1 Iout

Constant Current Source Buck Converter(cont)

Simulation Results light load

Simulation Results Light load

• Buck output voltage=0.5V
• Output current =10.87A
• Switching Duty cycle=5.55%
• Switching Frequency=110kHz
• Current ripple =694mA

Simulation Results Full load

Simulation Results Full load

• Buck output voltage=11V
• Output current =10.69A
• Switching Duty cycle=93%
• Switching Frequency=133kHz
• Current ripple =760mA

Constant Current Source Buck Converter(cont)

5 10 2 .10 5 4 .10 5 6 .10 5 fs Vo ( ) Vo

fs vs Vo Curve L=5.6uH, ∆I=1A

Simulation Results Dynamic load

• Output voltage slew rate=46V/us
• Output current =10.8A
• Current ripple =828mA

Input Buck Frequency Variation

• The highest frequency =518kHz

(output voltage =5.5V)

• All components are ideal

Simulation result on dynamic load

Push Pull Converter

B ranch 1

L5 2n L4 2n L3 2n Q2 irf6603 TX 1 Q1 irf6603 L2 2n 10.5 I 1 Q4 irf540ns D3 I DEA L 4.7n C3 2k R7 2k R1 4.7n C1 D1 I DEA L Q3 irf540ns

Fixed Duty Cycle of 50% Leakage Inductance causes increased voltage stress on Primary FETs Gate Drive Timing for Primary FETs and secondary Synchronous Rectification FETs is critical

Push Pull Converter – Matrix Transformer

Matrix Transformer Structure:

Core Size 11.8 X 6 X 4 mm

Coupling Coefficients:

Pri-Sec 0.996, Pri-Pri 0.994, Sec-Sec 0.994

Important for the Matrix Transformer cells and SRs to be in close proximity Staggered placement of the Matrix Cells on either side of the PCB facilitates optimum layout

Matrix Transformer Modeling

Standalone With Primary Termination In The Middle 0.5mm 4.5mm Magnetising Inductance 2.07uH 2.07uH Leakage S-P 2.72nH 3.27nH 8.04nH Leakage S-S 7.11nH 7.79nH Leakage P-P 10.94nH 11.61nH Equivalent R 1.38mOhm 1.41mOhm 2.08mOhm Primary R 0.476mOhm Secondary R 0.934mOhm Magnetising Current 1.063A Core Loss 0.375W

Push Pull Converter – Drive Signal Timing

Primary Gate Drive Overlapping

First, overlapping drive is considered to avoid breaking current source path Two primary windings are shorted during the period of overlapping and a current gap occurs Spike across the drain source is caused by the energy stored in leakage inductor

G1 G2

Primary Gate Drive Non-Overlapping

Non-overlapping avoids shorting the primary winding Spike on drain is caused by the current transient Current gap occurs during this period as the two primary FETs are off Non-overlapping gate drive is used. Adjusting dead time optimizes the current gap Device capacitance is sufficient to provide current continuity during commutation

Push Pull Converter – Drive Signal Timing (cont)

Reverse Recovery of Synch Rect. for non-overlapping

Simulation waveform under 100mOhm Load. 100nS primary deadtime, 150nS leading SR

• delay. 60nS SR trailing edge

delay. Note reverse recover current during SR off time The spike due to reverse recover current depends on the parasitic inductance of trace on PCB

Switched Current Converter

Vo 4.7u C1 1m I1 Vref1 Vcc U1 max962 VSn Gnd VSp Qout_p Qout_n VINp VINn D2 IDEAL 10 R3 ARB1 N1 OUT ARB2 N1 OUT Q2 irf6601_1 D3 IDEAL 10 R2 Q1 irf6601_1

Output Capacitance is necessary but smaller Voltage feedback Current supplied to the load is determined by voltage drop on the capacitor Delay of control loop requires a larger capacitance ESR and ESL of Output Capacitance is critical to the step control Gate drive timing stops current to load before short current to ground

Switched Current Converter(cont)

Simulation on dynamic load = 400A/us Simulation condition: Load current is changed from 5A to 95A (blue) Load current slew rate = 400A/us Simulation result: Load voltage is varied from 1.022V to 0.975V (light green)

• The red line Ic is the current waveform before output capacitance
• The light green line is the buck output current waveform

Switched Current Converter(cont)

Simulation on dynamic load = 1000A/us Simulation condition: Load current is changed from 5A to 95A (blue) Load current slew rate = 1000A/us Simulation result: Load voltage is varied from 1.022V to 0.975V (light green)

Switched Current Converter(cont)

Simulation on dynamic load = 2000A/us Simulation condition: Load current is changed from 5A to 95A (blue) Load current slew rate = 2000A/us Simulation result: Load voltage is varied from 1.022V to 0.975V (light green)

• The Slew Rate has no obvious effect on the Output Voltage Deviation

Switched Current Converter(cont)

Modeling The Interconnect:

• All the previous simulations include the parasitics associated with

the a representative system interconnect

• The simulations do not include PCB parasitics and depend on

component simulation accuracy

decoupling capacitors

• utput cap

560u C5 300u R6

Future Processor M

• del

current output

40u R5 L1 100p 300u R3 180u C1

V R M V R M

inter-connection

System Measurements – Actual results

Load changed from 0-50%, 5 phases switching Early results indicate that the 927A/uS can be achieved on rise time Optimisation continues…..

System Power Budget

full load 100A 1V light load 10A 1V item components power losses(W) power losses(W)

• utput choke

EE18 0.281 0.281 Mosfet High side IRF7822 2.463 1.693 Mosfet low side IRF7822 0.127 0.744 sense Resistance 0.01OHM 1 1 Driver IC ISL6605 0.04 0.04 total power losses 3.911 3.758

• utput power

114.754 23.154 Efficiency 96.70% 86.04% RCD 2.5 0.9 transformer Martrix 5.3 5.3 PP Mosfet STP75NF75 1.804 1.804 SYN Mosfet IRF6618 2.81 2.81 Switch current Mosfe IRF6618 2.34 2.34 total power losses 14.754 13.154

power loss 18.665 16.912 load power 100 10 total input power 118.665 26.912 Efficiency 84.27% 37.16% Total

Buck Converter Push Pull and Switch Current

System Power Budget indicates that the overall efficiency ~ 84% ~2-3% Lower than a conventional VRM due to the 3-Stage Topology

System Assembly

6 layer PCB 75mm X 25 mm Assembly height 13.6mm Matrix transformer divided between the top and bottom sides Rectifier FETs close to Matrix Transformer

Summary and Conclusions:

This paper introduces the concepts of switched current conversion as a possible alternative to common industry approaches to Fast transient requirements The converter consists of 3 Stages: Buck Current source, Push Pull converter employing a matrix transformer and the switched current output Simulation results indicate that the topology can meet very fast transient requirements limited only by parasitics and sensing delays Reduces overall system capacitance Transient response could be further enhanced by moving the switched current section to the load application Silicon integration to reduce complexity and component count Advent of flexible Digital control systems to reduce the number of phases, reduce complexity and improve efficiency

Reference Material

1) Edward Herbert, “ Switched-current Power Converter”, 2003 2) Edward Herbert, “ Voltage Control for Switched-current Power Converter”, 3) Edward Herbert, “ Fast Transition Power Control for Processors Using Switched Current and Switched Charge ” 4) Edward Herbert, “ Input Characteristics and Waveforms for Switched-Current Power Converters”