El. devices fabrication (2) [Hastings] Production of silicon - - PowerPoint PPT Presentation

• El. devices fabrication (2)

[Hastings]

Production of silicon

Crystal growth

• starting from electronic

grade Si, obtained by distillation from metallurgical grade Si

• Czochralski method ->

ingots (height ~ 1m) Then:

• cut -> wafers (diam. 6 - 12 inches, 0.150-0.300 mm)
• polishing (mechanical (abrasive) + chemical)

Orientation (100) or (111)

Oxide growth/deposition

• Oxide: SiO2
• easy growth/deposition
• mechanically rugged; readily dissolves in HF
• excellent isolator -> also for MOS
• Growth
• dry: Si + O2 -> SiO2
• wet (not so good (superficial charge) but faster):

Si + 2H2O -> SiO2 + 2H2

• T ~ 1000 oC
• thickness: ~ 2x wrt Si (see LOCOS later)
• Alternatively: deposition (not so good!). E.g.:

SiH4 + 2NO2 -> N2 + 2H2O + SiO2 This is an example of chemical vapor deposition (CVD)

Masks

• If selective processing is needed, a patterned material

can be used as a mask

• the patterning is done via photolithography (see later)
• materials:
• low T: photoresist (soft mask)
• high T: SiO2 o Si3N4 (hard mask), which, of course,

are patterned using photoresist)

Photolithography (1/3)

◼ Photoresist (deposited via

spinning)

• negative (polymerize with UV)
• positive (depolymerize with UV)

Photolithography (2/3)

• Photomasks (reticles)
• normally 5x or 10x (with

stepper -> several exposures (each normally for more than one die)

• or, mask 5x or 10x ->

stepped working plate ->

• nly one exposure, 1x
• very expensive; normally
• btained via direct writing

(electron beam lithography)

• r (photo)reticle

Photolithography (3/3)

• Then, development (with organic solvents) to remove

the non-polymerized photoresist

• Then, after the selective processing (deposition or

etching), the photoresist is removed

• chemically (with solvents), or with
• reactive ion etching (ashing): plasma with oxygen

Oxide removal

• wet etching (with

HF, isotropic)

• dry etching (e.g.

with reactive ion etching, e.g. trichloroethane + Ar; anisotropic -> better control on the widths)

Oxide…

Reactive ion etching

LOCOS; silicon nitride

LOCOS (local

• xidation of

silicon): selective growth

• f a very thick
• xide: normally

for field oxide For Si3N4: CVD 3SiH4+4NH3 -> Si3N4+12H2

Diffusions

Diffusion:

• (pre)deposition
• drive(-in)

T ~ 800-1250 oC Dopants: Si-p: B (B2H6) Si-n: P (POCl3, PH3), As, Sb Poor horizontal control: isotropic process! E.g.: 4POCl3+3O2 -> 2P2O5+6Cl2 P2O5 builds a glass on Si 2P2O5 +5Si -> 4P+5SiO2

Diffusions

Main parameters of the dopant:

• diffusion coeff.
• solid solubility

NB: As, Sb have low diff. coeff.

Diffusions

Ion implantation (actually, it is not a diffusion...)

◼ Ions are launched into the silicon ◼ then, short annealing (T ~ 800 oC)

and, possibly, high T drive

◼ high T not needed (-> photoresist

as mask)

◼ better control; expensive and slow ◼ self-alignment (apart from straggle

and small diffusion)

◼ depth depends on V (and by the

drive, if present)

Deposition of silicon (mono)

To have a single crystal: epitaxy

• (rare: liquid phase (with melted Si ))
• low pressure chemical vapor deposition (LPCVD),

SiH2Cl2 -> Si + 2HCl (with H2 as carrier), or SiCl4+2H2 -> Si + 4HCl or SiH4 -> Si + 2H2 possibly with PH3 o B2H6 o AsH3 to dope

• slow (~1 mm/min) and expensive
• T ~ 1100 oC

Deposition of silicon (polysilicon or “poly”)

For polysilicon: CVD SiH4 -> Si + 2H2 e.g. on SiO2 used

• normally for MOS gates (withstands larger T wrt

Al, and VT is better controlled)

• also for resistors (instead of diffused resistors)
• also as a layer for (short) routing

apparatus similar to the one for epitaxy

Metallizations (1/3)

Al deposition:

• e.g via evaporation (this is an

example of physical vapor deposition, PVD) Some % of Si in Al reduces the contact spiking (o emitter punchthrough) Some % of Cu in Al reduces electromigration Patterning:

• normal
• lift-off (metal on the photoresist)

On the contacts, Al dopes Si:

• ok for Si-p
• for Si-n, Si-n+ is needed (see

Schottky junction)

Metallizations (2/3)

To improve lateral coverage:

• reflow (before Al): high T, with P and B added to SiO2
• refractory barrier metals (Mo, W (tungsten), Ti)

Deposited via sputtering (they melt at too large T for evaporation) Also reduce contact spiking (and electromigration) But have poor conductance -> sandwich with Al -> e.g.. refractory metal, and Al with Cu (Si not needed)

Metallizations (3/3)

Silicides: Si + metal (PtSi, Pd2Si, TiSi…)

• good ohmic contacts, or Shottky diodes; moreover
• low resistivity -> for low resistivity poly (clad poly), e. g.

for high speed MOS Ex of final sandwich: PtSi + refractory + Al with Cu

◼ Also poly layers are often called “metallizations”

And then...

Between poly and metal1: multilevel oxide (MLO), with contact openings between metal1 and Si or Poly Between the various metals: interlevel oxide (ILO), with vias between the various metals Above all: protective overcoat (PO), or overglass, tipically Si3N4 (more resistent than SiO2), with openings for the pads

Assembly and testing

Often made in another facility (easy step -> e.g. in the far east) Process control structures: transistors, R, C, contacts… Test dice: variants of the IC, or to test subcircuits… Test (wafer probing):

• f the wafer
• f each IC (t ~ s; yield ~ 80%)

Assembly…

Then

• cut
• mounting on the leadframe (also for thermal exchange)
• epoxy resin
• soldering (also to have a substrate contact)

Assembly…

Bonding (from bondpads to leadfingers)

• Normally, 1 mil

gold wire and ball bonding

• for Al: wedge

bonding (similar, but the wire is snapped)

• 10 per second!

Assembly…

An IC with many leads...

Assembly…

An IC with many leads...

Assembly…

An IC with many leads...

Packaging

In plastic (normally injected from the bottom)…

Packaging

In plastic (normally injected from the bottom)…

Packaging

... or ceramic…

Finally…

◼ further tests ◼ final packaging (tubes, reels…)