EGSE Presentation, 12.12.2013, A. Fuchs, Siemens CVC Space Program - - PowerPoint PPT Presentation

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ProUST-FE platform EGSE Presentation, 12.12.2013, A. Fuchs, Siemens CVC Space Program and System Engineering PSE Space Business Unit Personal background Fuchs Alfred (substituting Peter Juzl) 6 years at Siemens Space, Product Line

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SLIDE 1

Program and System Engineering PSE Space Business Unit

EGSE Presentation, 12.12.2013,

  • A. Fuchs, Siemens CVC Space

ProUST-FE platform

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Siemens Austria CMT. Space Business Unit 07.01.2014

A.Fuchs

2

Personal background

  • Fuchs Alfred (substituting Peter Juzl)
  • 6 years at Siemens Space, Product Line Manager
  • 20+ years HW and FPGA-design @ Siemens (telecom, medical, …)
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Siemens Austria CMT. Space Business Unit 07.01.2014

A.Fuchs

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Our EGSE portfolio

  • 3 sectors
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Siemens Austria CMT. Space Business Unit 07.01.2014

A.Fuchs

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Interface Requirements

  • RF-SCOE
  • 2 LVDS / SpW
  • Power SCOE
  • 10 SHP
  • 40 Pyros
  • 10 Analog inputs
  • 5 Analog outputs
  • 20 RSA
  • 10 Thermistor sim
  • Instrument EGSE
  • 4 MIL1553
  • 8 SpW
  • 200 SHP/EHP/Valves
  • 40 Pyros
  • 100 Analog inputs
  • 50 Analog outputs
  • 200 RSA
  • 50 Thermistor sim
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Siemens Austria CMT. Space Business Unit 07.01.2014

A.Fuchs

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Other Requirements

  • Power
  • 30V 100A
  • 100V 30A
  • Performance
  • GB/s throughput
  • µs latency
  • Safety
  • OVP, OCP
  • Fault voltage emission/tolerance
  • (Security)
  • (High Availability)
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Siemens Austria CMT. Space Business Unit 07.01.2014

A.Fuchs

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COTS platform example

  • NI PXIe
  • Industry standard, modular I/O
  • Power: NA
  • Performance: 3-12GB/s,
  • Safety: NA
  • Rf: Partly
  • Still proprietary needs
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Siemens Austria CMT. Space Business Unit 07.01.2014

A.Fuchs

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ProUST SLP

  • ProUST – Protection Unit for Satellite Testing
  • 8 reconfigurable power channels for SAS or battery simulator or ...
  • + a bounty of discrete signal I/O
  • > single-rack solution
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Siemens Austria CMT. Space Business Unit 07.01.2014

A.Fuchs

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Make or buy

  • Discrete I/O: Test/DAQ industry
  • MIL-1553: Many suppliers
  • SpW: Several suppliers
  • Other, future I/O: TBD
  • Conclusions:
  • Don‘t fight COTS IT
  • Maximize I/O-performance with PCIe
  • Buy IP-cores
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Siemens Austria CMT. Space Business Unit 07.01.2014

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9

Emphasis

  • Non-functional properties
  • High-density
  • Versatility
  • RT-performance
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Siemens Austria CMT. Space Business Unit 07.01.2014

A.Fuchs

10

Platform for engineers

  • E.g. VW car platform strategy
  • Satellite „platform“
  • „Platform EGSE“
  • Alberto Sangiovalli-Vincentelly (Berkeley)
  • „ a platform is an abstraction layer in the design flow that facilitates a

number of possible refinements into a subsequent abstraction layer (platform) in the design flow. “

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Siemens Austria CMT. Space Business Unit 07.01.2014

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11

Platform FPGAs

  • E.g. „All-programmable“ Xilinx Zynq SOC
  • Logic (LUTs)
  • Memory
  • DSP-ALUs
  • Clock management
  • High-speed serial I/O (PCIe, ETH, other)
  • ADCs
  • Embedded system (ARM)
  • SW-Ecosystem
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Siemens Austria CMT. Space Business Unit 07.01.2014

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12

FPAAs

  • E.g. Anadigm
  • OPAMP-array
  • Filter bank
  • SAR-ADC
  • Typically absorbed into SOCs
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Siemens Austria CMT. Space Business Unit 07.01.2014

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ProUST-“Front-end“

  • Common communication architecture
  • PCIe-over-cable
  • Fiber-optic extension link
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Siemens Austria CMT. Space Business Unit 07.01.2014

A.Fuchs

14

ProUST-FE design

  • MIL-1553, SpaceWire, Cameralink,
  • + „Pyro“ Front-End platform
  • + Fast ADC/QUC
  • Focus: Real-Time HITL simulators
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Siemens Austria CMT. Space Business Unit 07.01.2014

A.Fuchs

15

ProUST-FE design

  • Multiple FPGA approach with Gigabit links
Fully isolated S/C I/F ProUST+ Probe_v3.vsd PJ, 1.8.11

ETHERNET PHY

RGMII ETH-JACK

bFPGA

Pow e rPC 4 4 0 LAN

10/100/1000 Mb MAC controller PLB 4.6 (processor bus) DDR2-256MB 64b@400MHz EMBEDDED SYSTEM – SW DRIVEN

FLASH controller

CFI - FLASH 32MB FW & SW

SYSTEM MONITOR BUS I/F

S/C BUS I/F - ONLY HW XILINX IP SIEMENS IP XILINX IP XILINX IP XILINX IP

MCPM I/F

XILINX IP - AURORA

IDL

port 1 XILINX IP - AURORA

IDL

port 2 XILINX IP - AURORA

SpW

port 1 XILINX IP - AURORA

SpW

port 2 XILINX IP - AURORA PLB 4.6 (processor bus) PLB 4.6 (processor bus)

Pow e r I 2 C

XILINX IP 1V0 2V5 3V3 5V0

U ART RS232 PHY

1V8 XILINX IP 18V -> 36V b o o t l o a d R A M XILINX IP Pow er Managment & Clock distribution

SPI

XILINX IP

SpaceWire port 2 cFPGA I/F

XILINX IP - AURORA

w FPGA

SpaceWire codec

DC-DC

OVP/UVP

SPI – FLASH firmware

1V2 2V5

SpaceWire port 1 Fully isolated domain SPI

XILINX IP

SPI

XILINX IP ISOLATION STAR-Dundee IP Fully isolated S/C I/F Fully isolated S/C I/F Fully isolated S/C I/F

GPI O

S/C I/Fs rear SCOE I/F rear

MIL-1553 PHY SITAL TECH I R Q XILINX IP

XO 125Mhz

POWER IN DEBUG JTAG connectror POWER IN 18V -> 36V POWER IN 18V -> 36V

front panel

3V3

IDL port 2 ` cFPGA I/F

XILINX IP - AURORA

c FPGA

IDL BRIDGE SPI – FLASH firmware

1V2 2V5

IDL port 1 Fully isolated domain status & control SPI

XILINX IP

SPI

XILINX IP ISOLATION SIEMENS IP SIEMENS IP Fully isolated S/C I/F

XO 125 Mhz

JTAG connectror CMD DATA CMD DATA Fully isolated S/C I/F RX TX 3V3

DC-DC

OVP/UVP Fast Analog I/F SIEMENS IP

BUS BRIDGE

SIEMENS IP ISOLATION

Analog I/F

SIEMENS IP 32X Pyro simulator / Thermistor simulator / Thermo-element simulation (configurable load, ADC, Vref)

Xilinx IPs Siemens IP Third

  • co. IP

PCIe 8x

XILINX IP - PCIe

LVDS Crosspoint

MIL-1553 port 1 SITAL TECH IP ISOLATION Isolated S/C I/F 2x ADC 500MSps (ADS5463) PCIe 8x 2x QUC-DAC 400 MHz (AD9957) SFP+ Module 2

MCPM I/F

XILINX IP - AURORA SFP+ Module 1

SpW BRIDGE

SIEMENS IP JTAG connectror c o n f i g l o g i c c o n f i g l o g i c 4X RS485

fFPGA

1V2 RX TX Fully isolated S/C I/F MIL-1553 PHY SITAL TECH MIL-1553 port 2 SITAL TECH IP

GPIO

clocking POWER S/W SYSTEM VOLTAGES

....

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Siemens Austria CMT. Space Business Unit 07.01.2014

A.Fuchs

16

ProUST-FE ES

  • Virtex 5 centered
  • Xilkernel
  • Lwip-stack

RGMII

bFPGA

Pow e rPC 4 4 0 LAN

10/100/1000 Mb MAC controller

PLB 4.6

(processor bus)

EMBEDDED SYSTEM – SW DRIVEN

FLASH controller SYSTEM MONITOR BUS I/F

S/C BUS I/F - ONLY HW

XILINX IP

SIEMENS IP

XILINX IP XILINX IP XILINX IP

MCPM I/F

XILINX IP - AURORA

IDL

port 1

XILINX IP - AURORA

IDL

port 2

XILINX IP - AURORA

SpW

port 1

XILINX IP - AURORA

SpW

port 2

XILINX IP - AURORA

PLB 4.6

(processor bus)

PLB 4.6

(processor bus)

Pow e r I 2 C

XILINX IP

U ART

XILINX IP

b o o t l o a d R A M

XILINX IP

SPI

XILINX IP

GPI O

I R Q

XILINX IP

Fast Analog I/F

SIEMENS IP

BUS BRIDGE

SIEMENS IP

Analog I/F

SIEMENS IP

Xilinx IPs Siemens IP Third

  • co. IP

PCIe 8x

XILINX IP - PCIe

MIL-1553

port 1 SITAL TECH IP

MCPM I/F

XILINX IP - AURORA

MIL-1553

port 2 SITAL TECH IP

GPIO

ProUST+bFPGA.vsd JB, 19.10.2011

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Siemens Austria CMT. Space Business Unit 07.01.2014

A.Fuchs

17

ProUST-FE serial interfaces

  • 2+2 MIL-1553
  • 4 SpaceWire
  • 2 Cameralink
  • 4 RS422
  • Many LVDS / TTL / CMOS IOs
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Siemens Austria CMT. Space Business Unit 07.01.2014

A.Fuchs

18

ProUST-FE „Pyro“

  • 32 Generic, programmable analogue interfaces
  • Individually isolated
  • Suitable for digital, analog, power
  • 150kS/s

ProUST Front-End „Pyro“ Interface

FPGA

DC DC

CLK

Analog Port

Load-FET ODAT OPAMP-2

  • +

OPAMP-1

  • +

1M2 GNDa MDAC +REF isolated + 500m ADC +

  • CS

IDAT Vref

  • D

SPI-IF

FB 100k Vref

  • A

12k4 100k 12k4 56k S1 S2 S3 S4 S5 S6 S7 S8 R1 T1

REF

1M2 348 100k 1k

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SLIDE 19

Siemens Austria CMT. Space Business Unit

FPGA

DC DC

CLK

Analog Port

Load-FET ODAT OPAMP-2

  • +

OPAMP-1

  • +

1M2 GNDa MDAC +REF isolated + 500m ADC +

  • CS

IDAT Vref

  • D

SPI-IF

FB 100k Vref

  • A

12k4 100k 12k4 56k S1 S2 S3 S4 S5 S6 S7 S8 R1 T1

REF

1M2 348 100k 1k

  • 07.01.2014

A.Fuchs

19

ProUST-FE „Pyro“

  • 10+ programmable functions
  • analog voltage input (AN1/2, ..)
  • analog voltage output (AN2)
  • resistor simulation (Thermistors, Pyro &relay)
  • resistor measurement (&relay)
  • current source (FSS, HPC)
  • current measurement
  • …
  • One type, many uses

FPGA

DC DC

CLK

Analog Port

Load-FET ODAT OPAMP-2

  • +

OPAMP-1

  • +

1M2 GNDa MDAC +REF isolated + 500m ADC +

  • CS

IDAT Vref

  • D

SPI-IF

FB 100k Vref

  • A

12k4 100k 12k4 56k S1 S2 S3 S4 S5 S6 S7 S8 R1 T1

REF

1M2 348 100k 1k

  • FPGA

DC DC

CLK

Analog Port

Load-FET ODAT OPAMP-2

  • +

OPAMP-1

  • +

1M2 GNDa MDAC +REF isolated + 500m ADC +

  • CS

IDAT Vref

  • D

SPI-IF

FB 100k Vref

  • A

12k4 100k 12k4 56k S1 S2 S3 S4 S5 S6 S7 S8 R1 T1

REF

1M2 348 100k 1k

  • FPGA

DC DC

CLK

Analog Port

Load-FET ODAT OPAMP-2

  • +

OPAMP-1

  • +

1M2 GNDa MDAC +REF isolated + 500m ADC +

  • CS

IDAT Vref

  • D

SPI-IF

FB 100k Vref

  • A

12k4 100k 12k4 56k S1 S2 S3 S4 S5 S6 S7 S8 R1 T1

REF

1M2 348 100k 1k

  • FPGA

DC DC

CLK

Analog Port

Load-FET ODAT OPAMP-2

  • +

OPAMP-1

  • +

1M2 GNDa MDAC +REF isolated + 500m ADC +

  • CS

IDAT Vref

  • D

SPI-IF

FB 100k Vref

  • A

12k4 100k 12k4 56k S1 S2 S3 S4 S5 S6 S7 S8 R1 T1

REF

1M2 348 100k 1k

  • FPGA

DC DC

CLK

Analog Port

Load-FET ODAT OPAMP-2

  • +

OPAMP-1

  • +

1M2 GNDa MDAC +REF isolated + 500m ADC +

  • CS

IDAT Vref

  • D

SPI-IF

FB 100k Vref

  • A

12k4 100k 12k4 56k S1 S2 S3 S4 S5 S6 S7 S8 R1 T1

REF

1M2 348 100k 1k

  • FPGA

DC DC

CLK

Analog Port

Load-FET ODAT OPAMP-2

  • +

OPAMP-1

  • +

1M2 GNDa MDAC +REF isolated + 500m ADC +

  • CS

IDAT Vref

  • D

SPI-IF

FB 100k Vref

  • A

12k4 100k 12k4 56k S1 S2 S3 S4 S5 S6 S7 S8 R1 T1

REF

1M2 348 100k 1k

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Siemens Austria CMT. Space Business Unit 07.01.2014

A.Fuchs

20

ProUST-FE PQE

  • Complex real-time pulse qualification engine for each interface

ST_ERH_CNT

32 bit

ST_HI_CNT

32 bit

ST_EG_CNT

32 bit

ST_LO_CNT

32 bit

ST_ERL_CNT

32 bit

ST_ERH – MIN

32 bit

ST_ERH – MAX

32 bit

ST_HI – MIN

32 bit

ST_HI – MAX

32 bit

ST_EG – MIN

32 bit

ST_EG – MAX

32 bit

ST_LO – MIN

32 bit

ST_LO – MAX

32 bit

ST_ERL – MIN

32 bit

ST_ERL – MAX

32 bit

STATE counters

(PYRO logic)

STATE counters thresholds

(user defined)

STATE events

(PYRO logic) EV_ERH_MIN EV_ERH_CEN EV_ERH_MAX EV_HI_MIN EV_HI_CEN EV_HI_MAX EV_HI_MIN EV_HI_CEN EV_HI_MAX EV_LO_MIN EV_LO_CEN EV_LO_MAX EV_ERL_MIN EV_ERL_CEN EV_ERL_MAX

GLITCH DETECT ENGINE

(PYRO logic) EV_GLITCH

STATE event counter

(PYRO logic) EV_ERH_MIN_CNT

32bit

EV_ERH_CEN_CNT

32bit

EV_ERH_MAX_CNT

32bit

EV_HI_MIN_CNT

32bit

EV_HI_CEN_CNT

32bit

EV_HI_MAX_CNT

32bit

EV_HI_MIN_CNT

32bit

EV_HI_CEN_CNT

32bit

EV_HI_MAX_CNT

32bit

EV_LO_MIN_CNT

32bit

EV_LO_CEN_CNT

32bit

EV_LO_MAX_CNT

32bit

EV_ERL_MIN_CNT

32bit

EV_ERL_CEN_CNT

32bit

EV_ERL_MAX_CNT

32bit

ST_ERH ST_HI ST_EG ST_LO ST_ERL PYRO STATE

(PYRO logic) AMP_ERR_HI

16 bit

AMP_SIG_HI

16 bit

AMP_SIG_LO

16 bit

AMP_ERR_LO

16 bit

STATE thresholds

(user defined) EV_ERH_CNT_LAST

32bit

EV_HI_CNT_LAST

32bit

EV_EG_CNT_LAST

32bit

EV_LO_CNT_LAST

32bit

EV_ERL_CNT_LAST

32bit

USER (SW) DEFINED REGISTER R/W PYRO INFO REGISTER Read only PYRO LOGIC REGISTER invisible for SW PYRO EVENT

  • SOURCE OF

SW IRQ invisible for SW ProUST+ bFPGA_v1.vsd Peter Jůzl, 28.5.2012

PYRO – register structure

glitch_len

16 bit Bad high pulse Bad low pulse Good pulse

SIG_LO SIG_HI ERR_HI

Bad low pulse

Hi_min Hi_max ERR_LO Pulse start
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Siemens Austria CMT. Space Business Unit 07.01.2014

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21

Software

  • Universal driver architecture
  • function and access is defined via configuration file
  • abstracts used device and port (P / P-FE)
  • abstracts used communication (LAN, PCIe)
  • abstracts access method (SCPI vs register-based)
  • Java applications for simple interactive use
  • CCS integration
  • coming
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The pains of platform design

  • Wishes are
  • Platform is complex
  • Tedious debugging
  • Configuration trade-offs subtle
  • Platform must be optimized
  • PCB layout tricky (Xtalk)
  • Performance tuning across hierarchy
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23

Model-based verification

  • Solar Orbiter OBC testbench
  • 700+ interfaces
  • 16 ms simulation cycle

RTS-PC BRT Proust2 Communication structure Proust-FE1

Int PCIe

RCIM

To RIO

PS PCIe switch Proust3 Proust4 Proust5 Proust6 Proust1 Proust-FE2 Proust-FE3 Proust-FE4 Proust-FE5 Proust-FE6 Proust-FE7 Proust-FE8 Proust-FE9 Proust-FE10 ETH1 ETH0 SimFE LAN switch PCIe switch PCI PCI

PCIe Not in Config. A To RIO/CCS

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24

Mission experiences

  • S5 Precursor „TROPOMI“ Instrument-EGSE
  • Partly needed fallback
  • SOLO PWR SCOE
  • More „Pyro“ current capability requested
  • SOLO SIMFE
  • Display modes added, calibration refined,
  • Don‘t exaggerate density …
  • GFO PWR
  • Event-Trigger-Action feature added
  • MTG DHS
  • MIL functionality enhanced (EI, mRT)
  • Lack of RS422 IFs
  • MTG PDD
  • SpW/LVDS switch added
  • Exomars
  • Bad fit, small EGSEs, CAN-bus, …
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More features

  • UARTs added
  • ISD/OSD added
  • SpW-crossconnect added
  • 4 + 4x3 ports
  • With Equalizer for added cable length
  • Timestamp synchronisation (IRIG) added
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Lessons learned

  • Dedicated HW effort can help SW
  • Discrete I/O times : 0.4µs write, 1.8µs read, low jitter
  • IP-cores may not be the best solution for test equipent
  • Quality ok, but details missing e.g. error insertion
  • PCIe-over-cable is a small market
  • Substitute with FO-net
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27

Surprising benefits

  • Good self-test capability
  • Trivial spare policy,
  • Low risk of obsolescence
  • Easy post-delivery changes
  • Can procure EGSE before S/C settled

„Please one more“ proves attractiveness of versatility

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28

As Marx said …

  • „Das Sein bestimmt das Bewusstsein.“
  • Moore‘s law describes the technical essence of our time
  • Progammable logic, analogue, power
  • The logical conclusion: A soft EGSE
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Platform of platforms

  • Reconfigurable platform ProUST for scalable power protection
  • Reconfigurable platform ProUST-FE for discrete and serial interfaces
  • Reconfigurable platform ProUST-CSAS for bidirectional power
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Green „Chameleon SCOE“

  • Transform EGSE as you like
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Rack-level PCB platform

  • High-density XXL-Power-PCBs
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32

Rack-level PCB platform

  • Rack-level wiring solution incl. power
  • „Sideplane“ thermally optimal
  • Flex-PCB
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33

Roadmap

  • ProUST-FE is a platform within a platform (within a platform EGSE)

Filter 2 DAB (1 of 16) Filter 1 VRB 1 VRB 2 MPB (1 of 16)

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34

Thank you for your Attention!

ISS Cupola Tracy Caldwell