EGSE Presentation, 12.12.2013, A. Fuchs, Siemens CVC Space Program - PowerPoint PPT Presentation

ProUST-FE platform EGSE Presentation, 12.12.2013, A. Fuchs, Siemens CVC Space Program and System Engineering PSE Space Business Unit

Personal background  Fuchs Alfred (substituting Peter Juzl)  6 years at Siemens Space, Product Line Manager  20+ years HW and FPGA-design @ Siemens (telecom, medical, …) 2 07.01.2014 Siemens Austria CMT. Space Business Unit A.Fuchs

Our EGSE portfolio  3 sectors 3 07.01.2014 Siemens Austria CMT. Space Business Unit A.Fuchs

Interface Requirements  RF-SCOE  2 LVDS / SpW  Power SCOE  10 SHP  40 Pyros  10 Analog inputs  5 Analog outputs  20 RSA  10 Thermistor sim  Instrument EGSE  4 MIL1553  8 SpW  200 SHP/EHP/Valves  40 Pyros  100 Analog inputs  50 Analog outputs  200 RSA  50 Thermistor sim 4 07.01.2014 Siemens Austria CMT. Space Business Unit A.Fuchs

Other Requirements  Power  30V 100A  100V 30A  Performance  GB/s throughput  µs latency  Safety  OVP, OCP  Fault voltage emission/tolerance  (Security)  (High Availability) 5 07.01.2014 Siemens Austria CMT. Space Business Unit A.Fuchs

COTS platform example  NI PXIe  Industry standard, modular I/O  Power: NA  Performance: 3-12GB/s,  Safety: NA  Rf: Partly  Still proprietary needs 6 07.01.2014 Siemens Austria CMT. Space Business Unit A.Fuchs

ProUST SLP  ProUST – Protection Unit for Satellite Testing  8 reconfigurable power channels for SAS or battery simulator or ...  + a bounty of discrete signal I/O  -> single-rack solution 7 07.01.2014 Siemens Austria CMT. Space Business Unit A.Fuchs

Make or buy  Discrete I/O: Test/DAQ industry  MIL-1553: Many suppliers  SpW: Several suppliers  Other, future I/O: TBD  Conclusions:  Don‘t fight COTS IT  Maximize I/O-performance with PCIe  Buy IP-cores 8 07.01.2014 Siemens Austria CMT. Space Business Unit A.Fuchs

Emphasis  Non-functional properties  High-density  Versatility  RT-performance 9 07.01.2014 Siemens Austria CMT. Space Business Unit A.Fuchs

Platform for engineers  E.g. VW car platform strategy  Satellite „platform“  „Platform EGSE“  Alberto Sangiovalli-Vincentelly (Berkeley)  „ a platform is an abstraction layer in the design flow that facilitates a number of possible refinements into a subsequent abstraction layer (platform) in the design flow. “ 10 07.01.2014 Siemens Austria CMT. Space Business Unit A.Fuchs

Platform FPGAs  E.g. „All-programmable“ Xilinx Zynq SOC  Logic (LUTs)  Memory  DSP-ALUs  Clock management  High-speed serial I/O (PCIe, ETH, other)  ADCs  Embedded system (ARM)  SW-Ecosystem 11 07.01.2014 Siemens Austria CMT. Space Business Unit A.Fuchs

FPAAs  E.g. Anadigm  OPAMP-array  Filter bank  SAR-ADC  Typically absorbed into SOCs 12 07.01.2014 Siemens Austria CMT. Space Business Unit A.Fuchs

ProUST- “Front-end“  Common communication architecture  PCIe-over-cable  Fiber-optic extension link 13 07.01.2014 Siemens Austria CMT. Space Business Unit A.Fuchs

ProUST-FE design  MIL-1553, SpaceWire, Cameralink,  + „Pyro“ Front-End platform  + Fast ADC/QUC  Focus: Real-Time HITL simulators 14 07.01.2014 Siemens Austria CMT. Space Business Unit A.Fuchs

ProUST-FE design  Multiple FPGA approach with Gigabit links ProUST+ Probe_v3.vsd Xilinx Siemens Third PJ, 1.8.11 IPs IP co. IP Fully isolated Fully isolated Fully isolated Isolated Fully isolated S/C I/F S/C I/F S/C I/F S/C I/F S/C I/F S/C I/Fs rear SCOE I/F TX RX rear 32X Fully isolated SITAL TECH SITAL TECH Pyro simulator / DATA DATA domain CMD CMD Thermistor simulator / 4X Thermo-element RS485 2x 2x c FPGA simulation ADC QUC-DAC MIL-1553 MIL-1553 Fully 500MSps 400 MHz PHY PHY isolated (configurable load, ADC, Vref) XO (ADS5463) (AD9957) S/C I/F 125 Mhz XILINX IP - AURORA SIEMENS IP RX cFPGA I/F IDL BRIDGE TX JTAG connectror SIEMENS IP bFPGA status & control ` 1V2 XILINX IP XILINX IP SITAL TECH IP SITAL TECH IP SIEMENS IP Fast POWER IN SPI SPI DC-DC c o n f i g MIL-1553 MIL-1553 2V5 GPIO Analog 18V -> 36V OVP/UVP l o g i c port 2 port 1 I/F 3V3 SIEMENS IP Analog SFP+ Module 1 XILINX IP - AURORA SIEMENS IP ISOLATION IDL I/F SPI – FLASH port 1 firmware ISOLATION XILINX IP - AURORA XILINX IP - AURORA MCPM I/F IDL SFP+ Module 2 port 2 IDL port 1 BUS XILINX IP - AURORA BRIDGE XILINX IP - AURORA MCPM I/F IDL port 2 SpW Fully port 1 isolated XILINX IP - PCIe PCIe 8x Fully XILINX IP - AURORA S/C I/F ISOLATION PCIe 8x SpW isolated port 2 domain LVDS Crosspoint S/C BUS I/F - ONLY HW JTAG XO w FPGA connectror EMBEDDED SYSTEM – SW DRIVEN 125Mhz XILINX IP SIEMENS IP STAR-Dundee IP ETH-JACK XILINX IP - AURORA cFPGA I/F LAN SpaceWire ETHERNET BUS I/F XILINX IP codec RGMII 10/100/1000 Mb Pow e r PHY MAC controller I 2 C JTAG clocking XILINX IP XILINX IP connectror b o o t l o a d SIEMENS IP I R Q XILINX IP SpW BRIDGE R A M Fully XILINX IP SPI (processor bus) (processor bus) isolated 1V0 1V2 PLB 4.6 PLB 4.6 DDR2-256MB Pow e rPC PLB 4.6 S/C I/F XILINX IP XILINX IP 64b@400MHz 4 4 0 (processor bus) POWER IN DC-DC c o n f i g SPI SPI 2V5 l o g i c 1V2 18V -> 36V OVP/UVP POWER IN 3V3 GPI O Pow er 1V8 Managment 18V -> 36V XILINX IP XILINX IP & CFI - FLASH SPI – FLASH Clock SYSTEM 2V5 FLASH 32MB XILINX IP distribution firmware MONITOR controller U ART FW & SW ISOLATION 3V3 SpaceWire port 1 5V0 SpaceWire port 2 SYSTEM RS232 VOLTAGES PHY front panel fFPGA .... 15 07.01.2014 Siemens Austria CMT. Space Business Unit A.Fuchs POWER S/W DEBUG

Xilinx Siemens Third IPs IP co. IP ProUST-FE ES bFPGA SITAL TECH IP SITAL TECH IP SIEMENS IP Fast MIL-1553 MIL-1553 GPIO Analog  port 1 port 2 Virtex 5 centered I/F SIEMENS IP Analog XILINX IP - AURORA SIEMENS IP IDL I/F  port 1 Xilkernel XILINX IP - AURORA XILINX IP - AURORA IDL MCPM I/F port 2 BUS XILINX IP - AURORA  BRIDGE XILINX IP - AURORA Lwip-stack MCPM I/F SpW port 1 XILINX IP - PCIe XILINX IP - AURORA PCIe 8x SpW port 2 S/C BUS I/F - ONLY HW EMBEDDED SYSTEM – SW DRIVEN SIEMENS IP XILINX IP LAN BUS I/F XILINX IP RGMII 10/100/1000 Mb Pow e r MAC controller I 2 C XILINX IP XILINX IP b o o t l o a d I R Q XILINX IP R A M SPI XILINX IP (processor bus) (processor bus) PLB 4.6 PLB 4.6 Pow e rPC PLB 4.6 4 4 0 (processor bus) GPI O XILINX IP XILINX IP SYSTEM FLASH XILINX IP MONITOR controller U ART ProUST+bFPGA.vsd 16 07.01.2014 Siemens Austria CMT. Space Business Unit A.Fuchs JB, 19.10.2011

ProUST-FE serial interfaces  2+2 MIL-1553  4 SpaceWire  2 Cameralink  4 RS422  Many LVDS / TTL / CMOS IOs 17 07.01.2014 Siemens Austria CMT. Space Business Unit A.Fuchs

ProUST-FE „Pyro“  32 Generic, programmable analogue interfaces  Individually isolated  Suitable for digital, analog, power  150kS/s Analog Port REF 1M2 + + 100k Vref OPAMP-1 1M2 -A - CS S5 S3 DC 100k + 100k 12k4 CLK ADC FPGA IDAT - + ODAT T1 OPAMP-2 SPI-IF Load-FET - Vref -D DC GNDa S8 MDAC - FB +REF S6 500m R1 S4 56k S7 1k isolated 12k4 348 S1 S2 ProUST Front-End „Pyro“ Interface 18 07.01.2014 Siemens Austria CMT. Space Business Unit A.Fuchs