[PPT] - EE382V: EmbeddedSystemDesignandModeling Lecture4 PowerPoint Presentation

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EE382V: EmbeddedSystemDesignandModeling

Lecture4– SystemDesignFlowandMethodology

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Lecture4:Outline

* SpecC systemdesignmethodology * +

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SystemDesign

* Specificationtoarchitecturetoimplementation * Behaviortostructure

/) !0 ) - 00 Specification +constraints

Memory Memory (Processor . Comp. IP Bus . . . CustomHW

Systemarchitecture +estimates

.-

# 1

ProcessorImplementation +results

2 %3+ #

Mem

RF State

Control

ALU

Datapath

PC

Control Pipeline

State

IFFSM

State

IFFSM IPNetlist

RAM IR

Memory

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SystemDesignNeeds

* Designmodels * 2 * !030 * Designlanguages * !4

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Well2defined,rigoroussystem2levelsemantics $ $

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Modelingflow "0

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SystemDesignProcess

Computation Communication A B C D F

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* Abstractionbasedonlevelofdetail(structure/timing) * Systemdesignflow

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Designmethodology ! 4

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' (() =

Top2DownDesignFlow

. ! Logicdesign Productplanning

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Systemdesign

Processordesign

2%3.!

>

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Top2DownDesignFlow

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Logicdesign Productplanning

2%3.!

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Processordesign

Communicationdesign Computationdesign

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Top2DownDesignFlow
2%3.!

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Product planning

Logicdesign

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DesignMethodology

Systemdesign Validationflow ! ) .-

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SpecificationModel

* High2level,abstractmodel * - * 0 0 * B * Noimplicitstructure/architecture * 1000 * Untimed * C56 * * 0C

Specificationmodel

.

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SpecificationModelExample

B1

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1/

1 1

* Simple,typicalspecificationmodel * @07 * 00 $

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SpecificationLevelCommunication

* Message2passing * 0C * 0

1 1

1

1

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CleanSpecificationModelExample

1 1

B1

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1/

* Synthesizablespecificationmodel * @07 * 00 0

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ComputationRefinement

* PEallocation/selection * Behaviorpartitioning * Variablepartitioning * Scheduling

! Computationrefinement

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PEAllocation,BehaviorPartitioning

* - * - 0 * C

1 1

B1

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1/

AdditionallevelofhierarchytomodelPEstructure

PE1 PE2

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ModelafterBehaviorPartitioning

1 1 B1 1/

PE1

/

1/ 1& 1/ 1&

/ &

PE2

Synchronizationtopreserveexecutionorder/semantics

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* #

VariablePartitioning

Sharedmemoryvs.messagepassingimplementation

1 1/ 1& 1 B1 1/ 1/ 1&

PE1

/

/ &

PE2

/ /

* 70

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ModelafterVariablePartitioning

1 1/ 1& 1 B1 1/ 1/ 1&

PE1

/

/ &

PE2

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Keeplocalvariablecopiesinsync * 0C * D70

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TimedComputation

* Executiontimeofbehaviors * 3 * Granularity * 1033 7 E Annotatebehaviors * ! E * !0

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Scheduling

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Serializebehaviorexecutiononcomponents

1 B1 1/ 1/ 1&

PE1

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ComputationModelExample

1 1/ 1& 1 B1 1/ 1/ 1&

PE1

/

/ &

PE2

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ComputationModel

* Componentstructure/architecture * 000 * Behavioral/functionalcomponentview * 107 * !> 0 * Timed *

! Computationmodel

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CommunicationRefinement

* Networkallocation/protocolselection * Channelpartitioning * Protocolstackinsertion * Inlining

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Communicationrefinement

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NetworkAllocation/ChannelPartitioning

1 1& 1 B1 1/ 1/ 1&

PE1

/

/ &

PE2

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1/

* * -0 *

Additionallevelofhierarchytomodelbusstructure

Bus1

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ModelafterChannelPartitioning

1 1& 1 B1 1/ 1/ 1&

PE1

/

PE2

/

1/

/

&

Bus1

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ProtocolInsertion

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&

Bus1

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Network Layers

Bus1

* Insertprotocollayer * 10 * Createnetworklayers * .7 * Replacebuschannel * @0 E

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ModelafterProtocolInsertion

1 B1 1/ 1/ 1&

PE1

/

1 1&

PE2

/

1/

Bus1

IBusSlave IBusMaster

8/<(9

8/(9

BusProtocol

Master Slave

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Inlining

Bus1

IBusSlave IBusMaster

8/<(9

8/(9

BusProtocol

.-! .-#

PE1 PE2 PE2

PE2Bus

IBusSlave

PE2Protocol

.-!

PE1Bus

IBusMaster

PE1Protocol

.-#

PE1

8/<(9

8/(9

*

* 2

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CommunicationModelExample

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8/(9

1 1&

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1/ 1 B1 1/ 1/ 1&

PE1

/

PE2

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CommunicationModel

* Component&busstructure/architecture * 00 * Bus2functionalcomponentmodels * 7 * 10 * Timed *

!

Communicationmodel

.

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ProcessorRefinement

* Cycle2accurateimplementationofPEs * @4042% * !404.! * .042%3.!

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Processorrefinement

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HardwareSynthesis

* Scheduleoperationsintoclockcycles * "E 0 * +!#"0

1 1&

/

1/

PE2

PE2_CLK PE2_CLK PE2_CLK

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SoftwareSynthesis

* Implementbehavioronprocessorinstruction2set * *

1 B1 1/ 1/ 1&

PE1

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InterfaceSynthesis

* Implementcommunicationoncomponents * @4 * !4

PE2Bus

IBusSlave

PE2Protocol

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8/<(9 8/(9

PE1Bus

IBusMaster

PE1Protocol

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DRV

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ImplementationModel

Softwareprocessor Customhardware

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PE2

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PE1

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ImplementationModel

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Implementationmodel

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