EDT for Power Devices Cyril B UTTAY 1 , Chenjiang Y U 2 , ric L ABOUR - PowerPoint PPT Presentation

EDT for Power Devices Cyril B UTTAY 1 , Chenjiang Y U 2 , Éric L ABOURÉ 2 , Vincent B LEY 3 , Céline C OMBETTES 3 1 Laboratoire Ampère, Lyon, France 2 GEEPS, Paris, France 3 LAPLACE, Toulouse, France 22/09/16 1 / 24

Outline Power electronics requirements Review of PCB-based packaging Proposed Embedding Technique Summary and Conclusion 2 / 24

Outline Power electronics requirements Review of PCB-based packaging Proposed Embedding Technique Summary and Conclusion 3 / 24

Layout of a power electronic device Source/Emitter Gate/Base ◮ 1–2 pads on top, one on the bottom ◮ 50-400 µ m thick, 1-100 mm 2 die area ◮ Usually Al on top, Ag on the back ◮ Up to hundreds A/thousands V Drain/Collector 4 / 24

Thermal considerations Source: Lutz, J. et al. Semiconductor Power Devices – Physics, Characteristics, Reliability Springer, 2011 [1] ◮ Junction temperature up to 175 ° C (Si) ◮ Efficient cooling to avoid thermal runaway ◮ Ceramics often used 5 / 24

Thermal considerations Source: Lutz, J. et al. Semiconductor Power Devices – Physics, Characteristics, Reliability Springer, 2011 [1] 7e+07 Ag ◮ Junction temperature up to 175 ° C (Si) Cu Electrical Conductivity (S.m −1 ) 6e+07 ◮ Efficient cooling to avoid thermal runaway 5e+07 Au Al 4e+07 ◮ Ceramics often used 3e+07 2e+07 Ni Sn 1e+07 Pb Ti 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 Thermal Conductivity (W.cm −1 .K −1 ) 5 / 24

Thermal considerations Source: Lutz, J. et al. Semiconductor Power Devices – Physics, Characteristics, Reliability Springer, 2011 [1] 7e+07 Ag Wiedemann−Franz law ◮ Junction temperature up to 175 ° C (Si) Cu Electrical Conductivity (S.m −1 ) 6e+07 ◮ Efficient cooling to avoid thermal runaway 5e+07 Au Al 4e+07 ◮ Ceramics often used 3e+07 2e+07 Ni Sn 1e+07 Pb Ti 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 Thermal Conductivity (W.cm −1 .K −1 ) 5 / 24

Thermal considerations Source: Lutz, J. et al. Semiconductor Power Devices – Physics, Characteristics, Reliability Springer, 2011 [1] 7e+07 Ag Wiedemann−Franz law ◮ Junction temperature up to 175 ° C (Si) Cu Electrical Conductivity (S.m −1 ) 6e+07 ◮ Efficient cooling to avoid thermal runaway 5e+07 Au Al 4e+07 ◮ Ceramics often used 3e+07 2e+07 Ni Sn 1e+07 Pb Ti Al 2 O 3 Si 3 N 4 AlN BeO 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 Thermal Conductivity (W.cm −1 .K −1 ) 5 / 24

Standard power module packaging ◮ Standard Power Modules offer good thermal management ◮ Well suited to higher voltages ( > 1200 V) ◮ Issues: large, not flexible, and high parasitic inductance 6 / 24

Standard power module packaging ◮ Standard Power Modules offer good thermal management ◮ Well suited to higher voltages ( > 1200 V) ◮ Issues: large, not flexible, and high parasitic inductance 6 / 24

Standard power module packaging ◮ Standard Power Modules offer good thermal management ◮ Well suited to higher voltages ( > 1200 V) ◮ Issues: large, not flexible, and high parasitic inductance 6 / 24

Standard power module packaging ◮ Standard Power Modules offer good thermal management ◮ Well suited to higher voltages ( > 1200 V) ◮ Issues: large, not flexible, and high parasitic inductance 6 / 24

Standard power module packaging ◮ Standard Power Modules offer good thermal management ◮ Well suited to higher voltages ( > 1200 V) ◮ Issues: large, not flexible, and high parasitic inductance 6 / 24

Standard power module packaging ◮ Standard Power Modules offer good thermal management ◮ Well suited to higher voltages ( > 1200 V) ◮ Issues: large, not flexible, and high parasitic inductance 6 / 24

Effect of the Packaging on Electrical Performance R Gh T h V DRh V In I Out R Gl T l V DRl ◮ Stray inductances cause ringing and switching losses ◮ Caused by packaging ◮ Issue highlighted by fast WBG semiconductors 7 / 24

Effect of the Packaging on Electrical Performance L DC1 L DC2 C GDh R Gh L Gh C DSh T h C GSh V DRh C CM1 L Cdc L Sh V In C CM2 C DC C Out L Dl I Out C GDl R Gl L Gl C DSl T l C GSl V DRl L Sl L DC3 L DC4 ◮ Stray inductances cause ringing and switching losses ◮ Caused by packaging ◮ Issue highlighted by fast WBG semiconductors 7 / 24

Active devices – Evolution of the Packaged Devices 5 5 0 3 N 2 source: wikimedia commons for all packages except the Directfet, courtesy International Rectifier, and the WL-CSP , c.f. below Volume (mm 3 ) Package type molding compound% silicon % leadframe % interconnect % DPAK 90 75 4 20 1 SO8 (wire) 28 83 6 10 1 SO8 (clip) 28 70 6 20 2 MOSFET BGA 20 0 40 50 10 WL-CSP 20 0 82 0 18 source for table and bottom figure: “Trends of power semiconductor wafer level packaging”, Yong LIU [2] ◮ Gradual disappearance of the FLP (First Level Packaging) ◮ All fabrication steps made directly on wafer: Wafer Level-Chip Scale Packaging 8 / 24

Outline Power electronics requirements Review of PCB-based packaging Proposed Embedding Technique Summary and Conclusion 9 / 24

Literature Review – Converter on a flex substrate ◮ Flex PCB instead of wirebonds ◮ backside attached to a DBC ◮ advantages: ◮ low profile, low inductance ◮ higher interconnect density ◮ Implementations: ◮ GE [3] ◮ CPES [4] T. Stockmeier et al. “SKiN: Double side sintering technology for new ◮ TU Berlin/Fraunhofer Inst. [5] packages”, ISPD 2011 ◮ Semikron [6]. . . images from ECPE Seminar “Power PCBs and Busbars”, Delft, 2008, Papers: [7, 8] 10 / 24

Literature Review – “PCB-like” 3D structures P . Ning et al. “A novel high-temperature planar package for SiC multichip phase-leg power module”, IEEE Trans on PE vol 25, 2010, 25, 2059 Silver-sintered interconnects and Epoxy/Kapton insulation [9] 11 / 24

Literature Review – “PCB-like” 3D structures P . Ning et al. “A novel high-temperature planar package for SiC multichip phase-leg power Weidner, et al. “Planar Interconnect Technology for Power Module System Integration”, CIPS module”, IEEE Trans on PE vol 25, 2010, 25, 2059 2012 Silver-sintered interconnects and SiPLIT Copper electroplating, Epoxy/Kapton insulation [9] laminated isolation laser-structured in-situ [10] 11 / 24

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Literature Review – Die embedding in PCB Low-inductance packaging for SiC [11] ◮ Half bridge module ◮ 0.8 nH loop inductance ◮ Embedding die using stud bumps E. Hoene, “Ultra Low Inductance Package for SiC” ECPE workshop on power boards, 2012 ◮ Power module development through german project Hi-LEVEL [12] ◮ 10 kW and 50 kW demonstrators ◮ Thick copper or DBC for thermal management ❤tt♣✿✴✴✇✇✇✳♣❝❞❛♥❞❢✳❝♦♠✴♣❝❞❡s✐❣♥✴✐♥❞❡①✳♣❤♣✴❡❞✐t♦r✐❛❧✴♠❡♥✉✲❢❡❛t✉r❡s✴✾✷✺✼✲❝♦♠♣♦♥❡♥t✲♣❛❝❦❛❣✐♥❣✲✶✹✵✺ 12 / 24

Outline Power electronics requirements Review of PCB-based packaging Proposed Embedding Technique Summary and Conclusion 13 / 24

Overview of the process ◮ Start with a DBC substrate ◮ Die attach (silver sintering) ◮ PCB stacking ◮ PCB lamination ◮ Topside copper etching ◮ Laser ablation ◮ Copper electroplating 14 / 24

Overview of the process ◮ Start with a DBC substrate ◮ Die attach (silver sintering) ◮ PCB stacking ◮ PCB lamination ◮ Topside copper etching ◮ Laser ablation ◮ Copper electroplating 14 / 24

Overview of the process ◮ Start with a DBC substrate ◮ Die attach (silver sintering) ◮ PCB stacking ◮ PCB lamination ◮ Topside copper etching ◮ Laser ablation ◮ Copper electroplating 14 / 24

Overview of the process ◮ Start with a DBC substrate ◮ Die attach (silver sintering) ◮ PCB stacking ◮ PCB lamination ◮ Topside copper etching ◮ Laser ablation ◮ Copper electroplating 14 / 24

Overview of the process ◮ Start with a DBC substrate ◮ Die attach (silver sintering) ◮ PCB stacking ◮ PCB lamination ◮ Topside copper etching ◮ Laser ablation ◮ Copper electroplating 14 / 24

Overview of the process ◮ Start with a DBC substrate ◮ Die attach (silver sintering) ◮ PCB stacking ◮ PCB lamination ◮ Topside copper etching ◮ Laser ablation ◮ Copper electroplating 14 / 24

Overview of the process ◮ Start with a DBC substrate ◮ Die attach (silver sintering) ◮ PCB stacking ◮ PCB lamination ◮ Topside copper etching ◮ Laser ablation ◮ Copper electroplating 14 / 24