EDT for Power Devices Cyril B UTTAY 1 , Chenjiang Y U 2 , ric L ABOUR - - PowerPoint PPT Presentation

EDT for Power Devices

Cyril BUTTAY1, Chenjiang YU2, Éric LABOURÉ2, Vincent BLEY3, Céline COMBETTES3

1Laboratoire Ampère, Lyon, France 2GEEPS, Paris, France 3 LAPLACE, Toulouse, France

22/09/16

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Outline Power electronics requirements Review of PCB-based packaging Proposed Embedding Technique Summary and Conclusion

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Outline Power electronics requirements Review of PCB-based packaging Proposed Embedding Technique Summary and Conclusion

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Layout of a power electronic device

Source/Emitter Gate/Base Drain/Collector

◮ 1–2 pads on top, one on the bottom ◮ 50-400 µm thick, 1-100 mm2 die area ◮ Usually Al on top, Ag on the back ◮ Up to hundreds A/thousands V

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Thermal considerations

Source: Lutz, J. et al. Semiconductor Power Devices – Physics, Characteristics, Reliability Springer, 2011 [1]

◮ Junction temperature up to 175 °

C (Si)

◮ Efficient cooling to avoid thermal runaway ◮ Ceramics often used

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Thermal considerations

Source: Lutz, J. et al. Semiconductor Power Devices – Physics, Characteristics, Reliability Springer, 2011 [1]

1e+07 2e+07 3e+07 4e+07 5e+07 6e+07 7e+07 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 Electrical Conductivity (S.m−1) Thermal Conductivity (W.cm−1.K−1)

Cu Al Ag Au Ni Sn Pb Ti

◮ Junction temperature up to 175 °

C (Si)

◮ Efficient cooling to avoid thermal runaway ◮ Ceramics often used

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Thermal considerations

Source: Lutz, J. et al. Semiconductor Power Devices – Physics, Characteristics, Reliability Springer, 2011 [1]

1e+07 2e+07 3e+07 4e+07 5e+07 6e+07 7e+07 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 Electrical Conductivity (S.m−1) Thermal Conductivity (W.cm−1.K−1)

Cu Al Ag Au Ni Sn Pb Ti

Wiedemann−Franz law

◮ Junction temperature up to 175 °

C (Si)

◮ Efficient cooling to avoid thermal runaway ◮ Ceramics often used

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Thermal considerations

Source: Lutz, J. et al. Semiconductor Power Devices – Physics, Characteristics, Reliability Springer, 2011 [1]

1e+07 2e+07 3e+07 4e+07 5e+07 6e+07 7e+07 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 Electrical Conductivity (S.m−1) Thermal Conductivity (W.cm−1.K−1)

Cu Al Ag Au Ni Sn Pb Ti

Wiedemann−Franz law

Al2O3 AlN Si3N4 BeO

◮ Junction temperature up to 175 °

C (Si)

◮ Efficient cooling to avoid thermal runaway ◮ Ceramics often used

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Standard power module packaging

◮ Standard Power Modules offer good thermal management ◮ Well suited to higher voltages (>1200 V) ◮ Issues: large, not flexible, and high parasitic inductance

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Standard power module packaging

◮ Standard Power Modules offer good thermal management ◮ Well suited to higher voltages (>1200 V) ◮ Issues: large, not flexible, and high parasitic inductance

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Standard power module packaging

◮ Standard Power Modules offer good thermal management ◮ Well suited to higher voltages (>1200 V) ◮ Issues: large, not flexible, and high parasitic inductance

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Standard power module packaging

◮ Standard Power Modules offer good thermal management ◮ Well suited to higher voltages (>1200 V) ◮ Issues: large, not flexible, and high parasitic inductance

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Standard power module packaging

◮ Standard Power Modules offer good thermal management ◮ Well suited to higher voltages (>1200 V) ◮ Issues: large, not flexible, and high parasitic inductance

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Standard power module packaging

◮ Standard Power Modules offer good thermal management ◮ Well suited to higher voltages (>1200 V) ◮ Issues: large, not flexible, and high parasitic inductance

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Effect of the Packaging on Electrical Performance

RGl Tl VDRl RGh Th VDRh VIn IOut

◮ Stray inductances cause ringing and switching losses ◮ Caused by packaging ◮ Issue highlighted by fast WBG semiconductors

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Effect of the Packaging on Electrical Performance

RGl Tl VDRl RGh Th VDRh VIn IOut CGDl CGSl CDSl CGDh CGSh CDSh LDC1 LDC3 CDC LCdc LDC2 LDC4 LDl LGl LGh LSl LSh COut CCM1 CCM2

◮ Stray inductances cause ringing and switching losses ◮ Caused by packaging ◮ Issue highlighted by fast WBG semiconductors

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Active devices – Evolution of the Packaged Devices

2 N 3 5 5 source: wikimedia commons for all packages except the Directfet, courtesy International Rectifier, and the WL-CSP , c.f. below

Package type Volume (mm3) molding compound% silicon % leadframe % interconnect % DPAK 90 75 4 20 1 SO8 (wire) 28 83 6 10 1 SO8 (clip) 28 70 6 20 2 MOSFET BGA 20 40 50 10 WL-CSP 20 82 18

source for table and bottom figure: “Trends of power semiconductor wafer level packaging”, Yong LIU [2]

◮ Gradual disappearance of the FLP

(First Level Packaging)

◮ All fabrication steps made directly

• n wafer: Wafer Level-Chip Scale

Packaging

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Outline Power electronics requirements Review of PCB-based packaging Proposed Embedding Technique Summary and Conclusion

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Literature Review – Converter on a flex substrate

◮ Flex PCB instead of wirebonds ◮ backside attached to a DBC ◮ advantages:

◮ low profile, low inductance ◮ higher interconnect density

◮ Implementations:

◮ GE [3] ◮ CPES [4] ◮ TU Berlin/Fraunhofer Inst. [5] ◮ Semikron [6]. . .

• T. Stockmeier et al. “SKiN: Double side sintering technology for new

packages”, ISPD 2011 images from ECPE Seminar “Power PCBs and Busbars”, Delft, 2008, Papers: [7, 8]

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Literature Review – “PCB-like” 3D structures

P . Ning et al. “A novel high-temperature planar package for SiC multichip phase-leg power module”, IEEE Trans on PE vol 25, 2010, 25, 2059

Silver-sintered interconnects and Epoxy/Kapton insulation [9]

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Literature Review – “PCB-like” 3D structures

P . Ning et al. “A novel high-temperature planar package for SiC multichip phase-leg power module”, IEEE Trans on PE vol 25, 2010, 25, 2059

Silver-sintered interconnects and Epoxy/Kapton insulation [9]

Weidner, et al. “Planar Interconnect Technology for Power Module System Integration”, CIPS 2012

SiPLIT Copper electroplating, laminated isolation laser-structured in-situ [10]

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Literature Review – Die embedding in PCB

Low-inductance packaging for SiC [11]

◮ Half bridge module ◮ 0.8 nH loop inductance ◮ Embedding die using stud bumps

• E. Hoene, “Ultra Low Inductance Package for SiC” ECPE workshop on power

boards, 2012

❤tt♣✿✴✴✇✇✇✳♣❝❞❛♥❞❢✳❝♦♠✴♣❝❞❡s✐❣♥✴✐♥❞❡①✳♣❤♣✴❡❞✐t♦r✐❛❧✴♠❡♥✉✲❢❡❛t✉r❡s✴✾✷✺✼✲❝♦♠♣♦♥❡♥t✲♣❛❝❦❛❣✐♥❣✲✶✹✵✺

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Literature Review – Die embedding in PCB

Low-inductance packaging for SiC [11]

◮ Half bridge module ◮ 0.8 nH loop inductance ◮ Embedding die using stud bumps

• E. Hoene, “Ultra Low Inductance Package for SiC” ECPE workshop on power

boards, 2012

◮ Power module development through german

project Hi-LEVEL [12]

◮ 10 kW and 50 kW demonstrators ◮ Thick copper or DBC for thermal management

❤tt♣✿✴✴✇✇✇✳♣❝❞❛♥❞❢✳❝♦♠✴♣❝❞❡s✐❣♥✴✐♥❞❡①✳♣❤♣✴❡❞✐t♦r✐❛❧✴♠❡♥✉✲❢❡❛t✉r❡s✴✾✷✺✼✲❝♦♠♣♦♥❡♥t✲♣❛❝❦❛❣✐♥❣✲✶✹✵✺

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Outline Power electronics requirements Review of PCB-based packaging Proposed Embedding Technique Summary and Conclusion

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Overview of the process

◮ Start with a DBC substrate ◮ Die attach (silver sintering) ◮ PCB stacking ◮ PCB lamination ◮ Topside copper etching ◮ Laser ablation ◮ Copper electroplating

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Overview of the process

◮ Start with a DBC substrate ◮ Die attach (silver sintering) ◮ PCB stacking ◮ PCB lamination ◮ Topside copper etching ◮ Laser ablation ◮ Copper electroplating

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Overview of the process

◮ Start with a DBC substrate ◮ Die attach (silver sintering) ◮ PCB stacking ◮ PCB lamination ◮ Topside copper etching ◮ Laser ablation ◮ Copper electroplating

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Overview of the process

◮ Start with a DBC substrate ◮ Die attach (silver sintering) ◮ PCB stacking ◮ PCB lamination ◮ Topside copper etching ◮ Laser ablation ◮ Copper electroplating

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Overview of the process

◮ Start with a DBC substrate ◮ Die attach (silver sintering) ◮ PCB stacking ◮ PCB lamination ◮ Topside copper etching ◮ Laser ablation ◮ Copper electroplating

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Overview of the process

◮ Start with a DBC substrate ◮ Die attach (silver sintering) ◮ PCB stacking ◮ PCB lamination ◮ Topside copper etching ◮ Laser ablation ◮ Copper electroplating

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Overview of the process

◮ Start with a DBC substrate ◮ Die attach (silver sintering) ◮ PCB stacking ◮ PCB lamination ◮ Topside copper etching ◮ Laser ablation ◮ Copper electroplating

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Overview of the process – significant points

◮ Backside die attach with silver sintering:

◮ The die does not move during assembly ◮ Accurate positioning

◮ Ablation using a CO2 laser

◮ Very good selectivity (metal layers insensitive to laser light) ◮ Use of the copper layer as an alignment mask

◮ Prototype-scale equipment used

◮ Can manufacture prototypes from 4x4 cm2 up to 21x28 cm2 ◮ Affordable, useful for process development. 15 / 24

Overview of the process – significant points

◮ Backside die attach with silver sintering:

◮ The die does not move during assembly ◮ Accurate positioning

◮ Ablation using a CO2 laser

◮ Very good selectivity (metal layers insensitive to laser light) ◮ Use of the copper layer as an alignment mask

◮ Prototype-scale equipment used

◮ Can manufacture prototypes from 4x4 cm2 up to 21x28 cm2 ◮ Affordable, useful for process development. 15 / 24

Overview of the process – significant points

◮ Backside die attach with silver sintering:

◮ The die does not move during assembly ◮ Accurate positioning

◮ Ablation using a CO2 laser

◮ Very good selectivity (metal layers insensitive to laser light) ◮ Use of the copper layer as an alignment mask

◮ Prototype-scale equipment used

◮ Can manufacture prototypes from 4x4 cm2 up to 21x28 cm2 ◮ Affordable, useful for process development. 15 / 24

Effect of die finish

Preparation Die Mask PVD Two die finishes evaluated

◮ Standard Al topside ◮ Ti/Cu PVD with a shadow

mask

0.0 0.5 1.0 1.5 2.0 2.5 3.0 Displacement [mm] −5 5 10 15 20 25 30 Height [µm]

initial 10 mins electroplating on Cu 10 mins electroplating

➜ Need for a suitable topside finish for electroplating : copper

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Effect of die finish

Preparation Die Mask PVD Two die finishes evaluated

◮ Standard Al topside ◮ Ti/Cu PVD with a shadow

mask

0.0 0.5 1.0 1.5 2.0 2.5 3.0 Displacement [mm] −5 5 10 15 20 25 30 Height [µm]

initial 10 mins electroplating on Cu 10 mins electroplating

➜ Need for a suitable topside finish for electroplating : copper

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Cross section

◮ Vertical walls in epoxy layers ◮ Good self-alignment ◮ No degradation of die topside

metal due to CO2 laser

◮ Die contact not yet perfect

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Effect of contact area

Die Topside copper Wells R

Rtop Rwall Rcont Rdie RAl Raccess Vin

◮ Thick topside copper foil (35 µm) ◮ Thin electroplated copper (10 µm) ◮ Many wells:

◮ More copper section on walls

◮ Large well(s):

◮ Thicker die contact metallization ◮ reduction of topside copper section 18 / 24

Effect of contact area

Die Topside copper Wells R

Rtop Rwall Rcont Rdie RAl Raccess Vin

◮ Thick topside copper foil (35 µm) ◮ Thin electroplated copper (10 µm) ◮ Many wells:

◮ More copper section on walls

◮ Large well(s):

◮ Thicker die contact metallization ◮ reduction of topside copper section 18 / 24

Effect of contact area

Die Topside copper Wells R

Rtop Rwall Rcont Rdie RAl Raccess Vin

◮ Thick topside copper foil (35 µm) ◮ Thin electroplated copper (10 µm) ◮ Many wells:

◮ More copper section on walls

◮ Large well(s):

◮ Thicker die contact metallization ◮ reduction of topside copper section 18 / 24

Effect of contact area

Die Topside copper Wells R

Rtop Rwall Rcont Rdie RAl Raccess Vin

◮ Thick topside copper foil (35 µm) ◮ Thin electroplated copper (10 µm) ◮ Many wells:

◮ More copper section on walls

◮ Large well(s):

◮ Thicker die contact metallization ◮ reduction of topside copper section 18 / 24

Electrical Characterization

−1200 −1000 −800 −600 −400 −200 Reverse voltage [V] 10−8 10−7 10−6 10−5 Reverse current [A]

0.8 1.0 1.2 1.4 1.6 1.8 2.0 Voltage [V] 20 40 60 80 100 Current [A]

• 13. 60mΩ
• 6. 62mΩ
• 5. 43mΩ
• 4. 83mΩ

1 mm² contact 4 mm² contact 9 mm² contact 16 mm² contact

◮ Tests performed in air, without additional passivation ◮ Most important parameter for contact resistance:

distribution of contacts over die area

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Electrical Characterization

−1200 −1000 −800 −600 −400 −200 Reverse voltage [V] 10−8 10−7 10−6 10−5 Reverse current [A]

0.8 1.0 1.2 1.4 1.6 1.8 2.0 Voltage [V] 20 40 60 80 100 Current [A]

• 13. 60mΩ
• 6. 62mΩ
• 5. 43mΩ
• 4. 83mΩ

1 mm² contact 4 mm² contact 9 mm² contact 16 mm² contact

◮ Tests performed in air, without additional passivation ◮ Most important parameter for contact resistance:

distribution of contacts over die area

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Outline Power electronics requirements Review of PCB-based packaging Proposed Embedding Technique Summary and Conclusion

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Summary and Conclusion

◮ Embedding of power devices

◮ Scalable technology ◮ Allows for more compact systems ◮ Custom design ◮ Attractive for fast, wide-bandgap

devices

◮ Simple process

◮ Lab-scale process presented ◮ Good compatibility with CO2 laser ◮ Main issue: die topside finish

◮ Developments to come:

◮ Half-bridge with gate drivers ◮ Multi-layer design ◮ Embedding of passive components ◮ Work on thermal design 21 / 24

Summary and Conclusion

◮ Embedding of power devices

◮ Scalable technology ◮ Allows for more compact systems ◮ Custom design ◮ Attractive for fast, wide-bandgap

devices

◮ Simple process

◮ Lab-scale process presented ◮ Good compatibility with CO2 laser ◮ Main issue: die topside finish

◮ Developments to come:

◮ Half-bridge with gate drivers ◮ Multi-layer design ◮ Embedding of passive components ◮ Work on thermal design 21 / 24

Summary and Conclusion

◮ Embedding of power devices

◮ Scalable technology ◮ Allows for more compact systems ◮ Custom design ◮ Attractive for fast, wide-bandgap

devices

◮ Simple process

◮ Lab-scale process presented ◮ Good compatibility with CO2 laser ◮ Main issue: die topside finish

◮ Developments to come:

◮ Half-bridge with gate drivers ◮ Multi-layer design ◮ Embedding of passive components ◮ Work on thermal design 21 / 24

Summary and Conclusion

◮ Embedding of power devices

◮ Scalable technology ◮ Allows for more compact systems ◮ Custom design ◮ Attractive for fast, wide-bandgap

devices

◮ Simple process

◮ Lab-scale process presented ◮ Good compatibility with CO2 laser ◮ Main issue: die topside finish

◮ Developments to come:

◮ Half-bridge with gate drivers ◮ Multi-layer design ◮ Embedding of passive components ◮ Work on thermal design 21 / 24

Summary and Conclusion

◮ Embedding of power devices

◮ Scalable technology ◮ Allows for more compact systems ◮ Custom design ◮ Attractive for fast, wide-bandgap

devices

◮ Simple process

◮ Lab-scale process presented ◮ Good compatibility with CO2 laser ◮ Main issue: die topside finish

◮ Developments to come:

◮ Half-bridge with gate drivers ◮ Multi-layer design ◮ Embedding of passive components ◮ Work on thermal design 21 / 24

Summary and Conclusion

◮ Embedding of power devices

◮ Scalable technology ◮ Allows for more compact systems ◮ Custom design ◮ Attractive for fast, wide-bandgap

devices

◮ Simple process

◮ Lab-scale process presented ◮ Good compatibility with CO2 laser ◮ Main issue: die topside finish

◮ Developments to come:

◮ Half-bridge with gate drivers ◮ Multi-layer design ◮ Embedding of passive components ◮ Work on thermal design 21 / 24

Summary and Conclusion

◮ Embedding of power devices

◮ Scalable technology ◮ Allows for more compact systems ◮ Custom design ◮ Attractive for fast, wide-bandgap

devices

◮ Simple process

◮ Lab-scale process presented ◮ Good compatibility with CO2 laser ◮ Main issue: die topside finish

◮ Developments to come:

◮ Half-bridge with gate drivers ◮ Multi-layer design ◮ Embedding of passive components ◮ Work on thermal design 21 / 24

Bibliography I

• J. Lutz, H. Schlangenotto, U. Scheuermann, and R. De Donker, Semiconductor

Power Devices – Physics, Characteristics, Reliability. Springer, 2011.

• Y. Liu, “Trends of power semiconductor wafer level packaging,” Microelectronics

Reliability, vol. 50, pp. 514–521, 2010.

• B. Ozmat, C. S. Korman, and R. Fillion, “An Advanced Approach to Power

Module Packaging,” in Integrated Power Packaging, 2000. IWIPP 2000. International Workshop on, (Waltham, MA, USA), pp. 8–11, July 2000.

• Y. Xiao, H. Shah, R. Natarajan, E. J. Rymaszewski, T. Chow, and R. Gutmann,

“Integrated flip-chip flex-circuit packaging for power electronics applications,” Power Electronics, IEEE Transactions on, vol. 19, pp. 515–522, Mar. 2004.

• S. Dieckerhoff, T. Kirfe, T. Wernicke, C. Kallmayer, A. Ostmann, E. Jung,
• B. Wunderle, and H. Reichl, “Electric Characteristics of Planar Interconnect

Technologies for Power MOSFETs,” in Power Electronics Specialists Conference,

• 2007. PESC 2007. IEEE, pp. 1036–1042, June 2007.
• T. Stockmeier, P

. Beckedahl, C. Gobl, and T. Malzer, “SKiN: Double side sintering technology for new packages,” in Power Semiconductor Devices and ICs (ISPSD), 2011 IEEE 23rd International Symposium on, pp. 324–327, May 2011.

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Bibliography II

• E. de Jong, B. Ferreira, and P

. Bauer, “Toward the Next Level of PCB Usage in Power Electronic Converters,” Power Electronics, IEEE Transactions on, vol. 23,

• no. 6, pp. 3151–3163, 2008.
• B. Ferreira, “PCB Integration Technology Overview,” in ECPE Seminar “Power

PCBs and Busbars”, (Delft), 2008. P . Ning, T. G. Lei, F . Wang, G.-Q. Lu, K. D. Ngo, and K. Rajashekara, “A novel high-temperature planar package for SiC multichip phase-leg power module,” Power Electronics, IEEE Transactions on, vol. 25, no. 8, pp. 2059–2067, 2010.

• K. Weidner, M. Kaspar, and N. Seliger, “Planar Interconnect Technology for

Power Module System Integration,” in Integrated Power Electronics Systems (CIPS), 2012 7th International Conference on, pp. 1–5, IEEE, 2012.

• E. Hoene, “Ultra Low Inductance Package for SiC,” in ECPE workshop on power

boards, ECPE, 2012.

• A. Ostmann, L. Boettcher, D. Manessis, S. Karaszkiewicz, and K.-D. Lang,

“Power modules with embedded components,” in Microelectronics Packaging Conference (EMPC) , 2013 European, pp. 1–4, Sept. 2013.

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Thank you for your attention

cyril.buttay@insa-lyon.fr This work was funded by the French National Research Agency (ANR) under the grant name ETHAER. The authors thank Mr Gilles BRILLAT for his technical help.

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