ECOC2010 Invited Paper DA and AD Converters in SiGe Technology: - - PowerPoint PPT Presentation

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ECOC2010 Invited Paper DA and AD Converters in SiGe Technology: - - PowerPoint PPT Presentation

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ECOC2010 Invited Paper DA and AD Converters in SiGe Technology: Speed and Resolution for Ultra High Data Rate Applications Tobias Ellermeyer, Rolf Schmid, Anna Bielik, Jrg Rupeter and Michael Mller MICRAM Microelectronic GmbH, Bochum,

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SLIDE 1

SEPTEMBER 19-23, 2010 – TORINO, ITALY

  • T. Ellermeyer et al.: DA and AD Converters in SiGe Technology.

ECOC2010 Invited Paper DA and AD Converters in SiGe Technology: Speed and Resolution for Ultra High Data Rate Applications

Tobias Ellermeyer, Rolf Schmid, Anna Bielik, Jörg Rupeter and Michael Möller MICRAM Microelectronic GmbH, Bochum, Germany www.micram.com

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SLIDE 2

SEPTEMBER 19-23, 2010 – TORINO, ITALY

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  • T. Ellermeyer et al.: DA and AD Converters in SiGe Technology.

Introduction

TX

DA converter needed for:

  • Pre-Emphasis
  • Higher Level QAM / DQPSK
  • OFDM
  • Multi-Format / Adaptive Transmitters

RX

AD converter needed for:

  • Equalization in binary transmission
  • Higher Level QAM / DQPSK
  • OFDM
  • Multi-Format / Adaptive Receivers

DAC DAC DSP

90°

ADC

TIA

ADC

TIA

DSP

Simple example w/o PolMux Simple example w/o PolMux / direct detection

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SEPTEMBER 19-23, 2010 – TORINO, ITALY

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  • T. Ellermeyer et al.: DA and AD Converters in SiGe Technology.

State-of-the-Art converters

12 GSa/s 32 GSa/s 34 GSa/s 43 GSa/s 20 GSa/s 50 GSa/s

D A C C A D

1.0 Vfs 8 bit 5.7 bit 17 GHz 8 bit 1.0 Vpp tr > 30 ps 6 bit 8 bit tr > 24 ps CMOS SiGe HBT/BiCMOS III/V HBT 0.8 Vpp tr n/a 1.0 Vpp 6 bit tr = 30ps 0.3 Vpp 6 bit tr = 12 ps 1.6 Vpp 6 bit tr n/a n/a 20 GSa/s 10 GSa/s 24 GSa/s 30 GSa/s 35 GSa/s 56 GSa/s 40 GSa/s 1.0 Vfs 10 GHz 2.3 bit 3 bit 1.0 Vfs 10 GHz 6 bit 15 GHz 18 GHz 5 bit 3.5 bit 4 bit 22 GHz 0.28 Vfs 4 bit 3.2 bit 8 GHz 0.24 Vfs 4 bit 3.2 bit 0.5 Vfs 6 bit 3.9 bit 1.2 Vfs

  • Phys. resolution

Rise/fall time (20/80) Full scale swing

  • Phys. resolution

ENOB f(ENOB) GHz Full scale swing

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SEPTEMBER 19-23, 2010 – TORINO, ITALY

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  • T. Ellermeyer et al.: DA and AD Converters in SiGe Technology.

Technology Choice (ADC)

Bottleneck CMOS SiGe TIA / AGC

  • External IC (or add. bits instead

AGC)

  • Integrated on ADC

First T/H Stage - Bandwidth

  • Driving of next stages
  • Clock jitter
  • Resolution / Droop
  • Clock jitter

AD conversion - Slow ADC cores

  • Synchronization / calibration
  • Signal / Clock distribution
  • Fast ADC cores
  • No complex logic

100GbE: 28/56 GSa/s; 17 GHz BW 400GbE: 56-224 GSa/s; 28-112 GHz BW

T/H T/H T/H T/H T/H

T/H T/H T/H T/H

0°

AD C AD C AD C AD C

90° 180° 270°

CLK/4 CLK/n CLK fS /4 fS /n

17 GHz (100G) >30 GHz (400G) >30 GHz (400G) 17 GHz (100G) >4 GHz (100G) >7.5 GHz (400G) 17 GHz (100G) >30 GHz (400G)

ADC TIA/AGC

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SLIDE 5

SEPTEMBER 19-23, 2010 – TORINO, ITALY

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  • T. Ellermeyer et al.: DA and AD Converters in SiGe Technology.

Technology Choice (DAC)

Interleaving of DA converter cores

  • Needs analog multiplexer (AMUX)
  • Switching noise visible at output
  • AMUX needs
  • High bandwidth
  • Good linearity
  • AMUX sensitive to pattern effects

(e.g. through self heating)

DAC MUX 100G: 17 GS/s DAC MUX AMUX 100G: 17 GS/s

Single core DA converter

  • Significantly lower switching noise
  • Better accuracy/linearity
  • Better device matching

DAC MUX 100G: 34 GS/s

SiGe: Goal is to omit modulator driver. Max.

  • utput swing of latest SiGe devices is

0.8Vse/1.6Vdiff.

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SLIDE 6

SEPTEMBER 19-23, 2010 – TORINO, ITALY

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  • T. Ellermeyer et al.: DA and AD Converters in SiGe Technology.

Pros/Cons of SiGe Devices

Pro‘s

  • Bandwidth >25 GHz possible
  • High Gain
  • High output swing
  • Good device matching
  • Include TIA/AGC and MZM driver

Con‘s

  • Only medium complexity possible (50k

BJT) => DSP needs CMOS

  • Two chips: Massive bus between CMOS

and SiGe required Two Chip solution 3D Packaging with Through Silicon Vias (TSV)

Ref: Roger Allan in Electronic Design

Additional benefits:

  • Always best digital CMOS node
  • Any proprietary DSP possible
  • DAC / ADC independent of

CMOS

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SEPTEMBER 19-23, 2010 – TORINO, ITALY

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  • T. Ellermeyer et al.: DA and AD Converters in SiGe Technology.

Topologies for High Speed DA-Converter Cores

a) R2R Ladder J J All stages have identical devices K K Resistor matching L L Output impedance matching L L Timing matching L L Power (much power dissipated in internal resistors) b) Weighted currents J J Common current summing point => better impedance matching J J less power J J smaller area K K Timing also critical (diff. currents in CML stages) … continued on next slide…

I0 R R

D

I0 I0

D2

2R 2R

2

D

I0 2R 2R

D0

1

D D1

3

D D3

R R R R R R R R OUT OUT n p I0

D

I0 I0

D2

2

D

I0

D0

1

D D1

3

D D3

R R OUT OUT 8 4 2 n p

Examples: 4-bit cores

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SLIDE 8

SEPTEMBER 19-23, 2010 – TORINO, ITALY

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  • T. Ellermeyer et al.: DA and AD Converters in SiGe Technology.

Topologies for High Speed DA-Converter Cores

6-bit Binary weighted currents 6-bit Segmented DAC

(3 LSB binary weighted / 3 MSB thermometer code)

c) Segmented DAC (continued) J J Strongly reduces glitches J J No additional current for output stage L L Additional logic required

R R

K0 K

1

K K1

2

K K2 K

2

K

1

K

2

D

3

D

0 0 0 0 0 0 1 0 0 1 1 0 0 1 1 1 1 1 1 1 3 2 2 1 0 D D K K K

D D0

1

D D1

2 I0 I0 I 4 8 weighted I Binary I 2 2 currents Equal

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SEPTEMBER 19-23, 2010 – TORINO, ITALY

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  • T. Ellermeyer et al.: DA and AD Converters in SiGe Technology.

DAC30 Demonstrator Chip

5.07 mm 5.07 mm

  • 6 bit segmented DAC
  • Demonstrator with

FPGA interface (24 serial lines)

  • 34 GSa/s
  • Single core
  • Half rate clock
  • Configuration register
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SLIDE 10

SEPTEMBER 19-23, 2010 – TORINO, ITALY

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  • T. Ellermeyer et al.: DA and AD Converters in SiGe Technology.

DAC30 Demonstrator Chip

Sampling rate dc – 34 GSa/s Resolution 6 bit Rise/Fall (20/80%) 12 ps INL < 0.2 LSB Full scale swing 800 mV,se 1600 mV,diff ENOB† 5.27 SFDR† 46.9 dB Total power diss. 12.5 W Converter core power 0.4 W Die size 5 . 0 7 x 5 . 0 7 mm² Technology I n f i n e o n b7hf200 Converter core size 0 . 4 0 x 0 . 4 3 mm² DA core incl. last mux/ FF 0 . 8 0 x 1 . 3 0 mm²

†(†‡28 GSa/s, 875 MHz sine wave output,

measured with spectrum analyser up to Nyquist frequency)

DAC output voltage vs. code

  • 1000
  • 750
  • 500
  • 250

250 500 750 1000 8 16 24 32 40 48 56 64

Code Output (differential) mV

540mVpp 1060mVpp 1640mVpp 1930mVpp

Integral Nonlinearity vs. Code

  • 0,2
  • 0,15
  • 0,1
  • 0,05

0,05 0,1 0,15 0,2 8 16 24 32 40 48 56 64

Code INL (LSB)

1250mVpp 1600mVpp 1900mVpp

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SLIDE 11

SEPTEMBER 19-23, 2010 – TORINO, ITALY

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  • T. Ellermeyer et al.: DA and AD Converters in SiGe Technology.

DAC30 Output Waveforms

l Measurements performed with

chips mounted in sockets (cf. Slide “Measurement setup“)

l Driven by Virtex-4

(overclocked to 7 Gb/s)

l Measured with Tektronix

CSA8000 sampling scope (50 GHz bandwidth)

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SEPTEMBER 19-23, 2010 – TORINO, ITALY

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  • T. Ellermeyer et al.: DA and AD Converters in SiGe Technology.

Signal Impairments through Passive Components

  • Signal impairments due to passive components

(e.g. traces, cables, connectors, package, etc.)

  • Essential but challenging to maintain high

frequency performance and effective resolution.

  • For example: Reflection
  • Reflection should be less than 1 LSB:
  • Written in dB:

For 8-bit resolution and |r1|=|r2|: è Return loss < -24 dB over the whole bandwidth on both ends (6-bit: <-18 dB)

r2 r1 DAC

bits ¡

  • f

Number ¡ ¡ ¡ ¡ ¡ ¡ ¡ ¡ ¡ ¡ ¡ ¡ = ≤ ⋅ b r r

b

2 1

2 1

dB dB

2 1

02 . 6 r b r − ⋅ − ≤

Reflections in DAC output signal

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SLIDE 13

SEPTEMBER 19-23, 2010 – TORINO, ITALY

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  • T. Ellermeyer et al.: DA and AD Converters in SiGe Technology.

Topologies for High Speed AD-Converter Cores

a) Massive Parallelization (SAR)

  • ADC cores typically SAR converters

J J SAR: Slow but simple architecture / binary

  • utput

J J Bandwidth is determined by first set of T/H L L Clock distribution difficult L L Lots of calibration b) Flash ADC J J Extremely fast K K Only low resolution: 6 bit => 2^(n-1)=63 comparators in parallel L L Complex logic (thermometer code to binary)

  • Also often used: Half-Flash/Pipeline Flash

c) Interpolation/Folding J J Fast flash type converter J J Number of comparators reduced to 2^(n-1)/m by folding m times (typ. m=2) L L Complex logic (thermometer code) K K Analog stages required

T/H T/H

ADC ADC T/H T/H ADC ADC T/H T/H

T/H FF Thermometer -> Binary DECODE FF FF FF FF FF FF FF

Massive Parallelization Flash Converter

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SEPTEMBER 19-23, 2010 – TORINO, ITALY

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  • T. Ellermeyer et al.: DA and AD Converters in SiGe Technology.

Topologies for High Speed AD-Converter Cores

Vin V3 V0 V1 V2 V4 V5

Q1 Q0 Q2 Q3 Q4 Q5 CLK Q3 Q5 Q4 Q2 Q1 Q0 Vin=V5 V4 V3 V2 V1 V0

d) Serial ripple converter K K Little bit slower than flash J J Simple architecture (number of amps / flip-flops equal to resolution) J J Direct output of gray coded binary K K Highly analog concept K K Propagation delay through each stage critical

Integer Binary Gray 6‘b000000 6‘b000000 1 6‘b000001 6‘b000001 2 6‘b000010 6‘b000011 … … … 31 6‘b011111 6‘b010000 32 6‘b100000 6‘b110000 33 6‘b100001 6‘b110001 … … … 62 6‘b111110 6‘b100001 63 6‘b111111 6‘b100000

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SLIDE 15

SEPTEMBER 19-23, 2010 – TORINO, ITALY

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  • T. Ellermeyer et al.: DA and AD Converters in SiGe Technology.

ADC30 Demonstrator Chip

Sampling rate dc – 34 GSa/s Resolution 6 bit Full scale input range 282 mV (se or diff) INL 1.5 LSB Bandwidth >25 GHz ENOB (30 GSa/s) 4.7 (fin=7.5 GHz) 3.3 (fin=25 GHz) † Total power diss. 10 W C o n v e r t e r c o r e power 4 W Die size 5.07 x 5.07 mm² Converter size 1.0 x 2.6 mm²

†second Nyquist band

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SEPTEMBER 19-23, 2010 – TORINO, ITALY

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  • T. Ellermeyer et al.: DA and AD Converters in SiGe Technology.
  • 6 bit serial ripple converter
  • Demonstrator with FPGA

interface (24 serial lines)

  • 34 GSa/s
  • Four interleaved cores
  • Half rate clock
  • Configuration register

ADC30 Demonstrator Chip

5.07 mm 5.07 mm

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SLIDE 17

SEPTEMBER 19-23, 2010 – TORINO, ITALY

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  • T. Ellermeyer et al.: DA and AD Converters in SiGe Technology.

ADC30 Measurement Results

Upper:

l Internal memory mode (16 Samples) l Running at 30 GSa/s (Int. Osc.)

Right:

l Data transferred to FPGA

(512kSamples)

l Running at 10 GSa/s (FPGA driver

issues)

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SEPTEMBER 19-23, 2010 – TORINO, ITALY

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  • T. Ellermeyer et al.: DA and AD Converters in SiGe Technology.

FPGA/DSP Interface

Current demonstrators based on FPGA constraints:

  • Use of commercial available FPGA evaluation boards.
  • Most commonly used is ML525 (Virtex5): 24 RocketIOs
  • 6-bit resolution; 4x time multiplex => 24 lanes
  • Raw data transfer to avoid protocol overhead
  • MGT clock reference is provided by DAC/ADC
  • Critical:
  • RocketIOs show reset dependent delay
  • Power (50 ohm interfaces)

6.5 Gb/s 26 Gb/s x6 6x 26 Gb/s D[5:0] :20 :2 6.5 GHz Clocks 13 GHz Clk 26 GS/s

FPGA DAC

for SR > 26 GS/s FPGA is overclocked

24x RocketIO REF MUX DAC Core

52x SMA Cables

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SLIDE 19

SEPTEMBER 19-23, 2010 – TORINO, ITALY

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  • T. Ellermeyer et al.: DA and AD Converters in SiGe Technology.

FPGA/DSP Interface

Future demonstrators with FPGA interface:

  • Make use of higher data rates and higher RocketIO count
  • Virtex 7: 56x 10 Gb/s and/or 72x 13 Gb/s
  • Stratix V: 66x 12.5 Gb/s

è Increase Sampling rate and / or number of bits Next generation: >56 GSa/s / 8 bit Interface for 3D-packaging with DSP:

  • Source synchronous
  • Data rate as high as the DSP/CMOS can handle

(to keep I/O count low)

  • Free in changing resolution and/or multiplexing

ratio

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SLIDE 20

SEPTEMBER 19-23, 2010 – TORINO, ITALY

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  • T. Ellermeyer et al.: DA and AD Converters in SiGe Technology.

Measurement Setup

Front: Evaluation Board with DAC module Back: Xilinx ML424 Board with Virtex4-FX140 (24 RocketIOs)

  • 15 GHz clock is fed to the

DAC module (blue cable)

  • Reference clock (:40) for

FPGA is generated by DAC

  • 48 RF-cables for 24

differential SerDes links VEGA30G Module

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SLIDE 21

SEPTEMBER 19-23, 2010 – TORINO, ITALY

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  • T. Ellermeyer et al.: DA and AD Converters in SiGe Technology.

Beyond 100GbE

4-QAM 16-QAM 64-QAM 256-QAM Bandwidth (GHz) 112 56 37 28 bits/Hz 4 8 12 16 GSa/s 112 56 37 28 ENOB (?) 1 2 3 4 GSa/s 224 112 84 56 ENOB 3.8 4.9 5.7 7.0 DAC ADC

Ref: T. Pfau, ECOC‘09

  • Next step will be 400 GbE
  • Data rates up to 448 Gb/s including FEC
  • Keep WDM grid à higher order modulation formats
  • DA-converters become mandatory in TX
  • Very high bandwidth/ENOB à AD-converter may become bottleneck again
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SLIDE 22

SEPTEMBER 19-23, 2010 – TORINO, ITALY

  • T. Ellermeyer et al.: DA and AD Converters in SiGe Technology.

Thank you!