Duo-Binary Circular Turbo Decoder Based on Border Metric Encoding - - PowerPoint PPT Presentation
Duo-Binary Circular Turbo Decoder Based on Border Metric Encoding - - PowerPoint PPT Presentation
Duo-Binary Circular Turbo Decoder Based on Border Metric Encoding for WiMAX for WiMAX Ji-Hoon Kim and In-Cheol Park Division of Electrical Engineering Division of Electrical Engineering KAIST Introduction to Turbo Codes Introduction to Turbo
Introduction to Turbo Codes Introduction to Turbo Codes
- Introduced in 1993
– Error Correcting Performance within 0.5dB of Shannon limit Wid l U d i W CDMA CDMA2000 d WiMAX – Widely Used in W-CDMA, CDMA2000, and WiMAX – Non-Uniform Interleaver – Iterative Decoding Iterative Decoding
SISO RSC Decoder 1 Encoder 1 RSC Interleaver SISO Interleaver
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Encoder 2 Decoder 2
Turbo Codes for WiMAX Turbo Codes for WiMAX
- Double-Binary Turbo Codes
– Better Convergence Larger Minimum Distances
- Circular Coding
– a.k.a Tail-Biting No Tail Bits – Larger Minimum Distances – Reduced Latency – No Tail Bits – Avoid Spectrum Waste
< CTC Encoder for WiMAX > < 4-State Trellis for Circular Coding >
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Max log MAP for Double Binary Max-log-MAP for Double-Binary
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11/00/01/10 Z (Source Bits)
6 5 6 5
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4 4
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3 2 3 2
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1 1
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with Minimum Overhead with Minimum Overhead
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Sliding Window For Non-Binary Turbo Decoder
Small Window Size, Large Frame Size Huge Border Memory!
- Border Metric with the values
- f previous Iteration
Avoid complex dummy calculation
g y
– Avoid complex dummy calculation
Complex Dummy Metric Calculation
Efficient for Efficient for
Dummy Metric Calculation @ Border
Efficient for Efficient for Circular Coding Circular Coding
Proposed Border Metric Encoding Proposed Border Metric Encoding
- Allow only a few values for the Border Metric
Flooring the Original Value to the Closest Power-of-Two Number
Encoding Scheme Encoded Values
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4-bit Encoding ±256, ±128, ±64, ±32, ±16, ±8, ±4, 0 (15 values)
BER Performance Comparison BER Performance Comparison
- Almost No Performance Degradation!
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Proposed Dedicated Interleaver Proposed Dedicated Interleaver
- Accumulator-Based Interleaver
– Small Area due to Simple Hardware
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Key to Low Power Consumption Key to Low-Power Consumption
- Small-Sized Border Memory
– By Border Metric Encoding
I f t A t B d M
- Infrequent Access to Border Memory
– Only one load/store for processing one Window
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Implementation Results Implementation Results
- Time Multiplex Architecture
- Time-Multiplex Architecture
SISO Algorithm Max-log-MAP (Duo-Binary) Operating Frequency 200 MHz Window Size 32 Gate Count 65k Iteration 8 (Fixed) Data Rate 24.26 Mbps
Memory Size Comparison Memory Size Comparison
- Single-Port SRAM Size
– Required for a SISO Decoder 100 % 100.4 % 79.3 % 20.7 %
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Energy Consumption Comparison Energy Consumption Comparison
- For a SISO Decoder @ 1 2dB
- For a SISO Decoder @ 1.2dB
100 % 73.8 % 26.2 %
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Conclusion Conclusion
- Border Metric Encoding is Proposed
– Avoid Complex Dummy Calculation Eff ti f bi T b C d – Effective for non-binary Turbo Codes
- Dedicated Hardware Interleaver is Proposed
– Generate Interleaved Addresses on-the-fly
- CTC Decoder for WiMAX is Designed
g
– Based on ..
- Border Metric Encoding
- Dedicated Hardware Interleaver
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