[PPT] - Digital Design Disc: RTL Combinatorial Components 2-to-4 Decoder PowerPoint Presentation

SLIDE 1

Principles Of

Digital Design

Disc: RTL Combinatorial Components

2-to-4 Decoder 4-to-16 Decoder 8-bit Shifter Absolute Differences Delay in Adder/Subtractor Comparator 6-to-1 Selector

SLIDE 2

RTL Combinatorial Components DIGITAL DESIGN 101, University of California

 Build a 2-to-4 decoder using 1-to-2 decoders  Solution:

Create Truth Table  Connect Wires

2-to-4 Decoders

E A1 A0 C3 C2 C1 C0 1 1 1 1 1 1 1 1 1 1 1 1 X X E A0 C1 C0

1 1 1 1 1 X Truth Table of 1-to-2 decoder Truth Table of 2-to-4 decoder

C3 C2 C1 C0 A0 A1 E

E

1

E

1

E

1

C1 C0

E

1

E A0 2

SLIDE 3

RTL Combinatorial Components DIGITAL DESIGN 101, University of California

 Build a 4-to-16 decoder using 2-to-4 decoders  Solution:

Create Truth Table  Connect Wires

4-to-16 Decoders

3

E

Decoder

C3 C0 A0 C2 C1 A1 3 1 2

SLIDE 4

RTL Combinatorial Components DIGITAL DESIGN 101, University of California

 Build a 4-to-16 decoder using 2-to-4 decoders

4-to-16 Decoders

4 E A3 A2 A1 A0 C15 C14 C13 C12 C11 C10 C9 C8 C7 C6 C5 C4 C3 C2 C1 C0

1 0 0 0 0 1 1 0 0 0 1 1 1 0 0 1 0 1 1 0 0 1 1 1 1 0 1 0 0 1 1 0 1 0 1 1 1 0 1 1 0 1 1 0 1 1 1 1 1 1 0 0 0 1 1 1 0 0 1 1 1 1 0 1 0 1 1 1 0 1 1 1 1 1 1 0 0 1 1 1 1 0 1 1 1 1 1 1 0 1 1 1 1 1 1 1 0 X X X X

SLIDE 5

RTL Combinatorial Components DIGITAL DESIGN 101, University of California

 Build a 4-to-16 decoder using 2-to-4 decoders

4-to-16 Decoders

5

E

Decoder

C3 C0 A0 C2 C1 A1 3 1 2 C3 C2 C1 C0 A0 A2 E A3 A1 C7 C6 C5 C4 C11C10 C9 C8 C15C14C13C12

Decoder Decoder Decoder Decoder Decoder

SLIDE 6

RTL Combinatorial Components DIGITAL DESIGN 101, University of California

8-bit Shifter

 Design a 8-bit shifter that multiplies or divides a two’s

complement number by 2 based on the truth table shown.

 Two’s complement representation:

1. If positive: it stays as simple binary. 2. If negative: invert the digits, then add 1 to the result.



Two’s complement arithmetics:

1. Multiply by 2: shift the binary to the left 1 position cause of base 2. If multiply by 4, then shift left 2 positions,… 2. Divides by 2: shift the binary to the right 1 position, and shift 2 position if divide by 4,…



Notice:

1. The most significant bit (left-most) represents the sign bit. If it’s 0, then it’s

positive. If it’s 1, then it’s negative.

2. Therefore, the left-most bit doesn’t shift, it just stays and propagates to the next.

6 S1 S0 Y Comment

D No Shift 1 Not Used 1 mul(D) Multiply by 2 1 1 div(D) Divide by 2 Truth Table of 4-to-1 Selector

SLIDE 7

RTL Combinatorial Components DIGITAL DESIGN 101, University of California

 Design a 8-bit shifter that multiplies or divides a two’s

complement number by 2 based on the truth table shown.

 Solution:

Multiply by 2 = Shift Left Divide by 2 = Shift Right

Selector Selector Selector Selector Selector Selector Selector Selector

D0 D1 D2 D3 Y0 Y1 Y2 Y3 S1 S0 Y4 Y5 Y6 Y7 D4 D5 D6 D7

3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0

8-bit Shifter

7 S1 S0 Y Comment

D No Shift 1 Not Used 1 mul(D) Multiply by 2 1 1 div(D) Divide by 2 Truth Table of 4-to-1 Selector

SLIDE 8

RTL Combinatorial Components DIGITAL DESIGN 101, University of California

8-bit Shifter

 Design a 8-bit shifter that multiplies or divides a two’s

complement number by 2 based on the truth table shown.

 Error Detection: -128 to 127 (range)

Multiply by 2:

1. Positive case: _ _ _ _ _ _ _ _

If D6=1: overflow occurs (product > 127): 01000000(64) x 2 = 128 (overflow!) Otherwise, Đ6=0, the largest number would be 63, 00111111(63) x 2 = 126 (ok) Condition: D7 = 0 & D6 = 1

2. Negative case: _ _ _ _ _ _ _ _

IF D6=0: 10111111(-65) x 2= -130 (overflow!) Otherwise, we only need D6=1, 11000000(-64) x 2 = -128 (ok). Condition: D7 = 1 & D6 = 0

Divide by 2: We only need D0 = 0

Since D0 = 1, we would have odd number: couldn’t represent decimal.

8 S1 S0 Y Comment

D No Shift 1 Not Used 1 mul(D) Multiply by 2 1 1 div(D) Divide by 2 Truth Table of 4-to-1 Selector 32 128 8 16 1 64 2 4 D6 D6 1 128 64 32 16 8 4 2 1

XOR Gate

SLIDE 9

RTL Combinatorial Components DIGITAL DESIGN 101, University of California

 Design a 8-bit shifter that multiplies or divides a two’s

complement number by 2 based on the truth table shown.

 Solution:

Multiply by 2 = Shift Left Divide by 2 = Shift Right

Selector Selector Selector Selector Selector Selector Selector Selector

D0 D1 D2 D3 Y0 Y1 Y2 Y3 S1 S0 Y4 Y5 Y6 Y7 D4 D5 D6 D7

3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0

8-bit Shifter

9 S1 S0 Y Comment

D No Shift 1 Not Used 1 mul(D) Multiply by 2 1 1 div(D) Divide by 2 Truth Table of 4-to-1 Selector

Error Detection

Error

SLIDE 10

RTL Combinatorial Components DIGITAL DESIGN 101, University of California

 Design a 8-bit shifter that multiplies or divides a two’s

complement number by 2 based on the truth table shown.

 Examples:

10100000 x 2 = -96 x 2 = -192 (overflow!)

Selector Selector Selector Selector Selector Selector Selector Selector

D0 D1 D2 D3 Y0 Y1 Y2 Y3 S1 S0 Y4 Y5 Y6 Y7 D4 D5 D6 D7

3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0

8-bit Shifter

10 S1 S0 Y Comment

D No Shift 1 Not Used 1 mul(D) Multiply by 2 1 1 div(D) Divide by 2 Truth Table of 4-to-1 Selector

Error Detection

Error 1 1

1 1 1 1 1 1 1 1 1 1

SLIDE 11

RTL Combinatorial Components DIGITAL DESIGN 101, University of California

 Design a 8-bit shifter that multiplies or divides a two’s

complement number by 2 based on the truth table shown.

 Examples:

11000100 x 2 = -60 x 2 = -120 (ok)

Selector Selector Selector Selector Selector Selector Selector Selector

D0 D1 D2 D3 Y0 Y1 Y2 Y3 S1 S0 Y4 Y5 Y6 Y7 D4 D5 D6 D7

3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0

8-bit Shifter

11 S1 S0 Y Comment

D No Shift 1 Not Used 1 mul(D) Multiply by 2 1 1 div(D) Divide by 2 Truth Table of 4-to-1 Selector

Error Detection

No Error 1 1 1

1 1 1 1 1 1 1 1

SLIDE 12

RTL Combinatorial Components DIGITAL DESIGN 101, University of California

 Design a 8-bit shifter that multiplies or divides a two’s

complement number by 2 based on the truth table shown.

 Examples:

00110001 x 2 = 49 x 2 = 98 (ok)

Selector Selector Selector Selector Selector Selector Selector Selector

D0 D1 D2 D3 Y0 Y1 Y2 Y3 S1 S0 Y4 Y5 Y6 Y7 D4 D5 D6 D7

3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0

8-bit Shifter

12 S1 S0 Y Comment

D No Shift 1 Not Used 1 mul(D) Multiply by 2 1 1 div(D) Divide by 2 Truth Table of 4-to-1 Selector

Error Detection

No Error 1 1 1

1 1 1 1 1 1 1 1

SLIDE 13

RTL Combinatorial Components DIGITAL DESIGN 101, University of California

Absolute Differences

 Design a circuit that computes the absolute difference of

2 two’s-complement numbers.

 Solution:

Look at some examples: A = 5, B = -3 A – B = 8, |A – B| = 8 B – A = -8, |B – A| = 8 A = -5, B = -3 A – B = -2, |A – B| = 2 B – A = 2, |B – A| = 2 Use 2 subtractors & select positive result based on sign bit

13

selector
A

B B A

sign bit

Y

1

SLIDE 14

RTL Combinatorial Components DIGITAL DESIGN 101, University of California

Adder/Subtractor Delay (1)

 Problem: Determine the delay of an 8-bit carry-ripple Adder/Subtractor when FA

is implemented using (a) XOR gates as in Fig.1, (b) fast gates as in Fig. 2.

S a b a

1

b

1

a

2

b

2

a

3

b

3

a

4

b

4

a

5

b

5

a

6

b

6

a

7

b

7

f0 f1 f2 f3 f4 f5 f6 f7

FA FA FA FA FA FA FA FA

xi yi ci si ci + 1 4. 2 2. 4 2. 4 2. 4 4. 2

xi yi ci si ci + 1 2.4 1.4 1.4 1.4 1.4 1.4

Fig. 1
Fig. 2

1.4 2.4

cout

14

SLIDE 15

RTL Combinatorial Components DIGITAL DESIGN 101, University of California

Adder/Subtractor Delay (2)

8-bit Adder/Subtractor Unit Schematic xi yi ci si ci +

1

4.2 2.4 2.4 2.4 4.2

Input/Output Path Delay (ns)

ci to ci + 1 4.8 ns ci to si 4.2 ns xi, yi to ci + 1 9.0 ns xi, yi to si 8.4 ns

Full–adder delays

 Procedure

1. Identify possible critical path (longest path)
2. Calculate delay with XOR gate implementation

cout S a b a

1

b

1

a

2

b

2

a

3

b

3

a

4

b

4

a

5

b

5

a

6

b

6

a

7

b

7

f0 f1 f2 f3 f4 f5 f6 f7

FA FA FA FA FA FA FA FA 15

SLIDE 16

RTL Combinatorial Components DIGITAL DESIGN 101, University of California

Adder/Subtractor Delay (3)

 Red: 8* (delay of ci to ci + 1) = 8*4.8 = 38.4 ns  Green: (delay of XOR) +(delay of xi, yi to ci + 1 )

+7*(delay of ci to ci + 1)

 = 4.2 + 9 + 7*4.8 = 46.8 ns  Yellow: (delay of XOR )+ delay of xi, yi to ci + 1

+6*(delay of ci to ci + 1)+ (delay of ci to si)

 = 4.2 +9 + 6*4.8 + 4.2 = 46.2 ns

Input/Output Path Delay (ns)

ci to ci + 1 4.8 ns ci to si 4.2 ns xi, yi to ci + 1 9.0 ns xi, yi to si 8.4 ns

Full–adder delays xi yi ci si ci +

1

4.2 2.4 2.4 2.4 4.2 cout S a b a

1

b

1

a

2

b

2

a

3

b

3

a

4

b

4

a

5

b

5

a

6

b

6

a

7

b

7

f0 f1 f2 f3 f4 f5 f6 f7

FA FA FA FA FA FA FA FA

Critical Path !

16

SLIDE 17

RTL Combinatorial Components DIGITAL DESIGN 101, University of California

Adder/Subtractor Delay (4)

8-bit Adder/Subtractor Unit Schematic cout S a b a

1

b

1

a

2

b

2

a

3

b

3

a

4

b

4

a

5

b

5

a

6

b

6

a

7

b

7

f0 f1 f2 f3 f4 f5 f6 f7

FA FA FA FA FA FA FA FA

Full–adder delays

 Procedure

3. Calculate delay with fast

gate implementation

xi yi ci si ci + 1 2.4 1.4 1.4 1.4 1.4 1.4 1.4 2.4

Input/Output Path Delay (ns)

ci to ci + 1 2.8 ns ci to si 3.8 ns xi, yi to ci + 1 5.2 ns xi, yi to si 7.6 ns

17

SLIDE 18

RTL Combinatorial Components DIGITAL DESIGN 101, University of California

Adder/Subtractor Delay (5)

8-bit Adder/Subtractor Unit Schematic Full–adder delays  Red: 8* (delay of ci to ci + 1) = 8*2.8 = 22.4 ns  Green: (delay of XOR) +(delay of xi, yi to ci + 1 )  +7*(delay of ci to ci + 1)  = 4.2 + 5.2 + 7*2.8 = 29 ns  Yellow: (delay of XOR )+ delay of xi, yi to ci + 1

+6*(delay of ci to ci + 1)+ (delay of ci to si)

 = 4.2 + 5.2 + 6*2.8 + 3.8 = 30 ns

xi yi ci si ci + 1 2.4 1.4 1.4 1.4 1.4 1.4 1.4 2.4

Input/Output Path Delay (ns)

ci to ci + 1 2.8 ns ci to si 3.8 ns xi, yi to ci + 1 5.2 ns xi, yi to si 7.6 ns

cout S a b a

1

b

1

a

2

b

2

a

3

b

3

a

4

b

4

a

5

b

5

a

6

b

6

a

7

b

7

f0 f1 f2 f3 f4 f5 f6 f7

FA FA FA FA FA FA FA FA

Critical Path !

18

SLIDE 19

RTL Combinatorial Components DIGITAL DESIGN 101, University of California

Magnitude Comparator (1)

 G = 1 when X > Y,

L = 1 when X < Y, G = L = 0 when X = Y. x

1

x y y

1

G L 2-bit Comparat

r

 Problem: Design a system that determines if three 2-bit

numbers are equal, by connecting 2-bit magnitude comparators together and using additional components if necessary.

19

SLIDE 20

RTL Combinatorial Components DIGITAL DESIGN 101, University of California

Magnitude Comparator (2)

 Procedure:

1. To compare 3 numbers (X, Y, Z), we compare two numbers at a time

using two 2-bit comparators

2. Generate final results from comparator outputs using 4-input NOR

 When X = Y = Z, G1 = L1 = G0 = L0 = 0 and F=1

x

1

y

1

x y G1 2-bit Comparat

r

x

1

x z z

1

2-bit Comparat

r

L1 G0 L0 F

20

SLIDE 21

RTL Combinatorial Components DIGITAL DESIGN 101, University of California

21

2-bit Magnitude Comparator

1 3 2 4 5 7 6 12 13 15 14 8 9 11 10

10 11 01 00 01 00 10 11

1 1 1 1 1 1

x1 x0 y1 y0 G L 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

1 3 2 4 5 7 6 12 13 15 14 8 9 11 10

10 11 01 00 01 00 10 11

y1y x1x0

1 1 1 1 1 1

L Map Truth Table

G = x1y′1 + x0y′1y′0 + x1x0y′0

y1y x1x0

L = x′1 y1 + x′1x′0y0 + x′0y1y0

Logic Schematic  G = 1 when X > Y,

L = 1 when X < Y, G = L = 0 when X = Y. y

1 G L

x

1

x y

G Map Boolean Equations

SLIDE 22

RTL Combinatorial Components DIGITAL DESIGN 101, University of California

22

2-bit Magnitude Comparator – NEW DESIGN

1 3 2 4 5 7 6 12 13 15 14 8 9 11 10

10 11 01 00 01 00 10 11

1 1 1 1 1 1

x1 x0 y1 y0 G L 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

1 3 2 4 5 7 6 12 13 15 14 8 9 11 10

10 11 01 00 01 00 10 11

y1y x1x0

1 1 1 1 1 1

L Map Truth Table y1y x1x0 Logic Schematic  G = 1 when X > Y,

L = 1 when X < Y, G = L = 0 when X = Y. y

1 G L

x

1

x y

G Map Boolean Equations

1 1 1 1

G = x1y′1 + x0y′1 + x1x0 L = x′1 y1 + x′1y0+ y1y0

SLIDE 23

RTL Combinatorial Components DIGITAL DESIGN 101, University of California

Benefits of new design

23

G = x1y′1 + x0y′1 + x1x0 L = x′1 y1 + x′1y0+ y1y0 G = x1y′1 + x0y′1y′0 + x1x0y′0 L = x′1 y1 + x′1x′0y0 + x′0y1y0

1. Save 2 AND gate for each expression => 4 AND gate for each 2-bit

comparator

2. Save 2 INV for each 2-bit comparator (only x1 and y1 are complemented)
3. In case of 2-input logic gate restriction, the new design run faster

Alert: What if the next component doesn’t understand the output G=1, L=1

f the comparator and it costs a lot to modify the next component?

SLIDE 24

RTL Combinatorial Components DIGITAL DESIGN 101, University of California

24

8-bit Magnitude Comparator

Serial Implementation (n comparator delays) G

7

L7 y0 x0

 Larger magnitude comparators can be constructed from basic 2-bit

comparators using the following equations Gi = (xi > yi) OR ((xi = yi) AND (Gi – 1 > Li – 1)) Li = (xi < yi) OR ((xi = yi) AND (Gi – 1 < Li – 1))

G6 L6 G5 L5 G4 L4 G3 L3 G2 L2 G1 L1 G L G L G L G L G L G L G L G L G L G L G L G L G L G L

y1 x1 y2 x2 y3 x3 y4 x4 y5 x5 y6 x6 y7 x7 y0 x0 y1 x1 y2 x2 y3 x3 y4 x4 y5 x5 y6 x6 y7 x7 Parallel Implementation (log(n) comparator delays) G

7

L7

Adjust Adjust

SLIDE 25

RTL Combinatorial Components DIGITAL DESIGN 101, University of California

Compatibility with old system

Cost of new design

Gin Lin Gout Lout 1 1 1 1 1 1

25

Gout = GinL’in Lout = G’inLin Adjustment box

Gout Lout Gin Lin

Cost: 2 AND gates and 2 INV

SLIDE 26

RTL Combinatorial Components DIGITAL DESIGN 101, University of California

Summary: Save and Cost of new design

2n-bit comparator Save Cost Net gain 8 – bit 6 * 7 = 42 gates 4 gates 38 gates 16 – bit 6 * 15 = 90 gates 4 gates 86 gates 32 – bit 6 * 31 = 186 gates 4 gates 182 gates

26

To keep things simple, I’ll assume that AND gate and INV are the same. For each 2-bit comparator, the new design saves 4 AND + 2 INV = 6 gates For each set up of 8-bit, 16-bit or 32-bit comparator, the new design cost 2 AND + 2 INV = 4 gates to match the output of old design For 2n-bit comparator, we need 2n-1 2-bit comparators Conclusion: The saving is linearly correspondent to the increase in bit of the comparator while the cost remains constant. Implementing large comparator will result in higher efficiency.

SLIDE 27

RTL Combinatorial Components DIGITAL DESIGN 101, University of California

Selector Design

 Design a 6-to-1 selector using 2-to-1 selector.  Solution:

Y

D0 D3 S0 S1 S2 D1 D2 D4 D5

1 1 1 1 1 Y

D0 D3 S0 S1 S2 D1 D2 D4 D5

1 1 1 1 1

S2 S1 S0 Y

D0 1 D1 1 D2 1 1 D3 1 X D4 1 X 1 D5

6-to-1 Selector Truth Table

27

1 D0 D1 1 S Y