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Digital Design Disc: RTL Combinatorial Components 2-to-4 Decoder - PowerPoint PPT Presentation

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Principles Of Digital Design Disc: RTL Combinatorial Components 2-to-4 Decoder 4-to-16 Decoder 8-bit Shifter Absolute Differences Delay in Adder/Subtractor Comparator 6-to-1 Selector 2-to-4 Decoders Build a 2-to-4 decoder using 1-to-2

  1. Principles Of Digital Design Disc: RTL Combinatorial Components 2-to-4 Decoder 4-to-16 Decoder 8-bit Shifter Absolute Differences Delay in Adder/Subtractor Comparator 6-to-1 Selector

  2. 2-to-4 Decoders  Build a 2-to-4 decoder using 1-to-2 decoders  Solution: Create Truth Table  Connect Wires A 0 A 1 A 0 E A 0 C 1 C 0 1 0 0 1 E E 1 0 1 1 1 0 0 X 0 0 E C 1 C 0 Truth Table of 1-to-2 decoder E 1 0 E A 1 A 0 C 3 C 2 C 1 C 0 1 0 0 0 0 0 1 E E 1 0 1 0 0 1 0 1 0 1 0 1 1 0 0 1 0 0 1 1 1 1 0 0 0 0 X X 0 0 0 0 C 3 C 2 C 1 C 0 Truth Table of 2-to-4 decoder 2 DIGITAL DESIGN 101, University of California RTL Combinatorial Components

  3. 4-to-16 Decoders  Build a 4-to-16 decoder using 2-to-4 decoders  Solution: Create Truth Table  Connect Wires A 1 A 0 E Decoder 3 2 1 0 C 3 C 2 C 1 C 0 3 DIGITAL DESIGN 101, University of California RTL Combinatorial Components

  4. 4-to-16 Decoders  Build a 4-to-16 decoder using 2-to-4 decoders E A 3 A 2 A 1 A 0 C 15 C 14 C 13 C 12 C 11 C 10 C 9 C 8 C 7 C 6 C 5 C 4 C 3 C 2 C 1 C 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 1 1 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 1 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 1 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 1 0 1 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X X X X 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4 DIGITAL DESIGN 101, University of California RTL Combinatorial Components

  5. 4-to-16 Decoders  Build a 4-to-16 decoder using 2-to-4 decoders A 3 A 2 A 1 A 0 E Decoder A 1 A 0 E Decoder 3 2 1 0 Decoder Decoder Decoder Decoder C 3 C 2 C 1 C 0 C 15 C 14 C 13 C 12 C 11 C 10 C 9 C 8 C 7 C 6 C 5 C 4 C 3 C 2 C 1 C 0 5 DIGITAL DESIGN 101, University of California RTL Combinatorial Components

  6. 8-bit Shifter  Design a 8-bit shifter that multiplies or divides a two’s S 1 S 0 Y Comment complement number by 2 based on 0 0 D No Shift the truth table shown. 0 1 Not Used Multiply by 2 1 0 mul( D )  Two’s complement representation: 1 1 div( D ) Divide by 2 Truth Table of 4-to-1 Selector 1. If positive: it stays as simple binary. 2. If negative: invert the digits, then add 1 to the result. Two’s complement arithmetics:  1. Multiply by 2: shift the binary to the left 1 position cause of base 2. If multiply by 4, then shift left 2 positions,… 2. Divides by 2: shift the binary to the right 1 position, and shift 2 position if divide by 4,… Notice:  1. The most significant bit (left-most) represents the sign bit. If it’s 0, then it’s positive. If it’s 1, then it’s negative. 2. Therefore, the left-most bit doesn’t shift, it just stays and propagates to the next. 6 DIGITAL DESIGN 101, University of California RTL Combinatorial Components

  7. 8-bit Shifter  Design a 8-bit shifter that multiplies or divides a two’s complement number by 2 based on Comment S 1 S 0 Y No Shift the truth table shown. 0 0 D 0 1 Not Used Multiply by 2  Solution: 1 0 mul( D ) Divide by 2 1 1 div( D )  Multiply by 2 = Shift Left Truth Table of 4-to-1 Selector  Divide by 2 = Shift Right D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 0 0 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 Selector Selector Selector Selector Selector Selector Selector Selector S 1 S 0 Y 7 Y 6 Y 5 Y 4 Y 3 Y 2 Y 1 Y 0 7 DIGITAL DESIGN 101, University of California RTL Combinatorial Components

  8. 8-bit Shifter  Design a 8-bit shifter that multiplies or divides a two’s complement number by 2 based on Comment S 1 S 0 Y the truth table shown. 0 0 D No Shift Not Used 0 1  Error Detection: -128 to 127 (range) Multiply by 2 1 0 mul( D )  Multiply by 2: Divide by 2 1 1 div( D ) Truth Table of 4-to-1 Selector 0 1. Positive case: _ _ _ _ _ _ _ _ D6 128 64 32 2 16 8 4 1 If D6=1: overflow occurs (product > 127): 01000000(64) x 2 = 128 (overflow!) Otherwise, Đ6=0, the largest number would be 63, 00111111(63) x 2 = 126 (ok) Condition: D7 = 0 & D6 = 1 1 D6 2. Negative case: _ _ _ _ _ _ _ _ 128 64 32 4 2 16 1 8 IF D6=0: 10111111(-65) x 2= -130 (overflow!) Otherwise, we only need D6=1, 11000000(-64) x 2 = -128 (ok). Condition: D7 = 1 & D6 = 0  Divide by 2: We only need D0 = 0 XOR Gate Since D0 = 1, we would have odd number: couldn’t represent decimal. 8 DIGITAL DESIGN 101, University of California RTL Combinatorial Components

  9. 8-bit Shifter  Design a 8-bit shifter that multiplies or divides a two’s complement number by 2 based on Comment S 1 S 0 Y No Shift the truth table shown. 0 0 D 0 1 Not Used Multiply by 2  Solution: 1 0 mul( D ) Divide by 2 1 1 div( D )  Multiply by 2 = Shift Left Truth Table of 4-to-1 Selector  Divide by 2 = Shift Right D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 0 0 Error Detection 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 Selector Selector Selector Selector Selector Selector Selector Selector S 1 S 0 Error Y 7 Y 6 Y 5 Y 4 Y 3 Y 2 Y 1 Y 0 9 DIGITAL DESIGN 101, University of California RTL Combinatorial Components

  10. 8-bit Shifter  Design a 8-bit shifter that multiplies or divides a two’s complement number by 2 based on Comment S 1 S 0 Y No Shift the truth table shown. 0 0 D 0 1 Not Used Multiply by 2  Examples: 1 0 mul( D ) Divide by 2 1 1 div( D )  10100000 x 2 = -96 x 2 = -192 (overflow!) Truth Table of 4-to-1 Selector 0 1 0 0 0 1 0 0 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 0 1 0 1 0 0 1 0 0 1 1 1 0 0 1 Error Detection 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 1 Selector Selector Selector Selector Selector Selector Selector Selector S 1 0 S 0 0 1 1 0 0 0 0 0 Error Y 7 Y 6 Y 5 Y 4 Y 3 Y 2 Y 1 Y 0 10 DIGITAL DESIGN 101, University of California RTL Combinatorial Components

  11. 8-bit Shifter  Design a 8-bit shifter that multiplies or divides a two’s complement number by 2 based on Comment S 1 S 0 Y No Shift the truth table shown. 0 0 D 0 1 Not Used Multiply by 2  Examples: 1 0 mul( D ) Divide by 2 1 1 div( D )  11000100 x 2 = -60 x 2 = -120 (ok) Truth Table of 4-to-1 Selector 0 0 1 0 1 1 0 0 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 0 0 1 0 0 1 1 0 0 1 1 0 0 0 0 Error Detection 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 1 Selector Selector Selector Selector Selector Selector Selector Selector S 1 0 S 0 0 1 0 1 0 0 0 0 No Error Y 7 Y 6 Y 5 Y 4 Y 3 Y 2 Y 1 Y 0 11 DIGITAL DESIGN 101, University of California RTL Combinatorial Components

  12. 8-bit Shifter  Design a 8-bit shifter that multiplies or divides a two’s complement number by 2 based on Comment S 1 S 0 Y No Shift the truth table shown. 0 0 D 0 1 Not Used Multiply by 2  Examples: 1 0 mul( D ) Divide by 2 1 1 div( D )  00110001 x 2 = 49 x 2 = 98 (ok) Truth Table of 4-to-1 Selector 1 1 0 0 0 0 1 0 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 1 0 0 0 0 0 0 0 1 1 0 1 0 0 0 Error Detection 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 1 Selector Selector Selector Selector Selector Selector Selector Selector S 1 0 S 0 0 0 0 0 0 1 1 1 No Error Y 7 Y 6 Y 5 Y 4 Y 3 Y 2 Y 1 Y 0 12 DIGITAL DESIGN 101, University of California RTL Combinatorial Components

  13. Absolute Differences  Design a circuit that computes the absolute difference of 2 two’s-complement numbers.  Solution: A B B A  Look at some examples: A = 5, B = -3 - - A – B = 8, |A – B| = 8 B – A = -8, |B – A| = 8 1 0 A = -5, B = -3 selector sign bit A – B = -2, |A – B| = 2 B – A = 2, |B – A| = 2 Y  Use 2 subtractors & select positive result based on sign bit 13 DIGITAL DESIGN 101, University of California RTL Combinatorial Components

  14. Adder/Subtractor Delay (1)  Problem: Determine the delay of an 8-bit carry-ripple Adder/Subtractor when FA is implemented using (a) XOR gates as in Fig.1, (b) fast gates as in Fig. 2. x i y i a a a a a a a a b b b b b b b b 7 7 6 6 5 5 4 4 3 3 2 2 1 1 0 0 2. S 4. 4 2 2. 2. c i + 1 c i 4 4 4. c out 2 FA FA FA FA FA FA FA FA Fig. 1 s i c i 2.4 y i 1.4 1.4 2.4 1.4 1.4 x i f 7 f 6 f 5 f 4 f 3 f 2 f 1 f 0 1.4 1.4 Fig. 2 s i c i + 1 14 DIGITAL DESIGN 101, University of California RTL Combinatorial Components

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