Distributed Systems for Real-Time Applications: Analysis and - - PowerPoint PPT Presentation

1 May 2003

Distributed Systems for Real-Time Applications: Analysis and Synthesis

Petru Eles

Department of Computer and Information Science (IDA) Linköpings universitet http://www.ida.liu.se/~petel/

2 May 2003

Linköping Linköping Stockholm

3 May 2003

■

Linköping University 23000 students, 1400 PhD students, 3500 staff&faculty

❚

Department of Computer and Information Science 207 employees 16 professors, 23 associate & assistant professors 90 PhD students

• Embedded Systems Laboratory

2 professors 1 assistant professor 10 PhD students

4 May 2003

■

National Graduate School in Computer Science

■

Socware - the Swedish Systems-on-Chip initiative

■

Centres of excellence

❚

Stringent - the Strategic Integrated Electronic Systems Research Center at LiTH

❚

ISIS Information Systems for Industrial Control and Supervision

Distributed Systems for Real-Time Applications: Analysis and Synthesis Petru Eles 5 May 2003

Outline

■

Embedded Real-Time System

■

System-level Design Flow

■

Distributed Embedded Real-Time Systems

❚

Application Model

❚

Heterogeneous Systems

❚

Time/Event Triggered Tasks

❚

Static/Dynamic Communication

❚

Analysis&Optimization

■

Single/Multi-cluster Heterogeneous Distributed Architectures

❚

Analysis&Optimization

■

Incremental Design Process

Distributed Systems for Real-Time Applications: Analysis and Synthesis Petru Eles 6 May 2003

Embedded Real-Time Systems

Distributed Systems for Real-Time Applications: Analysis and Synthesis Petru Eles 7 May 2003

Embedded Real-Time Systems

■

Dedicated (not general purpose)

■

Interact with the environment

■

Consist of a collection of

• programmable parts
• ASICs and other standard components
• sensors and actuators

Distributed Systems for Real-Time Applications: Analysis and Synthesis Petru Eles 8 May 2003

What Makes Them Different?

☞ Like with “ordinary” applications, functionality and user interfaces are

• ften very complex.

But, in addition to this:

❚

Time constraints

❚

Power constraints

❚

Cost constraints

❚

Safety

❚

Time to market

Distributed Systems for Real-Time Applications: Analysis and Synthesis Petru Eles 9 May 2003

Why Is the Design of Embedded Systems Difficult?

■

In order to achieve all these constraints, systems have to be

• highly optimized
• verified for safety
• delivered in (short) time

☞ Both hardware and software aspects have to be considered simultaneously!

Distributed Systems for Real-Time Applications: Analysis and Synthesis Petru Eles 10 May 2003

A Design Flow

Hardware model Software model Software Generation Hardware Synthesis Software blocks Hardware blocks Prototyping Product Fabrication Simulation Testing Informal Specification, Requirements Select an Architecture OK not OK not OK

Distributed Systems for Real-Time Applications: Analysis and Synthesis Petru Eles 11 May 2003

A Design Flow

Hardware model Software model Software Generation Hardware Synthesis Software blocks Hardware blocks Prototyping Product Fabrication Simulation Testing

Informal Specification, Requirements

Select an Architecture

Distributed Systems for Real-Time Applications: Analysis and Synthesis Petru Eles 12 May 2003

Hardware model Software model Software Generation Hardware Synthesis Software blocks Hardware blocks Prototyping Product Fabrication Simulation Testing Informal Specification, Requirements

A Design Flow

Select an Architecture µProcessor Memory Hardware Accelerator

Distributed Systems for Real-Time Applications: Analysis and Synthesis Petru Eles 13 May 2003

A Design Flow

Hardware model Software model

Software Generation Hardware Synthesis Software blocks Hardware blocks Prototyping Product Fabrication Simulation Testing Informal Specification, Requirements Select an Architecture

• C++
• VHDL

Distributed Systems for Real-Time Applications: Analysis and Synthesis Petru Eles 14 May 2003

Hardware model Software model Software Generation Hardware Synthesis

Software blocks Hardware blocks

Prototyping Product Fabrication Simulation Testing Informal Specification, Requirements Select an Architecture

A Design Flow

100100010110 010010000101 110001010100 010010011000

Distributed Systems for Real-Time Applications: Analysis and Synthesis Petru Eles 15 May 2003

A Design Flow

Hardware model Software model Software Generation Hardware Synthesis Software blocks Hardware blocks

Prototyping

Product Fabrication Simulation Testing Informal Specification, Requirements Select an Architecture not OK not OK

Distributed Systems for Real-Time Applications: Analysis and Synthesis Petru Eles 16 May 2003

What Is Missing?

Fabrication Informal Specification, Requirements

• Arch. Selection

OK not OK

• Softw. model
• Hardw. model
• Softw. Generation
• Hardw. Synthesis
• Softw. blocks
• Hardw. blocks

Prototype not OK Simulation Testing

Distributed Systems for Real-Time Applications: Analysis and Synthesis Petru Eles 17 May 2003

Fabrication Informal Specification, Requirements OK not OK

• Softw. model
• Hardw. model
• Softw. Generation
• Hardw. Synthesis
• Softw. blocks
• Hardw. blocks

Prototype not OK Simulation Testing

What Is Missing?

?

?

Distributed Systems for Real-Time Applications: Analysis and Synthesis Petru Eles 18 May 2003

The System Level

Fabrication Functional Simulation

• Arch. Selection

System architecture Mapping Estimation Mapped and scheduled model Scheduling Formal Verification

• Softw. model
• Hardw. model
• Softw. Generation
• Hardw. Synthesis
• Softw. blocks
• Hardw. blocks

Simulation Simulation Simulation Formal Verification Prototype System model Modeling

Informal Specification, Requirements

Distributed Systems for Real-Time Applications: Analysis and Synthesis Petru Eles 19 May 2003

The System Level

Fabrication Informal Specification, Requirements Functional Simulation

• Arch. Selection

System architecture Mapping Estimation Mapped and scheduled model Scheduling Formal Verification

• Softw. model
• Hardw. model
• Softw. Generation
• Hardw. Synthesis
• Softw. blocks
• Hardw. blocks

Simulation Simulation Simulation Formal Verification Prototype

τ1 τ3 τ6 τ7 τ8 τ4 τ2 τ5

System model Modeling

Distributed Systems for Real-Time Applications: Analysis and Synthesis Petru Eles 20 May 2003

The System Level

System model Fabrication Informal Specification, Requirements Modeling

• Arch. Selection

System architecture Mapping Estimation Mapped and scheduled model Scheduling

• Softw. model
• Hardw. model
• Softw. Generation
• Hardw. Synthesis
• Softw. blocks
• Hardw. blocks

Simulation Simulation Simulation Formal Verification Prototype

Verification engine

Yes No

No

τ1 τ3 τ6 τ7 τ8 τ4 τ2 τ5

Functional Simulation Formal Verification Functionality OK?

Distributed Systems for Real-Time Applications: Analysis and Synthesis Petru Eles 21 May 2003

The System Level

System model Fabrication Informal Specification, Requirements Functional Simulation Modeling Mapping Estimation Mapped and scheduled model Scheduling Formal Verification

• Softw. model
• Hardw. model
• Softw. Generation
• Hardw. Synthesis
• Softw. blocks
• Hardw. blocks

Simulation Simulation Simulation Formal Verification Prototype

µProcessor Memory Hardware Accelerator µProcessor

• Arch. Selection

System architecture

Distributed Systems for Real-Time Applications: Analysis and Synthesis Petru Eles 22 May 2003

• Softw. model

The System Level

System model Fabrication Informal Specification, Requirements Functional Simulation Modeling

• Arch. Selection

System architecture

Mapping

Estimation Mapped and scheduled model Scheduling Formal Verification

• Hardw. model
• Softw. Generation
• Hardw. Synthesis
• Softw. blocks
• Hardw. blocks

Simulation Simulation Simulation Formal Verification Prototype τ1

τ3 τ6 τ7 τ8 τ4 τ2 τ5

µProcessor Memory Hardware Accelerator µProcessor

Distributed Systems for Real-Time Applications: Analysis and Synthesis Petru Eles 23 May 2003

System model Fabrication Informal Specification, Requirements Functional Simulation Modeling

• Arch. Selection

System architecture Mapping Mapped and scheduled model Scheduling Formal Verification

• Softw. model
• Hardw. model
• Softw. Generation
• Hardw. Synthesis
• Softw. blocks
• Hardw. blocks

Simulation Simulation Simulation Formal Verification Prototype

The System Level

Estimation

Task Execution Time Energy Consumption τ1 5 235 τ2 9 450 τ3 5 210 τ4 10 390 τ5 11 440 τ6 17 570 τ7 5 205 τ8 5 150

Distributed Systems for Real-Time Applications: Analysis and Synthesis Petru Eles 24 May 2003

System model Fabrication Informal Specification, Requirements Functional Simulation Modeling

• Arch. Selection

System architecture Mapping Estimation Mapped and scheduled model Formal Verification

• Softw. model
• Hardw. model
• Softw. Generation
• Hardw. Synthesis
• Softw. blocks
• Hardw. blocks

Simulation Simulation Simulation Formal Verification Prototype

The System Level

µp1 µp2 bus

m1-3 m2-4 m7-8

ASIC

τ1 τ2 τ3 τ6 τ5 τ7 τ4 τ8

Scheduling

Distributed Systems for Real-Time Applications: Analysis and Synthesis Petru Eles 25 May 2003

• Softw. model

The System Level

System model Fabrication Informal Specification, Requirements Functional Simulation Modeling

• Arch. Selection

System architecture Mapping Estimation

Mapped and scheduled model

Scheduling Formal Verification

• Hardw. model
• Softw. Generation
• Hardw. Synthesis
• Softw. blocks
• Hardw. blocks

Simulation Simulation

Simulation Formal Verification

Prototype

Verification engine

Yes No

Functionality & Timing

τ1 τ3 τ6 τ7 τ8 τ4 τ2 τ5

OK?

No No

Distributed Systems for Real-Time Applications: Analysis and Synthesis Petru Eles 26 May 2003

The System Level

System model Fabrication Informal Specification, Requirements Functional Simulation Modeling

• Arch. Selection

System architecture Mapping Estimation Mapped and scheduled model Scheduling Formal Verification

• Softw. model
• Hardw. model
• Softw. Generation
• Hardw. Synthesis
• Softw. blocks
• Hardw. blocks

Simulation

Simulation

Simulation Formal Verification Prototype

• C++

VHDL

• VHDL

Simulator Compiler& ISA model Co-simulation engine N

• t

O K

Distributed Systems for Real-Time Applications: Analysis and Synthesis Petru Eles 27 May 2003

System Level Design Flow

System model Fabrication Informal Specification, Requirements Functional Simulation Modeling

• Arch. Selection

System architecture Mapping Estimation Mapped and scheduled model Scheduling OK not OK not OK Formal Verification

• Softw. model
• Hardw. model
• Softw. Generation
• Hardw. Synthesis
• Softw. blocks
• Hardw. blocks

Simulation Simulation Simulation Formal Verification Prototype not OK

Distributed Systems for Real-Time Applications: Analysis and Synthesis Petru Eles 28 May 2003

System-level Design

☞ System-level design is performed before any effective hardware/software implementation has been generated.

■

It is a design loop including the exploration of different

• architectures (including communication infrastructure)
• mappings
• schedules

■

It is supported by

• system level models
• estimation
• analysis & formal verification
• simulation

Distributed Systems for Real-Time Applications: Analysis and Synthesis Petru Eles 29 May 2003

System-level Design

☞ System-level design is performed before any effective hardware/software implementation has been generated.

■

It is a design loop including the exploration of different

• architectures (including communication infrastructure)
• mappings
• schedules

■

It is supported by

• system level models
• estimation/analysis
• analysis & formal verification
• simulation

Hardware Architecture and Software are jointly developed!

Distributed Systems for Real-Time Applications: Analysis and Synthesis Petru Eles 30 May 2003

Platforms and IP-blocks

System model Fabrication Informal Specification, Requirements Functional Simulation Modeling

• Arch. Selection

System architecture Mapping Estimation Mapped and scheduled model Scheduling OK not OK not OK Formal Verification

• Softw. model
• Hardw. model
• Softw. Generation
• Hardw. Synthesis
• Softw. blocks
• Hardw. blocks

Simulation Simulation Simulation Formal Verification Prototype not OK

Distributed Systems for Real-Time Applications: Analysis and Synthesis Petru Eles 31 May 2003

Platforms and IP-blocks

System model Fabrication Informal Specification, Requirements Functional Simulation Modeling Mapping Estimation Mapped and scheduled model Scheduling Formal Verification

• Softw. model
• Hardw. model
• Softw. Generation
• Hardw. Synthesis
• Softw. blocks
• Hardw. blocks

Simulation Simulation Simulation Formal Verification Prototype

• Arch. Selection

System architecture Component library

Distributed Systems for Real-Time Applications: Analysis and Synthesis Petru Eles 32 May 2003

Platforms and IP-blocks

System model Fabrication Informal Specification, Requirements Functional Simulation Modeling Mapping Estimation Mapped and scheduled model Scheduling Formal Verification

• Softw. model
• Hardw. model
• Softw. Generation
• Hardw. Synthesis
• Softw. blocks
• Hardw. blocks

Simulation Simulation Formal Verification Prototype

• Arch. Selection

System architecture Component library Processor Architecture Algorithm(s) Compiler Simulator

Simulation

Performance numbers

Distributed Systems for Real-Time Applications: Analysis and Synthesis Petru Eles 33 May 2003

Platforms and IP-blocks

System model Fabrication Informal Specification, Requirements Functional Simulation Modeling Mapping Estimation Mapped and scheduled model Scheduling Formal Verification

• Softw. model
• Hardw. model
• Softw. Generation
• Hardw. Synthesis
• Softw. blocks
• Hardw. blocks

Simulation Simulation Formal Verification Prototype

• Arch. Selection

System architecture Component library Platform Architecture Simulator

Simulation

Performance numbers Mapping/ Compiling Applications

Distributed Systems for Real-Time Applications: Analysis and Synthesis Petru Eles 34 May 2003

Platforms and IP-blocks

System model Fabrication Informal Specification, Requirements Functional Simulation Modeling Mapping Estimation Mapped and scheduled model Scheduling Formal Verification

• Softw. model
• Hardw. model
• Softw. Generation
• Hardw. Synthesis
• Softw. blocks
• Hardw. blocks

Simulation Simulation Formal Verification Prototype

• Arch. Selection

System architecture Component library Platform Architecture Simulator

Simulation

Performance numbers Mapping/ Compiling Applications Platform Instance Simulator Performance numbers Mapping/ Compiling Application Platform Architecture

Distributed Systems for Real-Time Applications: Analysis and Synthesis Petru Eles 35 May 2003

That’s what’s we are looking at

Fabrication Informal Specification, Requirements Functional Simulation Modeling Formal Verification

• Softw. model
• Hardw. model
• Softw. Generation
• Hardw. Synthesis
• Softw. blocks
• Hardw. blocks

Simulation Simulation Simulation Formal Verification Prototype Analysis System model

• Arch. Selection

System architecture Mapping Estimation Mapped and scheduled model Scheduling not OK not OK OK

Distributed Systems for Real-Time Applications: Analysis and Synthesis Petru Eles 36 May 2003

That’s what’s we are looking at

Fabrication Informal Specification, Requirements Functional Simulation Modeling Formal Verification

• Softw. model
• Hardw. model
• Softw. Generation
• Hardw. Synthesis
• Softw. blocks
• Hardw. blocks

Simulation Simulation Simulation Formal Verification Prototype

In the context of Distributed Heterogeneous Systems

Analysis System model

• Arch. Selection

System architecture Mapping Estimation Mapped and scheduled model Scheduling not OK not OK OK

Distributed Systems for Real-Time Applications: Analysis and Synthesis Petru Eles 37 May 2003

Outline

■

Embedded Real-Time System

■

System-level Design Flow

■

Distributed Embedded Real-Time Systems

❚

Application Model

❚

Heterogeneous Systems

❚

Time/Event Triggered Tasks

❚

Static/Dynamic Communication

❚

Analysis&Optimization

■

Single/Multi-cluster Heterogeneous Distributed Architectures

❚

Analysis&Optimization

■

Incremental Design Process

Distributed Systems for Real-Time Applications: Analysis and Synthesis Petru Eles 38 May 2003

Distributed Embedded Systems

■ ■ ■ ■ ■ ■

I/O Interface CPU RAM ROM ASIC

• Comm. Controller

Sensors&Actuators

Distributed Systems for Real-Time Applications: Analysis and Synthesis Petru Eles 39 May 2003

Distributed Embedded Systems

■ ■ ■ ■ ■ ■

Factory Systems ...

...

...

... ...

Automotive Electronics NoCs

Distributed Systems for Real-Time Applications: Analysis and Synthesis Petru Eles 40 May 2003

Distributed Embedded Systems

Why?

■

Physical constraints

• Operation close to sensor;

■

Modularity constraints

■

Safety Constraints

■

Performance

■ ■ ■ ■ ■ ■

Distributed Systems for Real-Time Applications: Analysis and Synthesis Petru Eles 41 May 2003

Distributed Embedded Systems

■

Dimensions of Heterogeneity

❚

Architectural Components

❚

Hardware/Software

❚

Software Implementation (language, OS)

❚

Data/Control Dominated

❚

Continuous/Discrete

❚

Network Protocol

❚

RT Design Approach/Scheduling Policy

❚

• - - - - - - - - - - - - - -

Distributed Systems for Real-Time Applications: Analysis and Synthesis Petru Eles 42 May 2003

Distributed Embedded Systems

☞ Heterogeneous Nature of Implemented Functions

Distributed Systems for Real-Time Applications: Analysis and Synthesis Petru Eles 43 May 2003

Distributed Embedded Systems

Engine Control

❚ hard real-time

Distributed Systems for Real-Time Applications: Analysis and Synthesis Petru Eles 44 May 2003

Distributed Embedded Systems

Engine Control

❚ hard real-time

Power Train (break-by-wire, ABS)

❚ hard real-time ❚ highly safety-critical

Distributed Systems for Real-Time Applications: Analysis and Synthesis Petru Eles 45 May 2003

Distributed Embedded Systems

Engine Control

❚ hard real-time

Power Train (break-by-wire, ABS)

❚ hard real-time ❚ highly safety-critical

Air Conditioning

❚ soft real-time

Distributed Systems for Real-Time Applications: Analysis and Synthesis Petru Eles 46 May 2003

Distributed Embedded Systems

■

Dimensions of Heterogeneity

❚

Architectural Components

❚

Hardware/Software

❚

Software Implementation (language, OS)

❚

Data/Control Dominated

❚

Continuous/Discrete

❚

Network Protocol

❚

RT Design Approach/Scheduling Policy

❚

• - - - - - - - - - - - - - -

Distributed Systems for Real-Time Applications: Analysis and Synthesis Petru Eles 47 May 2003

☞ An application is modelled as a set of task graphs:

Application Model

Γ1 Period: TΓ1 Deadline: DΓ1 Γ2 Period: TΓ2 Deadline: DΓ2 Γ3 Period: TΓ3 Deadline: DΓ3

Distributed Systems for Real-Time Applications: Analysis and Synthesis Petru Eles 48 May 2003

Application Model

☞ An application is modelled as a set of task graphs: Γ1 Period: TΓ1 Deadline: DΓ1 Γ2 Period: TΓ2 Deadline: DΓ2 Γ3 Period: TΓ3 Deadline: DΓ3

τ0 τ7 τ8 τ9 τ12 τ3 τ1 τ2 τ6 τ5 τ4 τ11 τ14 τ15 τ16 τ10 τ32 τ17 τ13

Distributed Systems for Real-Time Applications: Analysis and Synthesis Petru Eles 49 May 2003

Application Model

☞ An application is modelled as a set of task graphs: Γ1 Period: TΓ1 Deadline: DΓ1 Γ2 Period: TΓ2 Deadline: DΓ2 Γ3 Period: TΓ3 Deadline: DΓ3 Cτ3 δτ3

τ0 τ7 τ8 τ9 τ12 τ3 τ1 τ2 τ6 τ5 τ4 τ11 τ14 τ15 τ16 τ10 τ32 τ17 τ13

Distributed Systems for Real-Time Applications: Analysis and Synthesis Petru Eles 50 May 2003

Application Model

☞ An application is modelled as a set of task graphs: Γ1 Period: TΓ1 Deadline: DΓ1 Γ2 Period: TΓ2 Deadline: DΓ2 Γ3 Period: TΓ3 Deadline: DΓ3

C C D D K K C

Eles et al, IEEE TonVLSI 2000

τ0 τ7 τ8 τ9 τ12 τ3 τ1 τ2 τ6 τ5 τ4 τ11 τ14 τ15 τ16 τ10 τ32 τ17 τ13

Distributed Systems for Real-Time Applications: Analysis and Synthesis Petru Eles 51 May 2003

Application Model

☞ An application is modelled as a set of task graphs: Γ1 Period: TΓ1 Deadline: DΓ1 Γ2 Period: TΓ2 Deadline: DΓ2 Γ3 Period: TΓ3 Deadline: DΓ3

C C D D K K C

D∧C∧K

τ0 τ7 τ8 τ9 τ12 τ3 τ1 τ2 τ6 τ5 τ4 τ11 τ14 τ15 τ16 τ10 τ32 τ17 τ13

Distributed Systems for Real-Time Applications: Analysis and Synthesis Petru Eles 52 May 2003

Application Model

☞ An application is modelled as a set of task graphs: Γ1 Period: TΓ1 Deadline: DΓ1 Γ2 Period: TΓ2 Deadline: DΓ2 Γ3 Period: TΓ3 Deadline: DΓ3

C C D D K K C

D∧C∧K

τ0 τ7 τ8 τ9 τ12 τ3 τ1 τ2 τ6 τ5 τ4 τ11 τ14 τ15 τ16 τ10 τ32 τ17 τ13

Distributed Systems for Real-Time Applications: Analysis and Synthesis Petru Eles 53 May 2003

Heterogeneous Distributed Real-Time Systems

■

RT Design Approach

■

Network Protocol

Distributed Systems for Real-Time Applications: Analysis and Synthesis Petru Eles 54 May 2003

Heterogeneous Distributed Real-Time Systems

■

RT Design Approach

■

Network Protocol

• Time triggered
• Event triggered

Distributed Systems for Real-Time Applications: Analysis and Synthesis Petru Eles 55 May 2003

Heterogeneous Distributed Real-Time Systems

■

RT Design Approach

■

Network Protocol

• Time triggered
• Event triggered
• Static
• Dynamic

Distributed Systems for Real-Time Applications: Analysis and Synthesis Petru Eles 56 May 2003

Time Triggered Systems

■

The execution of tasks is initiated at pre-determined moments in time.

■

Task initiation is performed by the real-time kernel typically based on information stored in a schedule table.

Distributed Systems for Real-Time Applications: Analysis and Synthesis Petru Eles 57 May 2003

Time Triggered Systems

τ1 τ3 τ6 τ7 τ8 τ4 τ2 τ5

µProcessor µProcessor µProcessor

m1-3 m2-4 m7-8

Distributed Systems for Real-Time Applications: Analysis and Synthesis Petru Eles 58 May 2003

Time Triggered Systems

τ1 τ3 τ6 τ7 τ8 τ4 τ2 τ5

µProcessor µProcessor

µp1 µp2 bus

m1-3 m2-4 m7-8 τ1 τ2 τ3 τ6 τ5 τ7 τ4 τ8 5 6 14 11 28 39 44 16 45

µProcessor

µp3

m1-3 m2-4 m7-8

Distributed Systems for Real-Time Applications: Analysis and Synthesis Petru Eles 59 May 2003

Time Triggered Systems

Scheduling Schedule table Static cyclic schedule Task/Comm. Start Time τ1 τ2 5 τ3 6 τ4 16 τ5 28 τ6 11 τ7 39 τ8 45 m1-3 5 m2-4 14 m7-8 44 Over a Hyperperiod

Distributed Systems for Real-Time Applications: Analysis and Synthesis Petru Eles 60 May 2003

Time Triggered Systems

Scheduling Schedule table Static cyclic schedule Task/Comm. Start Time τ1 τ2 5 τ3 6 τ4 16 τ5 28 τ6 11 τ7 39 τ8 45 m1-3 5 m2-4 14 m7-8 44 Over a Hyperperiod The system is schedulable if it is possible to build a schedule table such that all deadlines are satisfied.

Distributed Systems for Real-Time Applications: Analysis and Synthesis Petru Eles 61 May 2003

Time Triggered Systems

■

In the case of Conditional Task Graphs we cannot build a static schedule Quasi-static scheduling

Distributed Systems for Real-Time Applications: Analysis and Synthesis Petru Eles 62 May 2003

Time Triggered Systems

■

In the case of Conditional Task Graphs we cannot build a static schedule

τ0 τ7 τ8 τ9 τ12 τ3 τ1 τ2 τ6 τ5 τ4 τ11 τ14 τ15 τ16 τ10 τ32 τ17 τ13

C C D D K K C

µProcessor µProcessor µProcessor

Distributed Systems for Real-Time Applications: Analysis and Synthesis Petru Eles 63 May 2003

Time Triggered Systems

true D D∧C D∧C∧K D∧C∧K D∧C D∧C∧K D∧C∧K D D∧C D∧C

τ1 τ2

3

τ10

34 34 26 26 34 26

τ11 τ14

35 24

τ17

29 37 30 26 22 24

τ18 (1→3)

3

τ19 (2→5)

9 10

τ20 (3→10)

28 20 21 21 22 18 D 6 C 7 7 K 15 15

Eles et al, IEEE TonVLSI 2000

Distributed Systems for Real-Time Applications: Analysis and Synthesis Petru Eles 64 May 2003

Time Triggered Systems

Why do we like (quasi)static cyclic scheduling?

■

High predictability

■

Easy to debug/validate

■

Low execution time overhead Suitable for safety-critical applications

Distributed Systems for Real-Time Applications: Analysis and Synthesis Petru Eles 65 May 2003

Time Triggered Systems

Some problems with (quasi)static cyclic scheduling:

■

Not flexible:

❚

quality degrades rapidly if periods and execution times deviate from those predicted;

❚

if new tasks are added, the whole schedule has to be regenerated.

■

Static scheduling for large task sets is computationally very expensive.

■

Urgent events (interrupts) are handled purely:

❚

time slots are statically allocated for polling and handling such events.

■

Very long hyper-periods have to be avoided:

❚

the periods of individual tasks have to be adjusted; this can lead to artificially reduced periods ⇒ artificially increased load ⇒ waste of processor time.

■

Tasks have to be “manually” split, in order to make the system schedulable.

Distributed Systems for Real-Time Applications: Analysis and Synthesis Petru Eles 66 May 2003

Event Triggered Systems

■

The execution of tasks is initiated by the occurrence of a certain event.

■

Task initiation is performed by the real-time kernel which selects and executes the ready task with the highest priority.

■

Task scheduling is, typically, preemptive.

■

No schedule (predetermined activation times) is generated off-line.

Distributed Systems for Real-Time Applications: Analysis and Synthesis Petru Eles 67 May 2003

Event Triggered Systems

τ1 τ3 τ2

µProcessor µProcessor

µp1 µp2

τ1 O1 m1 m2 prioritym1 < prioritym2 priorityτ2 > priorityτ3 O2 O3 a2 a3 O1,2 = O1,3

❚ Arrival time ai: The time at which τi becomes

ready for execution.

❚ Offset Oi: The earliest possible arrival time of τi.

Distributed Systems for Real-Time Applications: Analysis and Synthesis Petru Eles 68 May 2003

Event Triggered Systems

τ1 τ3 τ2 m1 m2 prioritym1 < prioritym2 priorityτ2 > priorityτ3

µp1 µp2 bus

τ1 O1 O2 O3 a2 a3

µProcessor µProcessor

m2

Distributed Systems for Real-Time Applications: Analysis and Synthesis Petru Eles 69 May 2003

Event Triggered Systems

τ1 τ3 τ2 m1 m2 prioritym1 < prioritym2 priorityτ2 > priorityτ3

µp1 µp2 bus

τ1 τ3 O1 O2 O3 a2 a3

❚ Start time si: Time when a task starts execution. ❚ Release jitter Ji: The delay between the arrival of

τi and the start of its execution.

µProcessor µProcessor

m2 m1 J3 J2 s3

Distributed Systems for Real-Time Applications: Analysis and Synthesis Petru Eles 70 May 2003

Event Triggered Systems

τ1 τ3 τ2 m1 m2 prioritym1 < prioritym2 priorityτ2 > priorityτ3

µp1 µp2 bus

τ1 τ3 O1 O2 O3 a2 a3

❚ Interference wi: The time τi is preempted by

higher priority tasks.

❚ Queuing delay wmi: The delay experienced by

mi before being sent.

µProcessor µProcessor

m2 m1 J3 J2 s3 τ2 w3 wm1

Distributed Systems for Real-Time Applications: Analysis and Synthesis Petru Eles 71 May 2003

Event Triggered Systems

τ3 τ1 τ3 τ2 m1 m2 prioritym1 < prioritym2 priorityτ2 > priorityτ3

µp1 µp2 bus

τ1 τ3 O1 O2 O3 a2 a3

❚ Response time ri: The time from the arrival of

τi until it finishes execution.

µProcessor µProcessor

m2 m1 J3 J2 s3 τ2 w3 wm1 r2 r3

Distributed Systems for Real-Time Applications: Analysis and Synthesis Petru Eles 72 May 2003

Event Triggered Systems

Schedulability analysis (is the system schedulable?)

Distributed Systems for Real-Time Applications: Analysis and Synthesis Petru Eles 73 May 2003

Event Triggered Systems

Schedulability analysis (is the system schedulable?)

■

Utilisation based tests

❚

Feasibility test for processes with RM priority assignment (Liu&Layland ‘73):

❚

Problems:

• Such tests are valid only under restrictive conditions.
• They are pessimistic.
• Necessary and sufficient tests (if available) are computationally

expensive. Ci Ti

• i

1 = n

∑

n 2

1 n

• 1

–       ≤

Distributed Systems for Real-Time Applications: Analysis and Synthesis Petru Eles 74 May 2003

Event Triggered Systems

Schedulability analysis (is the system schedulable?)

■

Response time analysis

❚

Calculate worst case response time ri for each task τi. If, for each task ri ≤ Di, then and only then the task set is schedulable.

❚

The basic equation (Audslay et al ‘91):

❚

Problem

• The above formula is exact (necessary and sufficient) only in

particular cases (monoprocessor, independent tasks, etc.).

• In more general cases (e.g. data dependencies) it is very pessimistic.

ri Ci ri T j

• C j

j ∀ hp τi ( ) ∈

∑

+ = This is the interference wi from higher priority tasks.

Distributed Systems for Real-Time Applications: Analysis and Synthesis Petru Eles 75 May 2003

Event Triggered Systems

Response time calculation for data dependent tasks (Tindell ‘94): , where the interference is ri Ji wi Ci + + = wi wi J j Oij – + T j

• C

j j ∀ hp τi ( ) ∈

∑

=

Distributed Systems for Real-Time Applications: Analysis and Synthesis Petru Eles 76 May 2003

Event Triggered Systems

Response time calculation for data dependent tasks (Tindell ‘94): , where the interference wi is:

■

Main idea:

• Use offsets and jitter to model dependencies

■

The same idea can be used to model communication in distributed systems (the release jitter of the receiver task depends on the communication delay).

■

Further reduce pessimism in the case with conditional execution (Pop, Eles, Peng, CODES 2000). ri Ji wi Ci + + = wi wi J j Oij – + T j

• C

j j ∀ hp τi ( ) ∈

∑

=

Distributed Systems for Real-Time Applications: Analysis and Synthesis Petru Eles 77 May 2003

Static Communication: TTP Network

■ ■ ■

I/O Interface CPU RAM ROM ASIC TTP Controller Sensors&Actuators TTP round 1 N0 writes N1 writes left empty in this round N0 N1 Nn S0 S1 Sn S0 S1 Sn TTP round 2 TTP cycle

Distributed Systems for Real-Time Applications: Analysis and Synthesis Petru Eles 78 May 2003

Static Communication: TTP Network

■ ■ ■

I/O Interface CPU RAM ROM ASIC TTP Controller Sensors&Actuators N0 N1 Nn Time Action length (bits) t1 rd-frame 16 t2 wr-frame 32 t3 rd-frame 32

...

... ... tx wr-frame 16 Over a TTP cycle

Distributed Systems for Real-Time Applications: Analysis and Synthesis Petru Eles 79 May 2003

Dynamic Communication: CAN Network

■

Priority bus with collision avoidance mechanism: The node that transmits the highest priority frame wins the contention.

■ ■ ■

I/O Interface CPU RAM ROM ASIC

• Comm. Controller

Sensors&Actuators N0 N1 Nn Identifier CAN frame Data field CRC, etc.

Distributed Systems for Real-Time Applications: Analysis and Synthesis Petru Eles 80 May 2003

Scheduling of Distributed RT Systems

■

The classical approaches:

❚

TT tasks over static network. (Eles et al, IEEE TonVLSI 2000)

❚

ET tasks over dynamic network. (Tindell et al ‘95)

Distributed Systems for Real-Time Applications: Analysis and Synthesis Petru Eles 81 May 2003

Scheduling of Distributed RT Systems

■

The classical approaches:

❚

TT tasks over static network. (Eles et al, IEEE TonVLSI 2000)

❚

ET tasks over dynamic network. (Tindell et al ‘95)

■

A first step towards heterogeneous systems:

❚

TT tasks over dynamic network. (Dobrin et al, 2001)

❚

ET tasks over static networks. (Tindell ‘94; Pop, Eles, Peng, DATE 2000 & RT Systems Journal 2003)

Distributed Systems for Real-Time Applications: Analysis and Synthesis Petru Eles 82 May 2003

Optimization of Distributed RT Systems

☞ Once a scheduling/schedulability analysis approach is in place, several

• ptimization tasks can be performed.

Distributed Systems for Real-Time Applications: Analysis and Synthesis Petru Eles 83 May 2003

Optimization of Distributed RT Systems

☞ Once a scheduling/schedulability analysis approach is in place, several

• ptimization tasks can be performed.

System model

• Arch. Selection

System architecture Mapping Estimation Mapped and scheduled model Scheduling not OK not OK OK Analysis

Distributed Systems for Real-Time Applications: Analysis and Synthesis Petru Eles 84 May 2003

Optimization of Distributed RT Systems

☞ Once a scheduling/schedulability analysis approach is in place, several

• ptimization tasks can be performed.

■

Task mapping

■

Bus access optimization Pop, Eles, Peng, RT Systems Journal 2003 Pop, Eles, Peng, CODES ‘99 Pop, Eles, T. Pop, Peng, DAC ‘01

Distributed Systems for Real-Time Applications: Analysis and Synthesis Petru Eles 85 May 2003

Task Mapping

τ1 τ2 τ3 τ4 N1 N2 N3 4ms 12ms 8ms

• 12ms

4ms 8ms

• T = D = 50ms

N1 N2 N3 fast slow τ1 τ4 τ2 τ3 TTP round S1 S2 S3 S1 = S2 = S3 = 4ms

Distributed Systems for Real-Time Applications: Analysis and Synthesis Petru Eles 86 May 2003

m4,3

Task Mapping

τ1 τ2 τ3 τ4 N1 N2 N3 4ms 12ms 8ms

• 12ms

4ms 8ms

• T = D = 50ms

N1 N2 N3 τ1 τ4 τ2 m1,2 m1,4 τ3 m2,3 fast slow N1 N3 Bus S1 S2

0ms 4ms 52ms

τ4 τ1 τ2 τ3

m1,2 m1,4 m2,3 m4,3

S3 S1 S2 S3 S1 S2 S3 S1 S2 S3 S1 TTP round S1 S2 S3 S1 = S2 = S3 = 4ms

Distributed Systems for Real-Time Applications: Analysis and Synthesis Petru Eles 87 May 2003

Task Mapping

m4,3 τ1 τ2 τ3 τ4 N1 N2 N3 4ms 12ms 8ms

• 12ms

4ms 8ms

• T = D = 50ms

N1 N2 N3 τ1 τ4 τ2 m1,2 m1,4 τ3 m2,3 fast slow S1 = S2 = S3 = 4ms N1 N2 Bus

0ms 4ms 48ms

τ1 τ2 τ4 τ3

m1,2 m1,4m2,3 m4,3

S1 S2 S3 S1 S2 S3 S1 S2 S3 S1 S2 S3 S1 TTP round S1 S2 S3

Distributed Systems for Real-Time Applications: Analysis and Synthesis Petru Eles 88 May 2003

Bus Access Optimization

N1 N2 m4,3 τ1 τ4 τ2 m1,2 m1,4 τ3 m2,3 TTP round S2 S1

Distributed Systems for Real-Time Applications: Analysis and Synthesis Petru Eles 89 May 2003

Bus Access Optimization

N1 N2 m4,3 τ1 τ4 τ2 m1,2 m1,4 τ3 m2,3 N1 N2 Bus S1

26ms

τ4 τ1 τ2 τ3

m1,4 m2,3m4,3

S2 S1 S2 S1 TTP round S2 S1 S2

m1,2

Distributed Systems for Real-Time Applications: Analysis and Synthesis Petru Eles 90 May 2003

Bus Access Optimization

N1 N2 m4,3 τ1 τ4 τ2 m1,2 m1,4 τ3 m2,3 N1 N2 Bus S2 S1

24ms

τ4 τ1 τ2 τ3

m1,4 m2,3 m4,3

S2 S1 S2 S1 S2 S1 S2 TTP round S2 S1 S1

m1,2

τ3

Distributed Systems for Real-Time Applications: Analysis and Synthesis Petru Eles 91 May 2003

Bus Access Optimization

N1 N2 m4,3 τ1 τ4 τ2 m1,2 m1,4 τ3 m2,3 N1 N2 Bus S1 S2

22ms

τ4 τ1 τ2 τ3

m1,4 m2,3 m4,3

S1 S2 S1 S2 S1 S2 S1 TTP round S2 S1 S2

m1,2

τ3

Distributed Systems for Real-Time Applications: Analysis and Synthesis Petru Eles 92 May 2003

Outline

■

Embedded Real-Time System

■

System-level Design Flow

■

Distributed Embedded Real-Time Systems

❚

Application Model

❚

Heterogeneous Systems

❚

Time/Event Triggered Tasks

❚

Static/Dynamic Communication

❚

Analysis&Optimization

■

Single/Multi-cluster Heterogeneous Distributed Architectures

❚

Analysis&Optimization

■

Incremental Design Process

Distributed Systems for Real-Time Applications: Analysis and Synthesis Petru Eles 93 May 2003

The Traditional Approach

■ ■ ■ ■ ■ ■

One node One function

Distributed Systems for Real-Time Applications: Analysis and Synthesis Petru Eles 94 May 2003

The Traditional Approach

■ ■ ■ ■ ■ ■

One node One function

■

Purchase node&function and integrate into system

■

Sophistication grew quickly More then 100 nodes Resources have to be used more efficiently

Distributed Systems for Real-Time Applications: Analysis and Synthesis Petru Eles 95 May 2003

What Comes

■ ■ ■ ■ ■ ■

One node Several functions Several nodes One function

■

Reduce cost

■

Improve resource usage

■

Function close to sensor

Flexibility!

Distributed Systems for Real-Time Applications: Analysis and Synthesis Petru Eles 96 May 2003

What Comes

■ ■ ■ ■ ■ ■

One node Several functions Several nodes One function ☞ Needed:

■

Middleware software

■

New analysis

■

New system optimization

■

Reduce cost

■

Improve resource usage

■

Function close to sensor

Flexibility!

Distributed Systems for Real-Time Applications: Analysis and Synthesis Petru Eles 97 May 2003

Multi-cluster Heterogeneous Distributed Architecture

■ ■ ■ ■ ■ ■

That we have seen. Time triggered cluster:

❚

TT tasks

❚

Static communication Event triggered cluster:

❚

ET tasks

❚

Dynamic communication

Distributed Systems for Real-Time Applications: Analysis and Synthesis Petru Eles 98 May 2003

Multi-cluster Heterogeneous Distributed Architecture

■ ■ ■ ■ ■ ■

Analyse this!

Distributed Systems for Real-Time Applications: Analysis and Synthesis Petru Eles 99 May 2003

Single-cluster Heterogeneous Distributed Architecture

■ ■ ■

static phase N0 N1 Nn Bus cycle static phase static phase dynamic phase dynamic phase ET tasks TT tasks

Distributed Systems for Real-Time Applications: Analysis and Synthesis Petru Eles 100 May 2003

Single-cluster Heterogeneous Distributed Architecture

■ ■ ■

N0 N1 Nn Bus cycle ET tasks TT tasks S0 S1 S2 S3 S4 S5 Sn

Distributed Systems for Real-Time Applications: Analysis and Synthesis Petru Eles 101 May 2003

Analysis

ET tasks DYN messages Static Cyclic Scheduling Schedulability Analysis

Activity

Response

Time

Times TT tasks ST messages

Distributed Systems for Real-Time Applications: Analysis and Synthesis Petru Eles 102 May 2003

Analysis

ET tasks DYN messages Static Cyclic Scheduling Schedulability Analysis

Activity

Response

Time

Times TT tasks ST messages Offsets Constraints F i x p

• i

n t

Distributed Systems for Real-Time Applications: Analysis and Synthesis Petru Eles 103 May 2003

Analysis

Single -cluster heterogeneous:

❚

• T. Pop, Eles, Peng, CODES’02

❚

• T. Pop, Eles, Peng, ERTC’03

Multi -cluster heterogeneous:

❚

Pop, Eles, Peng, DATE’03

Distributed Systems for Real-Time Applications: Analysis and Synthesis Petru Eles 104 May 2003

Optimization

☞ Once the analysis approach is in place, several new, specific optimization tasks can be performed:

■

Task partitioning into TT, ET

■

Cluster mapping

■

Bus access optimization (static, dynamic phases)

■

Buffer minimisation

Distributed Systems for Real-Time Applications: Analysis and Synthesis Petru Eles 105 May 2003

Mapping & Task Partitioning

■ ■ ■

N0 N1 Nn ET tasks TT tasks τ1 τ3 τ6 τ7 τ4 τ2 τ5 τ8 τ10 τ12 τ13 τ9 τ11 τ14 τ16 τ17 τ15 τ19 τ18

?

Distributed Systems for Real-Time Applications: Analysis and Synthesis Petru Eles 106 May 2003

Mapping & Task Partitioning

■ ■ ■ ■ ■ ■

τ1 τ3 τ6 τ7 τ4 τ2 τ5 τ8 τ10 τ12 τ13 τ9 τ11 τ14 τ16 τ17 τ15 τ19 τ18

?

Distributed Systems for Real-Time Applications: Analysis and Synthesis Petru Eles 107 May 2003

Bus Access Optimization

N1 N2 Bus cycle S1 Dyn S2 m τ1 τ2 Dyn

Distributed Systems for Real-Time Applications: Analysis and Synthesis Petru Eles 108 May 2003

Bus Access Optimization

N1 N2 Bus cycle S1 Dyn S2 m τ1 τ2 Dyn N1 N2 Bus S1 τ1 τ2

m

S2 S1 S2 Dyn Dyn Dyn Dyn S1

Distributed Systems for Real-Time Applications: Analysis and Synthesis Petru Eles 109 May 2003

Bus Access Optimization

N1 N2 Bus cycle S2 Dyn S1 m τ1 τ2 Dyn N1 N2 Bus S2 τ1 τ2

m

S1 S2 S1 Dyn Dyn Dyn Dyn

Distributed Systems for Real-Time Applications: Analysis and Synthesis Petru Eles 110 May 2003

Bus Access Optimization

N1 N2 Bus cycle S2 S1 m τ1 τ2 Dyn N1 N2 Bus S2 τ1 τ2

m

S1 S2 S1 Dyn Dyn

Distributed Systems for Real-Time Applications: Analysis and Synthesis Petru Eles 111 May 2003

Optimization Loop

System model

• Arch. Selection

System architecture Mapping Estimation Mapped and scheduled model Scheduling not OK not OK OK Analysis

Multi-cluster heterogeneous:

❚

Pop, Eles, Peng, DATE’03

Distributed Systems for Real-Time Applications: Analysis and Synthesis Petru Eles 112 May 2003

Improved Schedulability by Optimization

60 75 100% 50% 90 25% 75% 120 Straight-forward solution After optimization

• No. of tasks

❚ 6 nodes (single-cluster) ❚ 60% average processor utilisation

Distributed Systems for Real-Time Applications: Analysis and Synthesis Petru Eles 113 May 2003

Outline

■

Embedded Real-Time System

■

System-level Design Flow

■

Distributed Embedded Real-Time Systems

❚

Application Model

❚

Heterogeneous Systems

❚

Time/Event Triggered Tasks

❚

Static/Dynamic Communication

❚

Analysis&Optimization

■

Single/Multi-cluster Heterogeneous Distributed Architectures

❚

Analysis&Optimization

■

Incremental Design Process

Distributed Systems for Real-Time Applications: Analysis and Synthesis Petru Eles 114 May 2003

Incremental Design Process

☞ In practice we almost never start from scratch!

■

Start from an already existing system running certain applications.

■

The design problem:

❚

Implement new functionality or/and upgrades to the existing ones (without adding resources, if possible).

Distributed Systems for Real-Time Applications: Analysis and Synthesis Petru Eles 115 May 2003

Incremental Design Process

☞ In practice we almost never start from scratch!

■

Start from an already existing system running a certain application

■

The design problem:

❚

Implement new functionality or/and upgrades to the existing ones (without adding resources, if possible).

■

The same problems have to be solved as discussed before and in addition:

❚

Produce as few as possible modifications to the running applications.

❚

The resulting system should be such that, later, it is easy to add new functionality.

Distributed Systems for Real-Time Applications: Analysis and Synthesis Petru Eles 116 May 2003

Incremental Design Process

Existing applications: ψ

Distributed Systems for Real-Time Applications: Analysis and Synthesis Petru Eles 117 May 2003

Incremental Design Process

Existing applications: Application to Version N Version N-1 ψ be added to the system: Γcurrent

Distributed Systems for Real-Time Applications: Analysis and Synthesis Petru Eles 118 May 2003

Incremental Design Process

Existing applications: Application to Possible future Version N Version N-1 Version N+1 ψ be added to the system: Γcurrent application to be added: Γfuture

Distributed Systems for Real-Time Applications: Analysis and Synthesis Petru Eles 119 May 2003

Incremental Design Process

Existing applications: Application to Possible future Version N Version N-1 Version N+1 ψ be added to the system: Γcurrent application to be added: Γfuture Implement Γcurrent so that:

• 1. constraints on Γcurrent satisfied
• 2. modifications of ψ minimized
• 3. possible to implement Γfuture

Distributed Systems for Real-Time Applications: Analysis and Synthesis Petru Eles 120 May 2003

Incremental Design Process

☞ The goal:

❚

Minimise modification related costs:

• Modify as few as possible from ψ.
• Allocate resources so that it will be easy to implement Γfuture.

■

Resources that have to be allocated in the right way:

❚

Processor utilisation

❚

Bus bandwidth

❚

Time slots on processors and buses

❚

Memory Pop, Eles, T. Pop, Peng, CODES ‘01 Pop, Eles, T. Pop, Peng, DAC ‘01

Distributed Systems for Real-Time Applications: Analysis and Synthesis Petru Eles 121 May 2003

The Future Application

What do we know?

■

About the future application:

❚

Probability distributions regarding the need for

• Processor
• Bus bandwidth
• Memory

Distributed Systems for Real-Time Applications: Analysis and Synthesis Petru Eles 122 May 2003

The Existing Applications

What do we know?

■

About the existing applications:

❚

The application graph captures

• modification costs of applications (e.g. COCOMO, Boehm et al, 2000);
• dependencies: modifying an application can trigger the need to

modify other applications.

Distributed Systems for Real-Time Applications: Analysis and Synthesis Petru Eles 123 May 2003

The Existing Applications

Total modification cost of a subset of applications Ω ∈ ψ. R Ω ( ) RΓi

Γi Ω ∈

∑

= Γ1 Γ2 Γ3 Γ4 Γ5 Γ6 Γ7 Γ8 Γ9 Γ10 150 70 50 70 50 20 frozen If Γ4 modified then Γ7 to be modified. modif. cost RΓ1

Distributed Systems for Real-Time Applications: Analysis and Synthesis Petru Eles 124 May 2003

Conclusions

■

System-level design; the early design steps.

■

Heterogeneous distributed real-time systems: How to guarantee timing constraints?

■

It’s not sufficient to analyse! Help the designer to efficiently implement. Both functionality and communication!

■

You don’t start from scratch and there always comes another version.