Digital Hardware Design Why is it still so hard? Philipp Wagner - - PowerPoint PPT Presentation

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Digital Hardware Design Why is it still so hard? Philipp Wagner - - PowerPoint PPT Presentation

May 27, 2023 217 likes •704 views

Digital Hardware Design Why is it still so hard? Philipp Wagner The story of Ton Lear FOSDEM 2016 Digital Hardware Design Why is it still so hard? The story of Not Real Ton Lear FOSDEM 2016 Digital Hardware Design Why is it still

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Digital Hardware Design Why is it still so hard?

Philipp Wagner

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FOSDEM 2016 Digital Hardware Design – Why is it still so hard?

The story of Ton Lear

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FOSDEM 2016 Digital Hardware Design – Why is it still so hard?

The story of Ton Lear Not Real

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FOSDEM 2016 Digital Hardware Design – Why is it still so hard?

Digital Hardware Design Free and Open Source Silicon (FOSSi) maker

  • pen (source) hardware

What's the difference?

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FOSDEM 2016 Digital Hardware Design – Why is it still so hard?

FOSSi Reality Check 1 The Simulation Check

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FOSDEM 2016 Digital Hardware Design – Why is it still so hard?

Simulation: Required Ingredients

  • code to simulate
  • a simulator
  • testing
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FOSDEM 2016 Digital Hardware Design – Why is it still so hard?

Write your code

  • Choose from the incumbents

– Verilog/SystemVerilog – VHDL

  • or one of the new contenders

– Bluespec SystemVerilog – Chisel (UC Berkely) – MyHDL

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FOSDEM 2016 Digital Hardware Design – Why is it still so hard?

Simulation

  • The “big 3” commercial simulators

– Incisive Enterprise Simulator/ NCSim (Cadence) – ModelSim (Mentor) – VCS (Synopsys)

  • FOSS solutions

– Icarus Verilog – GHDL – Verilator

  • Add a good waveform viewer

– gtkview

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FOSDEM 2016 Digital Hardware Design – Why is it still so hard?

Testing & Verifjcation

  • cocotb: Python-based test
  • vunit: VHDL unit testing
  • Open Source VHDL Verifjcation Methodology

(OS-VVM)

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FOSDEM 2016 Digital Hardware Design – Why is it still so hard?

“The Simulation Check”: Results

  • Hobbyist-Accessibility-Score: 4/5
  • FOSS score: 4/5
  • Fun score: 2/5
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FOSDEM 2016 Digital Hardware Design – Why is it still so hard?

FOSSi Reality Check 2 The FPGA Check

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FOSDEM 2016 Digital Hardware Design – Why is it still so hard?

FPGA Design: Required Ingredients

  • code to simulate
  • a simulator
  • testing
  • a synthesis tool
  • an implementation tool
  • an FPGA board
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FOSDEM 2016 Digital Hardware Design – Why is it still so hard?

FPGA Synthesis

  • Commercial

– Synopsys Synplify – vendor tools (Xilinx, Altera, …)

  • free alternatives

– Verilog-to-Routing (VTR) – Yosys

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FOSDEM 2016 Digital Hardware Design – Why is it still so hard?

FPGA Implementation

  • Mostly vendor tools

– Xilinx ISE/Vivado, Altera Quartus, …

  • free alternatives

– IceStorm for Lattice iCE40

watch Clifford's presentation in the EDA Devroom today at 14:00

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FOSDEM 2016 Digital Hardware Design – Why is it still so hard?

FPGA Boards: student (< 100 $)

DE0-Nano $79 22,320 cells Artix-7 35T $99 33,280 cells iCEstick $20 1280 cells

All board pictures (c) by the manufacturers.

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FOSDEM 2016 Digital Hardware Design – Why is it still so hard?

FPGA Boards: amateur (~ 500 $)

Nexys 4 DDR ZTEX 2.1x Altera DE2-115

All board pictures (c) by the manufacturers.

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FOSDEM 2016 Digital Hardware Design – Why is it still so hard?

FPGA Board: pro (> 1000 $)

Xilinx KC705 Xilinx VC707

All board pictures (c) by the manufacturers.

Altera Cyclone V SoC Development Kit

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FOSDEM 2016 Digital Hardware Design – Why is it still so hard?

“The FPGA Check”: Results

  • Hobbyist-Accessibility-Score: 3/5
  • FOSS score: 2/5
  • Fun score: 4/5
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FOSDEM 2016 Digital Hardware Design – Why is it still so hard?

FOSSi Reality Check 3 The ASIC Check

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FOSDEM 2016 Digital Hardware Design – Why is it still so hard?

ASIC Production: Required Ingredients

  • code to simulate
  • a simulator
  • a synthesis tool
  • really good testing & verifjcation
  • a design kit
  • an implementation tool
  • money
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FOSDEM 2016 Digital Hardware Design – Why is it still so hard?

The Design Kit

  • standard cell libraries, design rules, electrical

parameters, ...

  • get it from the foundry
  • bad: requires pretty tough NDA
  • good: it's usually for free (again, as in beer)
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FOSDEM 2016 Digital Hardware Design – Why is it still so hard?

ASIC Implementation

  • Commercial options

– Synopsys Design Compiler – Cadence Encounter Toolset

  • FOSS options

– qfmow – Coriolis2

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FOSDEM 2016 Digital Hardware Design – Why is it still so hard?

Got Money?

[[user:]] via Wikimedia Commons, CC BY-SA

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FOSDEM 2016 Digital Hardware Design – Why is it still so hard?

Need Money

  • Multi-Project Wafer

– available from multiple vendors, e.g. Europractice – example

  • 50 pcs Globalfoundries 40 nm
  • 4 750 €/mm² (at least 9 mm² = 42 750 €) + packaging, etc.
  • up to 1500 KGates/mm²

– cheaper in older technologies (65nm + up)

  • eASIC

– pre-characterized ASICs “confjgured” with one custom

layer

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FOSDEM 2016 Digital Hardware Design – Why is it still so hard?

“The ASIC Check”: Results

  • Hobbyist-Accessibility-Score: 0.1/5
  • FOSS score: 1/5
  • Fun score: 1-5/5
  • Satisfaction score: 10/5

let's do it anyways?

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FOSDEM 2016 Digital Hardware Design – Why is it still so hard?

Don't celebrate alone.

Picture by WeI-chieh Chiu (fmickr), CC BY-SA

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FOSDEM 2016 Digital Hardware Design – Why is it still so hard?

Join the party!

The bachelor party. Signed Louis Wain. Oil on canvas, 29.5 x 60 cm (public domain, via Wikimedia Commons)

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FOSDEM 2016 Digital Hardware Design – Why is it still so hard?

FOSSi Reality Check 4 The Community Check

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FOSDEM 2016 Digital Hardware Design – Why is it still so hard?

Required ingredients

  • Let others participate
  • Build on existing work
  • Learn, teach and exchange ideas
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FOSDEM 2016 Digital Hardware Design – Why is it still so hard?

How to live together?

photo by Prskavka (Wikimedia Commons), public domain

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FOSDEM 2016 Digital Hardware Design – Why is it still so hard?

Let others participate, part 1: choose a license

  • Permissive
  • Weak Copyleft
  • Strong Copyleft
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FOSDEM 2016 Digital Hardware Design – Why is it still so hard?

Licensing: Permissive

  • without patent clause

– MIT and BSD widely used – example project: RISC V

  • with patent clause

– new: SolderPad License by Andrew Katz

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FOSDEM 2016 Digital Hardware Design – Why is it still so hard?

Licensing: Weak Copyleft

  • File-based copyleft

– OHDL: Julius Baxter for mor1kx, based on MPLv2

  • library copyleft

– LGPL

  • commonly used on opencores.org
  • what's “linking” in a hardware context?
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FOSDEM 2016 Digital Hardware Design – Why is it still so hard?

Licensing: Strong Copyleft

  • GPL

– GPLv3 uses “hardware-friendly” language

  • lesson learned from open sourcing SPARC

– example user: Gaisler LEON3 (GPLv2+) – implications not fully understood

  • ASIC (design kit)?
  • FPGA (built-in primitives)?
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FOSDEM 2016 Digital Hardware Design – Why is it still so hard?

OpenCores.org

photo by Andre Glechikoff (Flickr), CC BY-SA

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FOSDEM 2016 Digital Hardware Design – Why is it still so hard?

Community hub needed

  • publish your work
  • fjnd code to re-use
  • learn, teach, inspire
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FOSDEM 2016 Digital Hardware Design – Why is it still so hard?

Introducing LibreCores

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FOSDEM 2016 Digital Hardware Design – Why is it still so hard?

LibreCores Goals

  • Documentation

– How to get started? – Best practices – Success stories

  • News & Discussion

– Planet LibreCores

  • Project repository

– a directory of FOSSi projects – with quality indicators

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FOSDEM 2016 Digital Hardware Design – Why is it still so hard?

LibreCores: Where are we today?

  • Documentation

– How to get started? – Best practices – Success stories

  • News & Discussion

– Planet LibreCores

  • Project repository

– a directory of FOSSi projects – with quality indicators

First content online as of today

  • nline!

coming soon

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FOSDEM 2016 Digital Hardware Design – Why is it still so hard?

Who's behind all that?

  • OpenRISC community
  • Group formed ~2 years ago
  • First plans presented at ORCONF

2015 at CERN

  • since end of 2015: FOSSi Foundation,

CiC (UK) to provide shared legal entity

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FOSDEM 2016 Digital Hardware Design – Why is it still so hard?

So: Why is it still so hard?

  • you can do your own simulated and FPGA design

today!

  • producing ASICs will remain a challenge

But mostly: It's hard because information is hard to fjnd. LibreCores is ready to change that. Join us!

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FOSDEM 2016 Digital Hardware Design – Why is it still so hard?

Oh, just one Oh, just one more thing more thing

Peter Falk (by Sten), photo by Emanuele (fmickr), CC BY-SA

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TheOpenCorps!

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TheOpenCorps: Goals

⚫ Provide status indications for HW projects

  • Does it build?
  • Does it have sims / do they pass?
  • Resource utilisation and frequency

⚫ Improve quality of Open Source HW ⚫ Encourage re-use in Open Source HW ⚫ Free access to proprietary tools

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TheOpenCorps: Flow

⚫ Code hosted on Github ⚫ Describe build using .opencorps.yml ⚫ Develop! ⚫ For each commit:

  • Simulation regression
  • Synthesis on multiple platforms

⚫ Report status

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@TheOpenCorps

http://potential.ventures

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me

Philipp Wagner

mail@philipp-wagner.com www.philipp-wagner.com

let's talk!

FOSSi Foundation

discussion@fossi-foundation.org www.fossi-foundation.org #fossi on freenode

You can freely remix this presentation under the terms of the Creative Commons BY-SA 4.0 license.