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DiaSys: On-Chip Trace Analysis for Multi-Processor System-on-Chip Philipp Wagner, Thomas Wild, and Andreas Herkersdorf Technical University of Munich Department of Electrical and Computer Engineering Institute for Integrated Systems April 6,

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Technical University of Munich Department of Electrical and Computer Engineering Institute for Integrated Systems

DiaSys: On-Chip Trace Analysis for Multi-Processor System-on-Chip

April 6, 2016 @ ARCS 2016 Philipp Wagner, Thomas Wild, and Andreas Herkersdorf

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DiaSys | ARCS 2016 | Philipp Wagner 2

Software Debugging on a SoC

int main() { do(); something(); awesome(); but(); with(); bug:(; }

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Run-control debugging tracing

vs.

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Tracing Today

  • ARM CoreSight
  • NEXUS 5001
  • Infineon MCDS
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Future Proof?

Data from ITRS roadmap, 2013 edition.

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DiaSys: On-Chip Trace Analysis

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DiaSys: Event-Based Diagnosis

Event Generators

Functional SoC Components

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  • Event Type
  • uniquely identify the type of the event
  • Timestamp
  • Ordering
  • Correlation
  • Event Data
  • data associated with the event
  • usually synchronous with the event

Events

The Information Container

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  • bserve the functional system
  • (in general) configurable
  • triggers
  • event data (“payload”)
  • configuration and NoC interface conforming to a common interface
  • “synchronous island”

Event Generators

… generate events

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  • Triggers
  • PC (+ special cases)
  • event data (sync)
  • register values
  • stack arguments

Core Event Generator

Event Generator for CPUs

<<PC EVENT>> ts: 123456789 r3: 0x27 r4: 0x42 $SP+1: 0x72 timestamp event data event type

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DiaSys: Event-Based Diagnosis

Event Generators Processing Nodes

Functional SoC Components

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  • Less data, more information
  • Combine, filter, average, …

Processing Nodes

... transform events

Processing Node Data Information

Meaning

input event(s)

  • utput event(s)
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  • full-featured 32 bit RISC ISA with FPU
  • low overhead run-to-completion processing
  • interrupt-free hardware scheduler
  • I/O offloading

Diagnosis Processor

A Programmable Processing Node

Diagnosis NoC Event Ready Queue Event Output Queue Diagnosis NoC Diagnosis Script

OpenRISC Processor

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DiaSys: Architecture View

Event Generators generate Processing Nodes transform Event Sinks consume

Functional SoC Components

Developer Automation

Photo: herval on flickr, CC BY 2.0 Photo: Mattes on Wikimedia Commons, public domain

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Prototype Implementation: System View

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Resource Usage

Results for a ZTEX 1.15d board with a Xilinx Spartan-6 XC6SLX150 FPGA. Synthesis results by Synplify Premier.

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Usage Example

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  • Setup: Example running on one 25 MHz CPU with IPC = 0.2
  • Traditional tracing (CoreSight ETM, NEXUS 5001 Class 3)

(numbers scaled to our prototype implementation)

  • Full system trace (compressed to 2 bit/instruction)
  • data trace of writes to size (uncompressed)

Usage Example

CPU tracing module Host

10 Mbit/s

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Usage Example

CPU EG Diagnosis Processor Host write_to_buf was called ts = 12345 size = 100 size is >= 100 ts = 12345

4.3 Mbit/s 0.029 Mbit/s

  • ne event if write_to_buf is called (event packet size: 12 byte);

every 100th CPU event generates an off-chip event (event packet size: 8 byte)

configuration

Generate an event if write_to_buf is called Forward event if size is >=100

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We propose:

  • Use self-contained trace events
  • to enable on-chip trace processing
  • to overcome the trace off-chip bottleneck.

Outlook

  • System dimensioning for specific bug types
  • Knowledge formulation
  • Adapt knowledge to specific system instance

Summary

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Thank you! Questions?

Author contact Philipp Wagner Institute for Integrated Systems, Technical University of Munich

  • Arcisstr. 21, 80333 München, Germany

philipp.wagner@tum.de Paper reference

  • P. Wagner, T. Wild, and A. Herkersdorf, “DiaSys: On-Chip Trace Analysis for Multi-

processor System-on-Chip,” in Architecture of Computing Systems - ARCS 2016. Springer International Publishing, 2016, pp. 197–209. Acknowledgements This work was funded by the Bayerisches Staatsministerium für Wirtschaft und Medien, Energie und Technologie (StMWi) as part of the project “SoC Doctor,” and by the German Research Foundation (DFG) as part of the Transregional Collaborative Research Centre “Invasive Computing” (SFB/TR 89).

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Backup Slides

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Implementation: Diagnosis Processor