DESIGN OF LOW POWER VOLTAGE REGULATOR FOR RFID APPLICATIONS Josip - - PDF document
10.12.2015. UNIVERSITY OF ZAGREB FACULTY OF ELECTRICAL ENGINEERING AND COMPUTING DESIGN OF LOW POWER VOLTAGE REGULATOR FOR RFID APPLICATIONS Josip Mikulic Niko Bako Adrijan Baric MIDEM 2015, Bled Overview Introduction Voltage
FACULTY OF ELECTRICAL ENGINEERING AND COMPUTING
♦ Introduction ♦ Voltage Regulator Design ♦ Post-Layout Simulation Results ♦ Experimental Results ♦ Performance Comparison ♦ Conclusion MIDEM 2015, Bled 2 of 19
♦ Industry oriented to full on-chip solutions
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Profit and production complexity ♦ Design of the voltage regulators affected
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Cost production limits chip area
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Low-power
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Scalability to low voltages
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Conventional solutions no longer usable
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Fully compensated solutions take advantage ♦ Topic of this work is the design of voltage regulator which will fulfill the
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♦ Conventional linear regulator topology
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Pass device controled by the error amp
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Stability ensured with large output capacitor
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Area consuming (CL) ♦ Fully compensated linear regulator
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Miller compensation network included
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CL no longer important for stability
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Area efficient
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Convinient for fully integrated solutions
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Topology Overview
♦ RNMC (Reverse Nested Miller Compensation) error amplifier
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1st stage – differential amplifier
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2nd stage – common source
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3rd stage – pass device
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VF – direct implementation
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RNMC topology
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Suitable for driving large capacitive loads with low power
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VF in a feedback branch
♦ Feedback network ♦ Decoupling capacitor MIDEM 2015, Bled 5 of 19
Proposed Topology for the LDO Voltage Regulator
♦ DC gain
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♦ Dominant pole
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♦ GBW
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♦ ULGF
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♦ Negative Zero
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Open-Loop Transfer Function Analysis
2 2 1 1
r g r g A
m m V
− =
( )
1 2 2 1 1
1 r r g C
m C p
⋅ = ω
1 1 1 C m p V GBW
C g A = ⋅ = ω ω
GBW ULG
FB ω ω ⋅ =
2 1 2 fb fb fb
r r r FB + =
1 C mVF z
C g = ω
♦ Nondominant poles (assuming real)
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♦ Nondominant complex poles
2 1 3 2 C C L m p
C C C g ⋅ = ω
2 1 1 2 3 m C mVF C m mVF p
g C g C g g + = ω − + ± + = 1 1 4 1 1 2
2 2 2 2 1 3 2 1 2 3 , 2 m C L mVF m C m mVF m C m p
g C C g g C g j g g C g ω
♦ LDO voltage regulator designed in 0.18 um CMOS technology
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Biasing network and power enabling circuitry not shown
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1st stage – differential amplifier
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2nd stage – common source
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3rd stage – voltage follower
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Low threshold nMOS
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LDO feature
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500 µA <
RNMC topology
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VF in the feedback branch <
Voltage reference
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Feedback network
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Diode connected transistors
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Factor 1/3 <
Decoupling capacitor
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100 pF
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LDO Voltage Regulator Implementation (I)
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LDO Voltage Regulator Implementation (II)
Transistor Size (W/L) IQ M1a, M1b 1.2µm/1.8µm 0.25 µA M2 0.96µm/0.54µm 1 µA M3a 200µm/0.4µm 1.8 µA MVF 0.4µm/1.8µm 0.375 µA M2a, M2b 0.96µm/3.6µm 0.25 µA Md1, Md2, Md3 5.4µm/0.9µm 0.4 µA Mgp1 1.2µm/1.2µm 0.5 µA Mgp2 2.4µm/1.2µm 1 µA Mgn1 0.96µm/3.6µm 0.375 µA Mgn2 0.96µm/5.4µm 1.4 µA Capacitor Value CC1 1.8 pF CC2 0.18 pF CL 100 pF
♦ Nominal output voltage
♦ Nominal quiescent
♦ Layout of the designed voltage regulator
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Area : 0.065×0.085 mm2
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0.0055 mm2 <
Output capacitor CL not shown
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0.0129 mm2
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LDO Voltage Regulator Implementation (III)
♦ Simulated loop gain with
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IL: 0 to 500 µA (log steps)
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VDD = 1.6 V
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GBW = 100 kHz
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PM > 75 deg ♦ Poles and zeros
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Dominant pole: 0.05 kHz
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Nondominant complex poles
=
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Negative zero: 500 kHz MIDEM 2015, Bled 10 of 19
Loop Gain AC Response
♦ Simulated PSRR with the load current IL as a parameter
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IL: 0 to 500 µA (log steps)
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VDD = 1.8 V ♦ Low frequencies
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♦ Intermediate frequencies
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Worse for larger load currents
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Influenced by the output resistance of the pass device ♦ High frequencies
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Converges to the ratio of CL and CDS of the pass device MIDEM 2015, Bled 11 of 19
Power Supply Rejection Ratio
♦ Simulated DC response of the output voltage VOUT to the supply
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VDD changing from 1.4 V to 1.8 V
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IL = 500 µA ♦ Line regulation
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LiR = 1.25 mV/V MIDEM 2015, Bled 12 of 19
Line Regulation
MAX L I DD OUT
V V LiR
,
∆ ∆ =
♦ Simulated DC response of the output voltage VOUT to the load
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IL changing from 0 to 500 µA
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Room temperature
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Three voltages ♦ Load regulation
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LoR = 1.08 mV/mA for VDD = 1.6 V at 500 µA MIDEM 2015, Bled 13 of 19
Load Regulation
L OUT
I V LoR ∆ ∆ =
♦ Simulated transient response of the output voltage VOUT to the step
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IL changing from 0 to 500 µA
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Rise/fall time of tr/f = 1 µs <
VDD = 1.6 V
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Settling time: 6 µs MIDEM 2015, Bled 14 of 19
Transient Simulations
♦ Chip fabricated in UMC 0.18 um
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Microphotograph and measurement PCB visible in the figures ♦ Results:
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VOUT = 1.49 V
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35 mV higher than nominal <
ΔV = 60 mV
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IQ = 4.2 µA
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Including the voltage reference and biasing circuitry <
LiR = 3.5 mV/V
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LoR = 2.4 mV/mA at 500 µA
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PSRR: -49 dB at DC and -16 dB at 1MHz MIDEM 2015, Bled 15 of 19
VDD IBIAS VOUT GND
♦ Measured transient response of the output voltage VOUT to the step
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IL changing from 0 to 500 µA
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rise/fall time of tr/f = 100 ns <
VDD = 1.6 V
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Simulation results for the comparison ♦ Comparison
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Very good correspondence between the simulations and measurements MIDEM 2015, Bled 16 of 19
Transient Measurement
♦ Comparison with other
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Good static and dynamic behaviour for the invested power
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LDO feature
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Fully compensated
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Suitable for full on-chip solutions ♦ References:
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[5] L. Lijun, K.D. Gannes, K. Fricke, S. Senjuti, and R. Sobot, „Low–power CMOS voltage regulator architecture for implantable RF circuits,“ in RFID Technology (EURASIP RFID), 2012 Fourth International EURASIP Workshop on, pp. 99-106, 28-27 Sep. 2012.
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[6] J. Guo and K.N. Leung, „A CMOS voltage regulator for passive RFID tags ICs,“ International Journal of Circuit Theory and Application, vol. 40, no. 4, pp. 329-340, April 2012.
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[7] C.C. Liu. Chia-Chin, C. Chen „An ultra-low power voltage regulator for RFID application,“ in Circuits and Systems (MWSCAS), IEEE 56th International Midwest Symposium on, p.p. 780-783, 4-7 Aug. 2013.
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[5] [6] [7] This work Technology 0.13µm 0.18µm 65nm 0.18µm Chip area (mm2) NA 0.2236 NA 0.0184 Input voltage (V) >1.4 1.6 to 2 1.1 to 2.5 1.55 to 1.8 Nominal output voltage (V) 1 1.45 1.013 1.455 Referent voltage (V) 0.462 0.505 0.5078 0.485 Supply capability (µA) 4000 50 50 500 Quiescent current (µA) 11.6 0.7 0.064 3.7 (4.2) Load regulation (mV/mA) 0.29 @4mA 400 @50µA 130 @50µA 1.08 (2.4) @500µA Line regulation (mV/V) 3.1 22 4.06 1.25 (3.5) PSRR @DC PSRR @1MHz
NA NA
Settling time (µs) 7.9 20 NA 6 Load capacitance (pF) 50 1200 NA 100 Compensated YES NO NO YES
♦ Topology based on RNMC, suitable for low-power full on-chip voltage
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The topology was proposed based on analytic calculations ♦ LDO voltage regulator is designed by using the proposed topology
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Circuit is implemented in 0.18 um technology
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Layout was drawn
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Post-layout static and dynamic simulations are performed ♦ The designed regulator is fabricated in UMC 0.18 CMOS process
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Performed silicon measurements show high correspondence with the simulations MIDEM 2015, Bled 18 of 19
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