Design and Development of a CPU Scheduler Manuel Simulator for - - PowerPoint PPT Presentation

▶
design and development of a cpu scheduler
SMART_READER_LITE
LIVE PREVIEW

Design and Development of a CPU Scheduler Manuel Simulator for - - PowerPoint PPT Presentation

Oct 24, 2023 196 likes •793 views

1/22 Design and Development of a CPU Scheduler Simulator for Educational Purposes Using SDL Design and Development of a CPU Scheduler Manuel Simulator for Educational Purposes Using SDL Rodr guez- Cayetano Summary CPU Manuel

slide-1
SLIDE 1

1/22

Design and Development

  • f a CPU

Scheduler Simulator for Educational Purposes Using SDL Manuel Rodr´ ıguez- Cayetano Summary CPU Scheduling Overview The SDL CPU Scheduler Simulator The CPU Scheduler Simulator Graphical User Interface Conclusions and Further Work

Design and Development of a CPU Scheduler Simulator for Educational Purposes Using SDL

Manuel Rodr´ ıguez-Cayetano

Department of Signal Theory and Telematics Engineering University of Valladolid, ES-47011 Valladolid, Spain manuel.rodriguez@tel.uva.es

6th Workshop on System Analysis and Modelling Oslo, October 4th-5th 2010

slide-2
SLIDE 2

2/22

Design and Development

  • f a CPU

Scheduler Simulator for Educational Purposes Using SDL Manuel Rodr´ ıguez- Cayetano Summary CPU Scheduling Overview The SDL CPU Scheduler Simulator The CPU Scheduler Simulator Graphical User Interface Conclusions and Further Work

Summary

1

CPU Scheduling Overview CPU Scheduling Basics Related work

2

The SDL CPU Scheduler Simulator Requirements Behavior Overview Simulator structure Detailed Behavior

3

The CPU Scheduler Simulator Graphical User Interface

4

Conclusions and Further Work

slide-3
SLIDE 3

2/22

Design and Development

  • f a CPU

Scheduler Simulator for Educational Purposes Using SDL Manuel Rodr´ ıguez- Cayetano Summary CPU Scheduling Overview The SDL CPU Scheduler Simulator The CPU Scheduler Simulator Graphical User Interface Conclusions and Further Work

Summary

1

CPU Scheduling Overview CPU Scheduling Basics Related work

2

The SDL CPU Scheduler Simulator Requirements Behavior Overview Simulator structure Detailed Behavior

3

The CPU Scheduler Simulator Graphical User Interface

4

Conclusions and Further Work

slide-4
SLIDE 4

2/22

Design and Development

  • f a CPU

Scheduler Simulator for Educational Purposes Using SDL Manuel Rodr´ ıguez- Cayetano Summary CPU Scheduling Overview The SDL CPU Scheduler Simulator The CPU Scheduler Simulator Graphical User Interface Conclusions and Further Work

Summary

1

CPU Scheduling Overview CPU Scheduling Basics Related work

2

The SDL CPU Scheduler Simulator Requirements Behavior Overview Simulator structure Detailed Behavior

3

The CPU Scheduler Simulator Graphical User Interface

4

Conclusions and Further Work

slide-5
SLIDE 5

2/22

Design and Development

  • f a CPU

Scheduler Simulator for Educational Purposes Using SDL Manuel Rodr´ ıguez- Cayetano Summary CPU Scheduling Overview The SDL CPU Scheduler Simulator The CPU Scheduler Simulator Graphical User Interface Conclusions and Further Work

Summary

1

CPU Scheduling Overview CPU Scheduling Basics Related work

2

The SDL CPU Scheduler Simulator Requirements Behavior Overview Simulator structure Detailed Behavior

3

The CPU Scheduler Simulator Graphical User Interface

4

Conclusions and Further Work

slide-6
SLIDE 6

2/22

Design and Development

  • f a CPU

Scheduler Simulator for Educational Purposes Using SDL Manuel Rodr´ ıguez- Cayetano Summary CPU Scheduling Overview The SDL CPU Scheduler Simulator The CPU Scheduler Simulator Graphical User Interface Conclusions and Further Work

Summary

1

CPU Scheduling Overview CPU Scheduling Basics Related work

2

The SDL CPU Scheduler Simulator Requirements Behavior Overview Simulator structure Detailed Behavior

3

The CPU Scheduler Simulator Graphical User Interface

4

Conclusions and Further Work

slide-7
SLIDE 7

2/22

Design and Development

  • f a CPU

Scheduler Simulator for Educational Purposes Using SDL Manuel Rodr´ ıguez- Cayetano Summary CPU Scheduling Overview The SDL CPU Scheduler Simulator The CPU Scheduler Simulator Graphical User Interface Conclusions and Further Work

Summary

1

CPU Scheduling Overview CPU Scheduling Basics Related work

2

The SDL CPU Scheduler Simulator Requirements Behavior Overview Simulator structure Detailed Behavior

3

The CPU Scheduler Simulator Graphical User Interface

4

Conclusions and Further Work

slide-8
SLIDE 8

2/22

Design and Development

  • f a CPU

Scheduler Simulator for Educational Purposes Using SDL Manuel Rodr´ ıguez- Cayetano Summary CPU Scheduling Overview The SDL CPU Scheduler Simulator The CPU Scheduler Simulator Graphical User Interface Conclusions and Further Work

Summary

1

CPU Scheduling Overview CPU Scheduling Basics Related work

2

The SDL CPU Scheduler Simulator Requirements Behavior Overview Simulator structure Detailed Behavior

3

The CPU Scheduler Simulator Graphical User Interface

4

Conclusions and Further Work

slide-9
SLIDE 9

2/22

Design and Development

  • f a CPU

Scheduler Simulator for Educational Purposes Using SDL Manuel Rodr´ ıguez- Cayetano Summary CPU Scheduling Overview The SDL CPU Scheduler Simulator The CPU Scheduler Simulator Graphical User Interface Conclusions and Further Work

Summary

1

CPU Scheduling Overview CPU Scheduling Basics Related work

2

The SDL CPU Scheduler Simulator Requirements Behavior Overview Simulator structure Detailed Behavior

3

The CPU Scheduler Simulator Graphical User Interface

4

Conclusions and Further Work

slide-10
SLIDE 10

2/22

Design and Development

  • f a CPU

Scheduler Simulator for Educational Purposes Using SDL Manuel Rodr´ ıguez- Cayetano Summary CPU Scheduling Overview The SDL CPU Scheduler Simulator The CPU Scheduler Simulator Graphical User Interface Conclusions and Further Work

Summary

1

CPU Scheduling Overview CPU Scheduling Basics Related work

2

The SDL CPU Scheduler Simulator Requirements Behavior Overview Simulator structure Detailed Behavior

3

The CPU Scheduler Simulator Graphical User Interface

4

Conclusions and Further Work

slide-11
SLIDE 11

2/22

Design and Development

  • f a CPU

Scheduler Simulator for Educational Purposes Using SDL Manuel Rodr´ ıguez- Cayetano Summary CPU Scheduling Overview The SDL CPU Scheduler Simulator The CPU Scheduler Simulator Graphical User Interface Conclusions and Further Work

Summary

1

CPU Scheduling Overview CPU Scheduling Basics Related work

2

The SDL CPU Scheduler Simulator Requirements Behavior Overview Simulator structure Detailed Behavior

3

The CPU Scheduler Simulator Graphical User Interface

4

Conclusions and Further Work

slide-12
SLIDE 12

3/22

Design and Development

  • f a CPU

Scheduler Simulator for Educational Purposes Using SDL Manuel Rodr´ ıguez- Cayetano Summary CPU Scheduling Overview

CPU Scheduling Basics Related work

The SDL CPU Scheduler Simulator The CPU Scheduler Simulator Graphical User Interface Conclusions and Further Work

CPU Scheduling Basics (I)

CPU scheduling: deciding which of the ready processes is to be allocated the CPU Different selection criteria ⇒ different scheduling algorithms Two types of scheduling algorithms:

  • ne queue algorithms: appropriate when all the processes

belong to the same class (same scheduling requirements) multilevel queue algorithms: appropriate for processes belonging to several classes (different scheduling requirements)

Every algorithm may favor one class of process over another due its properties:

performance evaluation parameters (throughput, turnaround time, waiting time, . . . ) are used for comparing CPU scheduling algorithms

slide-13
SLIDE 13

3/22

Design and Development

  • f a CPU

Scheduler Simulator for Educational Purposes Using SDL Manuel Rodr´ ıguez- Cayetano Summary CPU Scheduling Overview

CPU Scheduling Basics Related work

The SDL CPU Scheduler Simulator The CPU Scheduler Simulator Graphical User Interface Conclusions and Further Work

CPU Scheduling Basics (I)

CPU scheduling: deciding which of the ready processes is to be allocated the CPU Different selection criteria ⇒ different scheduling algorithms Two types of scheduling algorithms:

  • ne queue algorithms: appropriate when all the processes

belong to the same class (same scheduling requirements) multilevel queue algorithms: appropriate for processes belonging to several classes (different scheduling requirements)

Every algorithm may favor one class of process over another due its properties:

performance evaluation parameters (throughput, turnaround time, waiting time, . . . ) are used for comparing CPU scheduling algorithms

slide-14
SLIDE 14

3/22

Design and Development

  • f a CPU

Scheduler Simulator for Educational Purposes Using SDL Manuel Rodr´ ıguez- Cayetano Summary CPU Scheduling Overview

CPU Scheduling Basics Related work

The SDL CPU Scheduler Simulator The CPU Scheduler Simulator Graphical User Interface Conclusions and Further Work

CPU Scheduling Basics (I)

CPU scheduling: deciding which of the ready processes is to be allocated the CPU Different selection criteria ⇒ different scheduling algorithms Two types of scheduling algorithms:

  • ne queue algorithms: appropriate when all the processes

belong to the same class (same scheduling requirements) multilevel queue algorithms: appropriate for processes belonging to several classes (different scheduling requirements)

Every algorithm may favor one class of process over another due its properties:

performance evaluation parameters (throughput, turnaround time, waiting time, . . . ) are used for comparing CPU scheduling algorithms

slide-15
SLIDE 15

3/22

Design and Development

  • f a CPU

Scheduler Simulator for Educational Purposes Using SDL Manuel Rodr´ ıguez- Cayetano Summary CPU Scheduling Overview

CPU Scheduling Basics Related work

The SDL CPU Scheduler Simulator The CPU Scheduler Simulator Graphical User Interface Conclusions and Further Work

CPU Scheduling Basics (I)

CPU scheduling: deciding which of the ready processes is to be allocated the CPU Different selection criteria ⇒ different scheduling algorithms Two types of scheduling algorithms:

  • ne queue algorithms: appropriate when all the processes

belong to the same class (same scheduling requirements) multilevel queue algorithms: appropriate for processes belonging to several classes (different scheduling requirements)

Every algorithm may favor one class of process over another due its properties:

performance evaluation parameters (throughput, turnaround time, waiting time, . . . ) are used for comparing CPU scheduling algorithms

slide-16
SLIDE 16

4/22

Design and Development

  • f a CPU

Scheduler Simulator for Educational Purposes Using SDL Manuel Rodr´ ıguez- Cayetano Summary CPU Scheduling Overview

CPU Scheduling Basics Related work

The SDL CPU Scheduler Simulator The CPU Scheduler Simulator Graphical User Interface Conclusions and Further Work

CPU Scheduling Basics (II)

Selecting an algorithm appropriate for a process workload ⇒ evaluation of the algorithms based on values of the performance evaluation parameters

for example, select the algorithm that produces the least mean waiting time for a process workload

Several evaluation methods:

deterministic modeling: results only valid for the concrete (deterministic) workload used queuing models based: classes of algorithms and statistical distributions of process parameters limited, results not accurate simulation: can support deterministic and statistical based workloads, results can be more accurate than those

  • btained using queuing models
slide-17
SLIDE 17

4/22

Design and Development

  • f a CPU

Scheduler Simulator for Educational Purposes Using SDL Manuel Rodr´ ıguez- Cayetano Summary CPU Scheduling Overview

CPU Scheduling Basics Related work

The SDL CPU Scheduler Simulator The CPU Scheduler Simulator Graphical User Interface Conclusions and Further Work

CPU Scheduling Basics (II)

Selecting an algorithm appropriate for a process workload ⇒ evaluation of the algorithms based on values of the performance evaluation parameters

for example, select the algorithm that produces the least mean waiting time for a process workload

Several evaluation methods:

deterministic modeling: results only valid for the concrete (deterministic) workload used queuing models based: classes of algorithms and statistical distributions of process parameters limited, results not accurate simulation: can support deterministic and statistical based workloads, results can be more accurate than those

  • btained using queuing models
slide-18
SLIDE 18

5/22

Design and Development

  • f a CPU

Scheduler Simulator for Educational Purposes Using SDL Manuel Rodr´ ıguez- Cayetano Summary CPU Scheduling Overview

CPU Scheduling Basics Related work

The SDL CPU Scheduler Simulator The CPU Scheduler Simulator Graphical User Interface Conclusions and Further Work

CPU Scheduling Basics (III)

Simulation consist of programming a model of the computer system that behaves like the actual system (at least regarding CPU scheduling) ⇒ modeling:

arrival, ready and finished queues clock . . .

Design, coding and debugging of a simulator are usually a major task

appropriate specification techniques (like SDL) should be used instead of just coding

slide-19
SLIDE 19

5/22

Design and Development

  • f a CPU

Scheduler Simulator for Educational Purposes Using SDL Manuel Rodr´ ıguez- Cayetano Summary CPU Scheduling Overview

CPU Scheduling Basics Related work

The SDL CPU Scheduler Simulator The CPU Scheduler Simulator Graphical User Interface Conclusions and Further Work

CPU Scheduling Basics (III)

Simulation consist of programming a model of the computer system that behaves like the actual system (at least regarding CPU scheduling) ⇒ modeling:

arrival, ready and finished queues clock . . .

Design, coding and debugging of a simulator are usually a major task

appropriate specification techniques (like SDL) should be used instead of just coding

slide-20
SLIDE 20

6/22

Design and Development

  • f a CPU

Scheduler Simulator for Educational Purposes Using SDL Manuel Rodr´ ıguez- Cayetano Summary CPU Scheduling Overview

CPU Scheduling Basics Related work

The SDL CPU Scheduler Simulator The CPU Scheduler Simulator Graphical User Interface Conclusions and Further Work

Related work and motivation

Several CPU scheduling simulators have been previously developed: CPU Scheduling Simulator, CPU Scheduler Application, Process Scheduling Simulator, MOSS Scheduling Simulator . . . Main shortcomings of these simulators:

algorithms specific for real-time processes are not supported multilevel queue algorithms are not supported, only single-queue ones deterministic workloads (useful for testing special scenarios) not supported in some of them

These shortcomings have led to the development of a CPU scheduling simulator using SDL (sdlCPUSched)

slide-21
SLIDE 21

6/22

Design and Development

  • f a CPU

Scheduler Simulator for Educational Purposes Using SDL Manuel Rodr´ ıguez- Cayetano Summary CPU Scheduling Overview

CPU Scheduling Basics Related work

The SDL CPU Scheduler Simulator The CPU Scheduler Simulator Graphical User Interface Conclusions and Further Work

Related work and motivation

Several CPU scheduling simulators have been previously developed: CPU Scheduling Simulator, CPU Scheduler Application, Process Scheduling Simulator, MOSS Scheduling Simulator . . . Main shortcomings of these simulators:

algorithms specific for real-time processes are not supported multilevel queue algorithms are not supported, only single-queue ones deterministic workloads (useful for testing special scenarios) not supported in some of them

These shortcomings have led to the development of a CPU scheduling simulator using SDL (sdlCPUSched)

slide-22
SLIDE 22

6/22

Design and Development

  • f a CPU

Scheduler Simulator for Educational Purposes Using SDL Manuel Rodr´ ıguez- Cayetano Summary CPU Scheduling Overview

CPU Scheduling Basics Related work

The SDL CPU Scheduler Simulator The CPU Scheduler Simulator Graphical User Interface Conclusions and Further Work

Related work and motivation

Several CPU scheduling simulators have been previously developed: CPU Scheduling Simulator, CPU Scheduler Application, Process Scheduling Simulator, MOSS Scheduling Simulator . . . Main shortcomings of these simulators:

algorithms specific for real-time processes are not supported multilevel queue algorithms are not supported, only single-queue ones deterministic workloads (useful for testing special scenarios) not supported in some of them

These shortcomings have led to the development of a CPU scheduling simulator using SDL (sdlCPUSched)

slide-23
SLIDE 23

7/22

Design and Development

  • f a CPU

Scheduler Simulator for Educational Purposes Using SDL Manuel Rodr´ ıguez- Cayetano Summary CPU Scheduling Overview The SDL CPU Scheduler Simulator

Requirements Behavior Overview Simulator structure Detailed Behavior

The CPU Scheduler Simulator Graphical User Interface Conclusions and Further Work

sdlCPUSched: requirements and assumptions

Main requirements:

simulator for educational purposes, mainly used for behavior and performance analysis of CPU scheduling algorithms support for non real-time and real-time algorithms support for multilevel queue algorithms (number of queues, queue algorithm and queue priority can be configured)

Main assumptions (to simplify the development of the simulator):

all the processes characteristics are independent

  • nly one CPU burst and zero I/O bursts per process
slide-24
SLIDE 24

7/22

Design and Development

  • f a CPU

Scheduler Simulator for Educational Purposes Using SDL Manuel Rodr´ ıguez- Cayetano Summary CPU Scheduling Overview The SDL CPU Scheduler Simulator

Requirements Behavior Overview Simulator structure Detailed Behavior

The CPU Scheduler Simulator Graphical User Interface Conclusions and Further Work

sdlCPUSched: requirements and assumptions

Main requirements:

simulator for educational purposes, mainly used for behavior and performance analysis of CPU scheduling algorithms support for non real-time and real-time algorithms support for multilevel queue algorithms (number of queues, queue algorithm and queue priority can be configured)

Main assumptions (to simplify the development of the simulator):

all the processes characteristics are independent

  • nly one CPU burst and zero I/O bursts per process
slide-25
SLIDE 25

8/22

Design and Development

  • f a CPU

Scheduler Simulator for Educational Purposes Using SDL Manuel Rodr´ ıguez- Cayetano Summary CPU Scheduling Overview The SDL CPU Scheduler Simulator

Requirements Behavior Overview Simulator structure Detailed Behavior

The CPU Scheduler Simulator Graphical User Interface Conclusions and Further Work

sdlCPUSched: behavior overview

Signal-based communication between the simulator and its environment

interactions are mainly asynchronous (only synchronous during the phase of simulation configuration)

Input signals:

simulation configuration (algorithm simulated, process

  • parameters. . . )

simulation control (start, stop, pause. . . )

Output signals:

confirmation of simulation configuration notification of simulation events (if verbose mode is selected) values of per-process and global statistics

Scenarios of interactions between the simulator and its environment modeled by MSCs

main scenarios: algorithm configuration, process workload configuration and simulation execution

slide-26
SLIDE 26

8/22

Design and Development

  • f a CPU

Scheduler Simulator for Educational Purposes Using SDL Manuel Rodr´ ıguez- Cayetano Summary CPU Scheduling Overview The SDL CPU Scheduler Simulator

Requirements Behavior Overview Simulator structure Detailed Behavior

The CPU Scheduler Simulator Graphical User Interface Conclusions and Further Work

sdlCPUSched: behavior overview

Signal-based communication between the simulator and its environment

interactions are mainly asynchronous (only synchronous during the phase of simulation configuration)

Input signals:

simulation configuration (algorithm simulated, process

  • parameters. . . )

simulation control (start, stop, pause. . . )

Output signals:

confirmation of simulation configuration notification of simulation events (if verbose mode is selected) values of per-process and global statistics

Scenarios of interactions between the simulator and its environment modeled by MSCs

main scenarios: algorithm configuration, process workload configuration and simulation execution

slide-27
SLIDE 27

8/22

Design and Development

  • f a CPU

Scheduler Simulator for Educational Purposes Using SDL Manuel Rodr´ ıguez- Cayetano Summary CPU Scheduling Overview The SDL CPU Scheduler Simulator

Requirements Behavior Overview Simulator structure Detailed Behavior

The CPU Scheduler Simulator Graphical User Interface Conclusions and Further Work

sdlCPUSched: behavior overview

Signal-based communication between the simulator and its environment

interactions are mainly asynchronous (only synchronous during the phase of simulation configuration)

Input signals:

simulation configuration (algorithm simulated, process

  • parameters. . . )

simulation control (start, stop, pause. . . )

Output signals:

confirmation of simulation configuration notification of simulation events (if verbose mode is selected) values of per-process and global statistics

Scenarios of interactions between the simulator and its environment modeled by MSCs

main scenarios: algorithm configuration, process workload configuration and simulation execution

slide-28
SLIDE 28

8/22

Design and Development

  • f a CPU

Scheduler Simulator for Educational Purposes Using SDL Manuel Rodr´ ıguez- Cayetano Summary CPU Scheduling Overview The SDL CPU Scheduler Simulator

Requirements Behavior Overview Simulator structure Detailed Behavior

The CPU Scheduler Simulator Graphical User Interface Conclusions and Further Work

sdlCPUSched: behavior overview

Signal-based communication between the simulator and its environment

interactions are mainly asynchronous (only synchronous during the phase of simulation configuration)

Input signals:

simulation configuration (algorithm simulated, process

  • parameters. . . )

simulation control (start, stop, pause. . . )

Output signals:

confirmation of simulation configuration notification of simulation events (if verbose mode is selected) values of per-process and global statistics

Scenarios of interactions between the simulator and its environment modeled by MSCs

main scenarios: algorithm configuration, process workload configuration and simulation execution

slide-29
SLIDE 29

9/22

Design and Development

  • f a CPU

Scheduler Simulator for Educational Purposes Using SDL Manuel Rodr´ ıguez- Cayetano Summary CPU Scheduling Overview The SDL CPU Scheduler Simulator

Requirements Behavior Overview Simulator structure Detailed Behavior

The CPU Scheduler Simulator Graphical User Interface Conclusions and Further Work

sdlCPUSched: example of an scenario

CPUScheduler environment 1 1 loop <1, globalStatistics> 2 2 loop <1, numberOfProcessStatistics> 1 1 loop <1, numberOfProcesses> 1 1

  • pt

3 3 loop<0,numberOfListsModified> 2 2 loop <1,numberOfEvents> simulationReadyToStart

MSC CPUSchedulerOverview_running

globalStatistic (IP, port, statisticName, statisticMsg, value) simulationEnd (IP, port, clock) sendList (IP, port, clock, listyKind, list,listId) schedulerEnd_c (IP, port) sendList (IP, port, clock, listyKind, list, listId) processStatistic (IP, port, processId, processPeriodNum, statisticName, statisticMsg, value) printEvent (IP,port, clock, processId, processPeriodNum, enventType, msg)

slide-30
SLIDE 30

10/22

Design and Development

  • f a CPU

Scheduler Simulator for Educational Purposes Using SDL Manuel Rodr´ ıguez- Cayetano Summary CPU Scheduling Overview The SDL CPU Scheduler Simulator

Requirements Behavior Overview Simulator structure Detailed Behavior

The CPU Scheduler Simulator Graphical User Interface Conclusions and Further Work

Simulator structure: motivation issues

To keep independent intra-queue and inter-queue scheduling functions ⇒ two process types:

MasterSchedulerType for inter-queue scheduling, one instance SlaveSchedulerType for intra-queue scheduling, as many instances as ready queues

To minimize the amount of code not automatically generated from the SDL specification:

  • ne simulator program for all the users using the TCP

communication module included in the SDL tool

programming communication functions with the system environment is avoided no need to use extra coding in C for sending the port number of every instance of the user’s simulator program to its GUI (using files, running program parameters, . . . )

  • ne control process required to route signals of one user

to the corresponding scheduling processes

slide-31
SLIDE 31

10/22

Design and Development

  • f a CPU

Scheduler Simulator for Educational Purposes Using SDL Manuel Rodr´ ıguez- Cayetano Summary CPU Scheduling Overview The SDL CPU Scheduler Simulator

Requirements Behavior Overview Simulator structure Detailed Behavior

The CPU Scheduler Simulator Graphical User Interface Conclusions and Further Work

Simulator structure: motivation issues

To keep independent intra-queue and inter-queue scheduling functions ⇒ two process types:

MasterSchedulerType for inter-queue scheduling, one instance SlaveSchedulerType for intra-queue scheduling, as many instances as ready queues

To minimize the amount of code not automatically generated from the SDL specification:

  • ne simulator program for all the users using the TCP

communication module included in the SDL tool

programming communication functions with the system environment is avoided no need to use extra coding in C for sending the port number of every instance of the user’s simulator program to its GUI (using files, running program parameters, . . . )

  • ne control process required to route signals of one user

to the corresponding scheduling processes

slide-32
SLIDE 32

10/22

Design and Development

  • f a CPU

Scheduler Simulator for Educational Purposes Using SDL Manuel Rodr´ ıguez- Cayetano Summary CPU Scheduling Overview The SDL CPU Scheduler Simulator

Requirements Behavior Overview Simulator structure Detailed Behavior

The CPU Scheduler Simulator Graphical User Interface Conclusions and Further Work

Simulator structure: motivation issues

To keep independent intra-queue and inter-queue scheduling functions ⇒ two process types:

MasterSchedulerType for inter-queue scheduling, one instance SlaveSchedulerType for intra-queue scheduling, as many instances as ready queues

To minimize the amount of code not automatically generated from the SDL specification:

  • ne simulator program for all the users using the TCP

communication module included in the SDL tool

programming communication functions with the system environment is avoided no need to use extra coding in C for sending the port number of every instance of the user’s simulator program to its GUI (using files, running program parameters, . . . )

  • ne control process required to route signals of one user

to the corresponding scheduling processes

slide-33
SLIDE 33

10/22

Design and Development

  • f a CPU

Scheduler Simulator for Educational Purposes Using SDL Manuel Rodr´ ıguez- Cayetano Summary CPU Scheduling Overview The SDL CPU Scheduler Simulator

Requirements Behavior Overview Simulator structure Detailed Behavior

The CPU Scheduler Simulator Graphical User Interface Conclusions and Further Work

Simulator structure: motivation issues

To keep independent intra-queue and inter-queue scheduling functions ⇒ two process types:

MasterSchedulerType for inter-queue scheduling, one instance SlaveSchedulerType for intra-queue scheduling, as many instances as ready queues

To minimize the amount of code not automatically generated from the SDL specification:

  • ne simulator program for all the users using the TCP

communication module included in the SDL tool

programming communication functions with the system environment is avoided no need to use extra coding in C for sending the port number of every instance of the user’s simulator program to its GUI (using files, running program parameters, . . . )

  • ne control process required to route signals of one user

to the corresponding scheduling processes

slide-34
SLIDE 34

11/22

Design and Development

  • f a CPU

Scheduler Simulator for Educational Purposes Using SDL Manuel Rodr´ ıguez- Cayetano Summary CPU Scheduling Overview The SDL CPU Scheduler Simulator

Requirements Behavior Overview Simulator structure Detailed Behavior

The CPU Scheduler Simulator Graphical User Interface Conclusions and Further Work

Simulator structure: CPUSchedulerBlockType

block type CPUSchedulerBlockType 1(1)

Synonym CPUSchedulerBlockType.sbt_Id charstring = ’$Id: CPUSchedulerBlockType.sbt,v 1.2 2010/03/11 18:36:02 manrod Exp $’;

control: ControlType masterScheduler(0,): MasterSchedulerType slaveScheduler(0,): SlaveSchedulerType ControlType MasterSchedulerType ctrl_scheduler_G

schedulerReady, errorSignal, clientIdSignal, schedulerEnd_c, (output_sl) (control_input_sl)

Control_Env_R

(control_input_sl) schedulerReady, errorSignal, clientIdSignal, schedulerEnd_c

ControlType_G Master_Env_R

(output_sl)

Master_Env_G master_slave_R

algorithmEnd, deactivateQueueACK startAlgorithm, abortAlgorithm, getList, quantumSignal, apropiative, finaltime, activateQueue, procedure updateReadyList

slave_master_G master_slave_G slave_env_R

sendList, errorSignal

slave_env_G control_scheduler_R

(scheduler_input_sl) schedulerEnd

ControlType_G Master_Control_G

slide-35
SLIDE 35

12/22

Design and Development

  • f a CPU

Scheduler Simulator for Educational Purposes Using SDL Manuel Rodr´ ıguez- Cayetano Summary CPU Scheduling Overview The SDL CPU Scheduler Simulator

Requirements Behavior Overview Simulator structure Detailed Behavior

The CPU Scheduler Simulator Graphical User Interface Conclusions and Further Work

Process Type functions

controlType process type:

creating a masterScheduler process for a simulation requested by one user dispatching signals coming from different users to the corresponding masterScheduler process

masterSchedulerType:

simulation configuration inter-queues algorithm (the maximum priority non-empty ready queue is activated) access control of the ready queues shared variables

slaveSchedulerType:

simulation of a simple (one ready queue) scheduling algorithm

finding process arrivals (storing every arrived process in the ready queue) selecting a process from the ready queue to be executed (leaves the ready queue) interrupting a process and returning it to the ready queue terminating a process when its CPU burst is completed (storing the process in the finished queue)

slide-36
SLIDE 36

12/22

Design and Development

  • f a CPU

Scheduler Simulator for Educational Purposes Using SDL Manuel Rodr´ ıguez- Cayetano Summary CPU Scheduling Overview The SDL CPU Scheduler Simulator

Requirements Behavior Overview Simulator structure Detailed Behavior

The CPU Scheduler Simulator Graphical User Interface Conclusions and Further Work

Process Type functions

controlType process type:

creating a masterScheduler process for a simulation requested by one user dispatching signals coming from different users to the corresponding masterScheduler process

masterSchedulerType:

simulation configuration inter-queues algorithm (the maximum priority non-empty ready queue is activated) access control of the ready queues shared variables

slaveSchedulerType:

simulation of a simple (one ready queue) scheduling algorithm

finding process arrivals (storing every arrived process in the ready queue) selecting a process from the ready queue to be executed (leaves the ready queue) interrupting a process and returning it to the ready queue terminating a process when its CPU burst is completed (storing the process in the finished queue)

slide-37
SLIDE 37

12/22

Design and Development

  • f a CPU

Scheduler Simulator for Educational Purposes Using SDL Manuel Rodr´ ıguez- Cayetano Summary CPU Scheduling Overview The SDL CPU Scheduler Simulator

Requirements Behavior Overview Simulator structure Detailed Behavior

The CPU Scheduler Simulator Graphical User Interface Conclusions and Further Work

Process Type functions

controlType process type:

creating a masterScheduler process for a simulation requested by one user dispatching signals coming from different users to the corresponding masterScheduler process

masterSchedulerType:

simulation configuration inter-queues algorithm (the maximum priority non-empty ready queue is activated) access control of the ready queues shared variables

slaveSchedulerType:

simulation of a simple (one ready queue) scheduling algorithm

finding process arrivals (storing every arrived process in the ready queue) selecting a process from the ready queue to be executed (leaves the ready queue) interrupting a process and returning it to the ready queue terminating a process when its CPU burst is completed (storing the process in the finished queue)

slide-38
SLIDE 38

13/22

Design and Development

  • f a CPU

Scheduler Simulator for Educational Purposes Using SDL Manuel Rodr´ ıguez- Cayetano Summary CPU Scheduling Overview The SDL CPU Scheduler Simulator

Requirements Behavior Overview Simulator structure Detailed Behavior

The CPU Scheduler Simulator Graphical User Interface Conclusions and Further Work

Procedures relating to single-queue algorithms

Two types of behavior in single queue scheduling algorithms:

behavior common to all the algorithms: included in the genericAlgorithm procedure algorithm-dependent behavior: included in algorithm specific procedures (one per single-queue algorithm)

Low level tasks (for example, managing process queues and updating the clock) are specified in auxiliary procedures (findArrivals, executeProcess, interruptProcess, etc.)

main behavior of the algorithm is clearly specified without unnecessary low-level details

slide-39
SLIDE 39

13/22

Design and Development

  • f a CPU

Scheduler Simulator for Educational Purposes Using SDL Manuel Rodr´ ıguez- Cayetano Summary CPU Scheduling Overview The SDL CPU Scheduler Simulator

Requirements Behavior Overview Simulator structure Detailed Behavior

The CPU Scheduler Simulator Graphical User Interface Conclusions and Further Work

Procedures relating to single-queue algorithms

Two types of behavior in single queue scheduling algorithms:

behavior common to all the algorithms: included in the genericAlgorithm procedure algorithm-dependent behavior: included in algorithm specific procedures (one per single-queue algorithm)

Low level tasks (for example, managing process queues and updating the clock) are specified in auxiliary procedures (findArrivals, executeProcess, interruptProcess, etc.)

main behavior of the algorithm is clearly specified without unnecessary low-level details

slide-40
SLIDE 40

14/22

Design and Development

  • f a CPU

Scheduler Simulator for Educational Purposes Using SDL Manuel Rodr´ ıguez- Cayetano Summary CPU Scheduling Overview The SDL CPU Scheduler Simulator

Requirements Behavior Overview Simulator structure Detailed Behavior

The CPU Scheduler Simulator Graphical User Interface Conclusions and Further Work

genericAlgorithm procedure specification (I)

;FPAR in/out readyList listType, in readyListId Integer, in/out runningProcess nodeData, in/out processInExec Boolean, in/out nextArrivalT Real, in/out clock Real, contextSaveT, contextLoadT Real, verboseMode Boolean, language languageType, clientData clientDataStruct; RETURNS endCauseType;

procedure genericAlgorithm 1(2)

DCL aborting Boolean := False, abortCause endCauseType, auxNode nodeData, algActive Boolean := False, maxPriArrivalQueueId Integer := 0; DCL genericAlgorithm.spd_Id charstring := ’ $Id: genericAlgorithm.spd,v 1.7 2010/09/07 09:32:45 manrod Exp $’; virtual deactivated procedure updateReadyList − activateQueue( clock, nextArrivalT) algActive := True (not (call emptyList( readyList))) and (not (nextArrivalT = clock)) checkingArrivals checkingExec *(deactivated) procedure updateReadyList checkingArrivals aborting = False call emptyArrivalList to PARENT ENDOK auxNode:= call getArrivalListHead to PARENT processInExec maxPriArrivalQueueId := call findMaxPriNonEmptyQueue to PARENT (maxPriArrivalQueueId /= readyListId) updateIdleCPUT (auxNode!arrivalTime −clock) to PARENT clock := auxNode!arrivalTime findArrivals(verboseMode, aborting, readyList, readyListId, Empty, clock, nextArrivalT, algActive, language, clientData) to PARENT checkingActive not(aborting) and not(algActive) processInExec interruptProcess( verboseMode, aborting, readyList, readyListId, runningProcess, processInExec, clock, contextSaveT, nextArrivalT, algActive, False,language, clientData) to PARENT deactivateQueueACK( clock) deactivated not(aborting) and algActive checkingExec algActive := False clock := auxNode!arrivalTime findArrivals(verboseMode, aborting, readyList, readyListId, mkstring(runningProcess), clock, nextArrivalT, algActive, language, clientData) to PARENT * abortAlgorithm( abortCause) abortCause aborting=True ERR checkingExec aborting=True ERR False True True False False False true false True True

slide-41
SLIDE 41

15/22

Design and Development

  • f a CPU

Scheduler Simulator for Educational Purposes Using SDL Manuel Rodr´ ıguez- Cayetano Summary CPU Scheduling Overview The SDL CPU Scheduler Simulator

Requirements Behavior Overview Simulator structure Detailed Behavior

The CPU Scheduler Simulator Graphical User Interface Conclusions and Further Work

genericAlgorithm procedure specification (II)

;FPAR in/out readyList listType, in readyListId Integer, in/out runningProcess nodeData, in/out processInExec Boolean, in/out nextArrivalT Real, in/out clock Real, contextSaveT, contextLoadT Real, verboseMode Boolean, language languageType, clientData clientDataStruct; RETURNS endCauseType;

procedure genericAlgorithm 2(2)

executingProc interruptingProc aborting = false aborting = false execProcess(verboseMode, aborting, readyList, readyListId, runningProcess, processInExec, clock, contextLoadT, nextArrivalT, algActive, language, clientData) to PARENT interruptProcess(verboseMode, aborting, readyList, readyListId, runningProcess, processInExec, clock, contextSaveT, nextArrivalT, algActive, True, language, clientData) to PARENT checkingActive checkingActive

slide-42
SLIDE 42

16/22

Design and Development

  • f a CPU

Scheduler Simulator for Educational Purposes Using SDL Manuel Rodr´ ıguez- Cayetano Summary CPU Scheduling Overview The SDL CPU Scheduler Simulator

Requirements Behavior Overview Simulator structure Detailed Behavior

The CPU Scheduler Simulator Graphical User Interface Conclusions and Further Work

An example of an specific algorithm procedure

inherits genericAlgorithm;

procedure fcfs 1(1)

DCL fcfs.spd_Id charstring := ’ $Id: fcfs.spd,v 1.6 2010/03/25 18:27:51 manrod Exp $’; checkingExec aborting=False processInExec executingProc ((call precCompare( runningProcess! remainingExecT+clock, nextArrivalT)) /= LESS) AND (NOT(nextArrivalT = NOMOREPROCESSES)) terminateProcess(verboseMode, aborting, runningProcess, processInExec, clock, language, clientData) to PARENT call emptyList( readyList) checkingArrivals decrRemainingExecT( runningProcess, nextArrivalT−clock) to PARENT False True False False True True

slide-43
SLIDE 43

17/22

Design and Development

  • f a CPU

Scheduler Simulator for Educational Purposes Using SDL Manuel Rodr´ ıguez- Cayetano Summary CPU Scheduling Overview The SDL CPU Scheduler Simulator The CPU Scheduler Simulator Graphical User Interface Conclusions and Further Work

The CPU Scheduler Simulator Graphical User Interface: tkCPUSched

A graphical user interface (GUI) has been developed to simplify the access to the simulator functionalities

simulator program generated from the SDL specification is

  • nly accessible through a TCP socket

GUI developed using Tcl/Tk language

interpreted language that provides rapid development of cross-platform graphical user interfaces

GUI module for parsing simulator outgoing signals:

format of the signals interchanged with the environment: Telelogic ASCII encoding (TCP communications module)

example: {1}{’schedulerEnd c’}{{’127.0.0.1’,50205}}

parsing module based on an automatically generated parser and lexical analyzer

parser and lexical analyzer based on a grammar specific to the ASCII encoding: changes in the signal encoding ⇒ modifying the grammar and re-generating the parser and lexical analyzer GUI can be adapted to support a simulator generated by different SDL case tools

slide-44
SLIDE 44

17/22

Design and Development

  • f a CPU

Scheduler Simulator for Educational Purposes Using SDL Manuel Rodr´ ıguez- Cayetano Summary CPU Scheduling Overview The SDL CPU Scheduler Simulator The CPU Scheduler Simulator Graphical User Interface Conclusions and Further Work

The CPU Scheduler Simulator Graphical User Interface: tkCPUSched

A graphical user interface (GUI) has been developed to simplify the access to the simulator functionalities

simulator program generated from the SDL specification is

  • nly accessible through a TCP socket

GUI developed using Tcl/Tk language

interpreted language that provides rapid development of cross-platform graphical user interfaces

GUI module for parsing simulator outgoing signals:

format of the signals interchanged with the environment: Telelogic ASCII encoding (TCP communications module)

example: {1}{’schedulerEnd c’}{{’127.0.0.1’,50205}}

parsing module based on an automatically generated parser and lexical analyzer

parser and lexical analyzer based on a grammar specific to the ASCII encoding: changes in the signal encoding ⇒ modifying the grammar and re-generating the parser and lexical analyzer GUI can be adapted to support a simulator generated by different SDL case tools

slide-45
SLIDE 45

17/22

Design and Development

  • f a CPU

Scheduler Simulator for Educational Purposes Using SDL Manuel Rodr´ ıguez- Cayetano Summary CPU Scheduling Overview The SDL CPU Scheduler Simulator The CPU Scheduler Simulator Graphical User Interface Conclusions and Further Work

The CPU Scheduler Simulator Graphical User Interface: tkCPUSched

A graphical user interface (GUI) has been developed to simplify the access to the simulator functionalities

simulator program generated from the SDL specification is

  • nly accessible through a TCP socket

GUI developed using Tcl/Tk language

interpreted language that provides rapid development of cross-platform graphical user interfaces

GUI module for parsing simulator outgoing signals:

format of the signals interchanged with the environment: Telelogic ASCII encoding (TCP communications module)

example: {1}{’schedulerEnd c’}{{’127.0.0.1’,50205}}

parsing module based on an automatically generated parser and lexical analyzer

parser and lexical analyzer based on a grammar specific to the ASCII encoding: changes in the signal encoding ⇒ modifying the grammar and re-generating the parser and lexical analyzer GUI can be adapted to support a simulator generated by different SDL case tools

slide-46
SLIDE 46

17/22

Design and Development

  • f a CPU

Scheduler Simulator for Educational Purposes Using SDL Manuel Rodr´ ıguez- Cayetano Summary CPU Scheduling Overview The SDL CPU Scheduler Simulator The CPU Scheduler Simulator Graphical User Interface Conclusions and Further Work

The CPU Scheduler Simulator Graphical User Interface: tkCPUSched

A graphical user interface (GUI) has been developed to simplify the access to the simulator functionalities

simulator program generated from the SDL specification is

  • nly accessible through a TCP socket

GUI developed using Tcl/Tk language

interpreted language that provides rapid development of cross-platform graphical user interfaces

GUI module for parsing simulator outgoing signals:

format of the signals interchanged with the environment: Telelogic ASCII encoding (TCP communications module)

example: {1}{’schedulerEnd c’}{{’127.0.0.1’,50205}}

parsing module based on an automatically generated parser and lexical analyzer

parser and lexical analyzer based on a grammar specific to the ASCII encoding: changes in the signal encoding ⇒ modifying the grammar and re-generating the parser and lexical analyzer GUI can be adapted to support a simulator generated by different SDL case tools

slide-47
SLIDE 47

18/22

Design and Development

  • f a CPU

Scheduler Simulator for Educational Purposes Using SDL Manuel Rodr´ ıguez- Cayetano Summary CPU Scheduling Overview The SDL CPU Scheduler Simulator The CPU Scheduler Simulator Graphical User Interface Conclusions and Further Work

tkCPUSched: main window

Additional features:

queue status shown during simulation (and process statistic values) plotting of Gantt charts during simulation

slide-48
SLIDE 48

18/22

Design and Development

  • f a CPU

Scheduler Simulator for Educational Purposes Using SDL Manuel Rodr´ ıguez- Cayetano Summary CPU Scheduling Overview The SDL CPU Scheduler Simulator The CPU Scheduler Simulator Graphical User Interface Conclusions and Further Work

tkCPUSched: main window

Additional features:

queue status shown during simulation (and process statistic values) plotting of Gantt charts during simulation

slide-49
SLIDE 49

19/22

Design and Development

  • f a CPU

Scheduler Simulator for Educational Purposes Using SDL Manuel Rodr´ ıguez- Cayetano Summary CPU Scheduling Overview The SDL CPU Scheduler Simulator The CPU Scheduler Simulator Graphical User Interface Conclusions and Further Work

Conclusions (I)

Simulator features:

simulator capable of simulating the behavior of

  • ne-queue scheduling algorithms (appropriate for one class
  • f processes workloads)

multilevel queue algorithms (appropriate for workloads consisting of processes with different scheduling requirements)

simulation results (per-process and global statistics) and simulation events shown in a human-readable format using a graphical user interface

results and events can also be saved in files

graphical user interface developed with the Tcl/Tk language: rapid development and cross-platform support parsing of signals outgoing simulator program based on a grammar definition of their encoding method

change of the encoding method only implies minimum changes in the graphical user interface (adapting the grammar and re-generating the parser and lexical analyzer) GUI customizable to interact with simulators generated by different SDL case tools

slide-50
SLIDE 50

19/22

Design and Development

  • f a CPU

Scheduler Simulator for Educational Purposes Using SDL Manuel Rodr´ ıguez- Cayetano Summary CPU Scheduling Overview The SDL CPU Scheduler Simulator The CPU Scheduler Simulator Graphical User Interface Conclusions and Further Work

Conclusions (I)

Simulator features:

simulator capable of simulating the behavior of

  • ne-queue scheduling algorithms (appropriate for one class
  • f processes workloads)

multilevel queue algorithms (appropriate for workloads consisting of processes with different scheduling requirements)

simulation results (per-process and global statistics) and simulation events shown in a human-readable format using a graphical user interface

results and events can also be saved in files

graphical user interface developed with the Tcl/Tk language: rapid development and cross-platform support parsing of signals outgoing simulator program based on a grammar definition of their encoding method

change of the encoding method only implies minimum changes in the graphical user interface (adapting the grammar and re-generating the parser and lexical analyzer) GUI customizable to interact with simulators generated by different SDL case tools

slide-51
SLIDE 51

19/22

Design and Development

  • f a CPU

Scheduler Simulator for Educational Purposes Using SDL Manuel Rodr´ ıguez- Cayetano Summary CPU Scheduling Overview The SDL CPU Scheduler Simulator The CPU Scheduler Simulator Graphical User Interface Conclusions and Further Work

Conclusions (I)

Simulator features:

simulator capable of simulating the behavior of

  • ne-queue scheduling algorithms (appropriate for one class
  • f processes workloads)

multilevel queue algorithms (appropriate for workloads consisting of processes with different scheduling requirements)

simulation results (per-process and global statistics) and simulation events shown in a human-readable format using a graphical user interface

results and events can also be saved in files

graphical user interface developed with the Tcl/Tk language: rapid development and cross-platform support parsing of signals outgoing simulator program based on a grammar definition of their encoding method

change of the encoding method only implies minimum changes in the graphical user interface (adapting the grammar and re-generating the parser and lexical analyzer) GUI customizable to interact with simulators generated by different SDL case tools

slide-52
SLIDE 52

19/22

Design and Development

  • f a CPU

Scheduler Simulator for Educational Purposes Using SDL Manuel Rodr´ ıguez- Cayetano Summary CPU Scheduling Overview The SDL CPU Scheduler Simulator The CPU Scheduler Simulator Graphical User Interface Conclusions and Further Work

Conclusions (I)

Simulator features:

simulator capable of simulating the behavior of

  • ne-queue scheduling algorithms (appropriate for one class
  • f processes workloads)

multilevel queue algorithms (appropriate for workloads consisting of processes with different scheduling requirements)

simulation results (per-process and global statistics) and simulation events shown in a human-readable format using a graphical user interface

results and events can also be saved in files

graphical user interface developed with the Tcl/Tk language: rapid development and cross-platform support parsing of signals outgoing simulator program based on a grammar definition of their encoding method

change of the encoding method only implies minimum changes in the graphical user interface (adapting the grammar and re-generating the parser and lexical analyzer) GUI customizable to interact with simulators generated by different SDL case tools

slide-53
SLIDE 53

20/22

Design and Development

  • f a CPU

Scheduler Simulator for Educational Purposes Using SDL Manuel Rodr´ ıguez- Cayetano Summary CPU Scheduling Overview The SDL CPU Scheduler Simulator The CPU Scheduler Simulator Graphical User Interface Conclusions and Further Work

Conclusions (II)

Experiences in the simulator development with SDL:

behavior specification of a scheduling algorithm is easier in SDL than in a programming language

a flow chart describing high-level algorithm behavior can be used to obtain SDL specifications SDL graphical syntax is more expressive than code for the description of an algorithm behavior

development and testing of concurrent applications easier in SDL

signal or procedure based communication in SDL versus external communications libraries, ad-hoc methods or shared variables in a programming language communications between processes explicitly shown (messages that can be exchanged, the sources and destinations allowed . . . ) powerful testing tools, including tracing of messages exchanged among processes (for example, MSC trace)

slide-54
SLIDE 54

20/22

Design and Development

  • f a CPU

Scheduler Simulator for Educational Purposes Using SDL Manuel Rodr´ ıguez- Cayetano Summary CPU Scheduling Overview The SDL CPU Scheduler Simulator The CPU Scheduler Simulator Graphical User Interface Conclusions and Further Work

Conclusions (II)

Experiences in the simulator development with SDL:

behavior specification of a scheduling algorithm is easier in SDL than in a programming language

a flow chart describing high-level algorithm behavior can be used to obtain SDL specifications SDL graphical syntax is more expressive than code for the description of an algorithm behavior

development and testing of concurrent applications easier in SDL

signal or procedure based communication in SDL versus external communications libraries, ad-hoc methods or shared variables in a programming language communications between processes explicitly shown (messages that can be exchanged, the sources and destinations allowed . . . ) powerful testing tools, including tracing of messages exchanged among processes (for example, MSC trace)

slide-55
SLIDE 55

21/22

Design and Development

  • f a CPU

Scheduler Simulator for Educational Purposes Using SDL Manuel Rodr´ ıguez- Cayetano Summary CPU Scheduling Overview The SDL CPU Scheduler Simulator The CPU Scheduler Simulator Graphical User Interface Conclusions and Further Work

Further work

Improvements for the current version of the simulator:

adding more complex algorithms, like multilevel feedback queue scheduling multi-processor / multi-core algorithms support of processes with several CPU and I/O bursts

slide-56
SLIDE 56

21/22

Design and Development

  • f a CPU

Scheduler Simulator for Educational Purposes Using SDL Manuel Rodr´ ıguez- Cayetano Summary CPU Scheduling Overview The SDL CPU Scheduler Simulator The CPU Scheduler Simulator Graphical User Interface Conclusions and Further Work

Further work

Improvements for the current version of the simulator:

adding more complex algorithms, like multilevel feedback queue scheduling multi-processor / multi-core algorithms support of processes with several CPU and I/O bursts

slide-57
SLIDE 57

21/22

Design and Development

  • f a CPU

Scheduler Simulator for Educational Purposes Using SDL Manuel Rodr´ ıguez- Cayetano Summary CPU Scheduling Overview The SDL CPU Scheduler Simulator The CPU Scheduler Simulator Graphical User Interface Conclusions and Further Work

Further work

Improvements for the current version of the simulator:

adding more complex algorithms, like multilevel feedback queue scheduling multi-processor / multi-core algorithms support of processes with several CPU and I/O bursts

slide-58
SLIDE 58

22/22

Design and Development

  • f a CPU

Scheduler Simulator for Educational Purposes Using SDL Manuel Rodr´ ıguez- Cayetano Summary CPU Scheduling Overview The SDL CPU Scheduler Simulator The CPU Scheduler Simulator Graphical User Interface Conclusions and Further Work

Questions?