CUstom Built HEterogeneous Multi- Core ArCHitectures (CUBEMACH): - - PowerPoint PPT Presentation

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CUstom Built HEterogeneous Multi- Core ArCHitectures (CUBEMACH): - - PowerPoint PPT Presentation

Dec 05, 2022 103 likes •530 views

CUstom Built HEterogeneous Multi- Core ArCHitectures (CUBEMACH): Breaking the Conventions Nagarajan Venkateswaran Director, Waran Research Foundation Karthikeyan Palavedu Saravanan - Nachiappan Chidambaram Nachiappan Research Trainees (2008 -

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CUstom Built HEterogeneous Multi- Core ArCHitectures (CUBEMACH):

Breaking the Conventions

Nagarajan Venkateswaran Director, Waran Research Foundation Karthikeyan Palavedu Saravanan - Nachiappan Chidambaram Nachiappan Research Trainees (2008 - 2010), Waran Research Foundation Aravind Vasudevan - Balaji Subramaniam - Ravindhiran Mukundarajan Former Research Trainees (2007 - 2009), Waran Research Foundation

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Chennai, India

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Motivation : Heterogeneity Redefined

  • Cost Effective High Performance Custom Built

Heterogeneous Multi-Core Node Design for wider class applications

– Inter and Intra core heterogeneity

  • Breaking the Conventions

– Multiple User Multiple Application without Space- Time sharing in a Cluster : Cost sharing across users – Single User Multiple Application without Space-Timer Sharing (non-multiprogramming) : Cost sharing across applications

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Chennai, India

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Overview

  • Custom Built Heterogeneous Multi-Core

Architectures (CUBEMACH)

  • Design Space

– Architectural Space – Optimization Space

– Customer Vendor Interaction

– Simulation Space

  • CUBEMACH Design and Simulation Tool

Framework

  • Conclusion

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Chennai, India

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Custom Built Heterogeneous Multi-Core Architectures (CUBEMACH)

  • CUBEMACH promises

– Increased Resource Utilization – Multiple Application Flavored Architectures – Elimination of Space Time Sharing at the Quantum Level during Multiple Application Execution – Manufacturing and Operational Cost reduction

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Chennai, India

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Overview

  • Custom Built Heterogeneous Multi-Core

Architectures (CUBEMACH)

  • Design Space

– Architectural Space

– Optimization Space

– Customer Vendor Interaction

– Simulation Space

  • CUBEMACH Design and Simulation Tool

Framework

  • Conclusion

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Chennai, India

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CUBEMACH Design Paradigm

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Chennai, India

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ONNET

CUBEMACH Architectural Space

SCOS PCOS

Compiler-On- Silicon

ALFU

SRAM DRAM

Memory ALISA

Architectural Design Space - CUBEMACH

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Chennai, India

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Architectural Space

  • Why ALU Why Not ALFU??

– Hardwired units –Design : Homogeneously Structured –Reduced Instruction Generation & Fetches : Employ a Higher Level ISA –Reduced memory-functional unit interaction –Helps execute multiple applications without space & time sharing

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Chennai, India

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Control Unit Algorithm Size Memory In Processor HLFU Characteristics ALFU Requirements Delay ALFU Types Class of Algorithms Type of MIP Cell Number

  • f MIP

Cells HLFU Control Centralize/ Decentralized Grain Size Architecture Class of Units Input Bits Scalar

ALFU Algorithm Level Functional Unit

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Chennai, India

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ALU vs ALFU Instruction Generation Results

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Chennai, India

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Sample Algorithm Level Functional Units

  • Matrix Centric Units
  • Matmul
  • Matadd
  • Chain Matadd
  • Scalar Units
  • Scalar Adder / Subtractor
  • Scalar Multiplier
  • Scalar Divider
  • Comparator
  • Sorter
  • Multiple Operand Adder
  • Min / Max Finder
  • Vector Units
  • Inner Product
  • Graph Theoretic Units
  • Graph Traversal Unit –

BFS, DFS

  • KL Graph Partitioning

Architectural Space Contd…

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Chennai, India

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ALISA – Algorithm Level Instruction Set Architecture

  • Algorithm Level Instructions
  • Triggers ALFUS
  • ALISA Multiple VLIWs
  • ALISA for heterogeneous multi-cores

Architectural Space Contd…

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Chennai, India

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Hierarchical Compilation Scheme

  • PCOS Partitions A Problem

Into Sub-Problems – Level 1

  • SCOS Partitions The Sub-

Problems Into ALFU Level Instruction – Level 2 PCOS SCOS

Application Sub - Application Instruction

Architectural Space Contd…

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Chennai, India

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ALISA & Compiler On Silicon

SCOS

PCOS

  • No. of parallel

Units Rate of Output Generation Scheduler Processing rate

  • No. of Ports

BISA Length

  • No. of I/O

Ports Scheduler O/P Generation rate

Compiler-On- Silicon

Number of Instructions Per ALISA Types of Instructions Per ALISA Types of Instructions in ISA

ALISA

No of ALISA Fields Decoding/ Encoding Logic Field Length

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Chennai, India

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ON-Node-Network Architecture

2D - Torus Sub-Local Router Local Router ALFU Population Global Router Core

Architectural Space Contd…

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Chennai, India

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ON-Node-Network Architecture

H- Tree Topology

Architectural Space Contd…

Sub-Local Router Local Router Global Router

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Chennai, India

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ONNET Conventional NOCs Type of Switch MIN Crossbar Number of Routers N* log 2 (N) N2 Hierarchy Yes No Switching Latency Log2(Number of Inputs) * Switch Delay Number of Inputs * Switch Delay

Comparison of Conventional NOCs with ONNET

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Chennai, India

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ONNET

Routers Organization Packet Switching Input/Output Packetization Address Decoding Destination ID Buffer Size Output Data Size HLFU ID Path Latency Destination Router ID Type of MIN Input Traffic HLFU Count Logical Grouping Buffer/ Stack Size Route Location Data Rate I/O Port

  • No. of

Decoders Decoding Rate Length of Stack

  • No. of Buffers

Packet Size I/P Data Size Word Length

On Node Network Architecture

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Chennai, India

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Overview

  • Motivation
  • Custom Built Heterogeneous Multi-Core

Architectures (CUBEMACH)

  • Design Space

– Architectural Space

– Optimization Space –Customer Vendor Interaction – Simulation Space

  • CUBEMACH Design and Simulation Tool

Framework

  • Conclusion

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Chennai, India

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CUBEMACH Architectural Space

Multiple Applications Multiple Applications

Multiple Applications Input

CUBEMACH Simulation Space

Optimization Space

Core Formation Power Model Performanc e Model Desired Power to Performance Ratio CUBEMACH Optimization Space Simulated Annealing Selected Parameters Final CUBEMACH Calculated Power to Performance Ratio

Initial Candidate Architecture Parameters

Game Theory

1 2 3 4 5 5a 5b 9 7 6 8

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Chennai, India

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Optimization Space

  • Generates Optimized CUBEMACH for input

specifications such as,

– Power – Performance – Cost – Initial Architecture

  • Power and Performance Model
  • Uses GT and SA for optimization of Power and

performance

  • Uses KL For Core Grouping

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Chennai, India

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Sample CUBEMACH Architecture

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CUBEMACH Design Implementation : Supercomputer On Chip (SCOC) IP Cores

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SCOC IP Cores

  • ALFUs designed as SCOC IP Cores
  • Soft IP Core
  • Coarse-grained Reusable Soft IP Cores
  • Scalable IP Cores

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Chennai, India

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Customer Vendor Interaction

App 2 App 3 App 4 App 1 CUBEMACH Node Manufacturers/ System Vendors

Customers Application Requirements – Power & Performance

Initial Heterogeneous Multi Core Candidate Architecture

Final Architecture

Layout Fabrication of IP Cores Simultaneous Multiple Applications

Optimizer

Workload Generation Intermediate Format

CUBEMACH Design Space

Simulator

SCOC IP CORES

Intermediate CUBEMACH Optimized CUBEMACH`

Optimization Space Contd…

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Chennai, India

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Overview

  • Motivation
  • Custom Built Heterogeneous Multi-Core

Architectures (CUBEMACH)

  • Design Space

– Architectural Space – Optimization Space –Customer Vendor Interaction – Simulation Space

  • CUBEMACH Design and Simulation Tool

Framework

  • Conclusion

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Chennai, India

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CUBEMACH Simulator

  • pThread based Simulator
  • Evaluates candidate CUBEMACH Architecture
  • Feed results to CUBEMACH Optimizer
  • CUBEMACH Optimization Engine (COE) produces

Optimized Architecture

  • Simulation & Optimization : An iterative process
  • Consists of

ALFU Sub-Simulator COS Sub-Simulator ONNET Sub-Simulator Memory Sub-Simulator

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Chennai, India

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CUBEMACH Simulator

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Integrated CUBEMACH Design Paradigm … What we have seen . . .

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Core Formation

ONNET

Routers Organization Packet Switching Input/Output Packetization Address Decoding Destination ID Buffer Size Output Data Size HLFU ID Path Latency Destination Router ID Type of MIN Input Traffic HLFU Count Logical Grouping Buffer/ Stack Size Route Location Data Rate I/O Port

  • No. of

Decoders Decodin g Rate Length

  • f Stack
  • No. of Buffers

Packet Size I/P Data Size Word Length

CUBEMACH Architectural Space

Multiple Applications Multiple Applications Multiple Applications Input Power Model Performance Model Desired Power to Performance Ratio

CUBEMACH Optimization Space CUBEMACH Simulation Space

Game Theory Simulated Annealing Selected Parameters Simulator Simulation Results Intermediate Architectural Parameters Final CUBEMACH Calculated Power to Performance Ratio Initial Candidate Architecture Parameters SCOS PCOS

  • No. of

parallel Units Rate of Output Generation Scheduler Processing rate

  • No. of

Ports BISA Length

  • No. of

I/O Ports Scheduler O/P Generation rate

Compiler-On-Silicon

Control Unit Algorithm Size Memory In Processor HLFU Characteristics ALFU Requirements Delay ALFU Types Class of Algorithms Type of MIP Cell Number

  • f MIP

Cells HLFU Control Centralize/ Decentralized Grain Size Architecture Class of Units Input Bits Scalar

ALFU SRAM DRAM

Mapping and Replacement Heuristic Packet Size No of Blocks DRAM Size SRAM Size Cache Line Size Word Length

Memory

No Of Ports Number of Instructions Per ALISA Types of Instructions Per ALISA Types of Instructions in ISA

ALISA

No of ALISA Fields Decoding/ Encoding Logic Field Length

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Sample CUBEMACH Architecture : Simulation Results

Matrix Based Algorithms Graph Based Algorithms

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Chennai, India

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Sample CUBEMACH Architecture : Simulation Results

Mixture of Algorithms Comparison of Performance delivered by Optimized Architectures for corresponding types of Algorithms

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Chennai, India

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Overall Resource Utilization of : (i) Initial CUBEMACH Architecture : Mean = 59 % (ii) Optimized CUBEMACH Architecture : Mean = 74 %

Sample CUBEMACH Architecture : Simulation Results

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Chennai, India

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In Initial Candidate CUBEMACH Architecture,

  • Matrix ALFUS – low usage
  • Scalar ALFUS – average usage
  • Graph ALFUS – high usage

In Optimized Candidate CUBEMACH Architecture,

  • Matrix ALFUS – high usage
  • Scalar ALFUS – high usage
  • Graph ALFUS – high usage

Sample CUBEMACH Architecture : Simulation Results

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Chennai, India

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Conclusion

  • Custom Built Heterogeneous Multi-Core

Architectures (CUBEMACH) promises,

– Increased Resource Utilization – Multiple application flavored architectures – Elimination of Space Time Sharing at the Quantum Level during Multiple Application Execution (without multiprogramming) – Manufacturing and Running Cost reduction

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Chennai, India

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Thank You Questions??

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Chennai, India

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Customizable Compiler-On-Silicon

  • What Compiler-On-Silicon?
  • Why do we need Compiler-On-Silicon ?
  • Why go for Customizable Compiler-On-Silicon ?

Architectural Space Contd…

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Chennai, India

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ONNET

Architecture uses -

  • Multistage Interconnect Network
  • Hardware Packetization Unit
  • ONNET Design Space

– H-Tree Structure within a Core – 2D Torus Across Cores – MIN Type

Architectural Space Contd…

ONNET

Routers Organizatio n Packet Switching Input/Outpu t Packetization Address Decoding Destination ID Buffer Size Output Data Size HLFU ID Path Latency Destination Router ID Type of MIN Input Traffic HLFU Count Logical Grouping Buffer/ Stack Size Route Location Data Rate I/O Port

  • No. of

Decoders Decodin g Rate Length

  • f Stack
  • No. of

Buffers Packet Size I/P Data Size Word Length

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Chennai, India

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Architectural Design Space - CUBEMACH

  • ALFU – Algorithm Level Functional Units
  • BISA – Backbone Instruction Set Architecture
  • COS – Compiler On Silicon
  • ONNET – On Node Network
  • Novel Cache Mapping Scheme
  • SCOC IP Cores : Achieving cost effectiveness

( Super Computer On Chip - IP Cores)

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Chennai, India

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Features -

  • Communication across heterogeneous multi-cores
  • Data requirements of diverse ALFUs
  • High bandwidth
  • Scalable
  • Hierarchical Network-On-Chip

On Node Network Architecture

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Chennai, India

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SRAM DRAM

Mapping and Replacement Heuristic Packet Size No of Blocks DRAM Size SRAM Size Cache Line Size Word Length

Memory

No Of Ports

Memory

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Chennai, India

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Advantages of SCOC IP Cores

  • Fully Customizable
  • Greatly reduces Design-Turnaround-Time
  • Physically Design Friendly

– Constraints of Area, Power and Performance

  • Constrained & Rigid Design Methodology

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Chennai, India