Cu electroplating in advanced packaging March 12 2019 Richard - - PowerPoint PPT Presentation

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Cu electroplating in advanced packaging March 12 2019 Richard - - PowerPoint PPT Presentation

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Cu electroplating in advanced packaging March 12 2019 Richard Hollman PhD Principal Process Engineer Internal Use Only Advancements in package technology The role of electroplating Examples: 4 challenging structures 2 Richard

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Cu electroplating in advanced packaging

Principal Process Engineer

March 12 2019

Richard Hollman PhD

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2 Richard Hollman / iMAPS NE meeting March 12 2019 Internal Use Only

  • Advancements in package technology
  • The role of electroplating
  • Examples: 4 challenging structures
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3 Richard Hollman / iMAPS NE meeting March 12 2019

Old paradigm: clear functional separation

IC:

  • Primary location for

performance improvement

  • Primary location for

increasing integration

Board:

  • Connection of heterogeneous components
  • IC’s
  • Passives
  • Switches, indicators
  • Peripherals
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4 Richard Hollman / iMAPS NE meeting March 12 2019 Internal Use Only

Moore’s Law on the wafer side

First transistor 1947 Bell Labs

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The longevity of the PWB concept

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Between the IC and the board: the Package

Package (old paradigm):

  • Mechanical protection for IC
  • Transparent 1:1 interface

between chip I/O and board IC:

  • Primary location for performance

improvement

  • Primary location for increasing

integration

Board:

  • Connection of heterogeneous components
  • IC’s
  • Passives
  • Switches, indicators
  • Peripherals
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New paradigm: package takes on aspects of IC and board

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8 Richard Hollman / iMAPS NE meeting March 12 2019

Smart Watch electronics  SIP

Smaller # of larger multichip packages

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“Moore’s Law for Packaging”

Rao Tummala, 2019 Pan Pacific Microelectronics Symposium

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Factors driving package technology acceleration

  • Possible slowdown in Moore’s Law shrinks

– Integration will involve multiple chips

  • Off-chip signal delays become critical

– Logic, memory and some passives connected in same package

  • More RF components, packaged closer to logic and memory
  • 5G networks: new interposer materials, new designs, more filters
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Feature shrinks in the package space

  • Feature size evolution lags IC

fabrication by ~ 30 years

  • Entering a period of faster

shrinks

  • Simply dust off old

semiconductor equipment and processes? No.

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12 Richard Hollman / iMAPS NE meeting March 12 2019

Unique challenges in package fabrication

  • Lithography

– Very thick photoresists, very high aspect ratio structures: low NA lenses required – Challenging substrates: reconstituted wafers, panels – Random die placement errors: requires new alignment strategies

  • PVD

– High-outgassing substrates – Low stiffness substrates – Sensitivity to heating during process

  • High temperature processes (CVD, etc) are ruled out
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Wafer Package

Metal deposition has a central role in electronics manufacturing

Layers of metals and insulators Most layers are patterned

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Method of metal deposition

Others ECD (electroplating) CVD Evaporation PVD

  • 3D printing
  • Screen printing
  • Foil lamination
  • Etc
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ECD (Electro Chemical Deposition)

  • Components

– Chemically resistant vessel – Electrolyte bath containing a metal salt – Anode: may or may not be the same metal as in solution – Cathode: substrate for deposited metal – Power source

  • Voltage is applied between the electrodes
  • Current flows across bath, carried by metal ions
  • When metal ions reach the cathode surface, they are

attached forming a film of solid metal

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ECD (Electro Chemical Deposition)

  • Components

– Chemically resistant vessel – Electrolyte bath containing a metal salt – Anode: may or may not be the same metal as in solution – Cathode: substrate for deposited metal – Power source

  • Voltage is applied between the electrodes
  • Current flows across bath, carried by metal ions
  • When metal ions reach the cathode surface, they are

attached forming a film of solid metal

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ECD vs evaporation, CVD, PVD

  • Low temperature process (20 - 60°C)
  • Not a vacuum process
  • Different set of metals available
  • Much faster deposition rates
  • Can be deposited through a photoresist pattern
  • Alloy deposition
  • Metal properties can be controlled by bath composition and

process

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Patterned deposition

Plating bath Ion flow Boundary layer Photoresist Substrate Seed layer: makes electrical connection at edge of wafer

After plating, photoresist and seed layer are stripped

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Plating in wafer fabrication

  • TSV
  • Damascene
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Plating in device packaging

  • On wafer before singulation

– Pad buildup – Flip chip bumping – Cu pillar – RDL

  • Other device types

– RF filters (bond pads, inductors) – OE devices

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Recent developments affecting plating for packaging

  • Reconstituted wafer
  • Fanout
  • Interposers
  • Heterogenous

integration

  • Panel
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Challenging structures for Cu plating

  • Megapillar
  • Embedded conductor
  • Large via plus pad
  • 3D integrated inductor
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Challenge for Cu plating: Megapillar

  • Some fanout designs include

stacking chips

  • Very large Cu pillars used for

power, signal and thermal conduction

  • Greatly scaled-up version of Cu

pillars used for chip-interposer connections

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Issues in plating megapillars

  • Because of the extreme height (200mm), a high

plating rate (3 to 5 mm/min) is demanded

  • Because of the extreme depth of the resist feature,

diffusion of Cu2+ ions places a strict limit on plating rate

– DV at interface drives the deposition reaction – Reaction removes Cu2+ ions from solution at the interface – Concentration gradient pulls Cu2+ ions from bulk

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Maximizing Cu diffusion

  • Steady-state diffusion:
  • Maximum deposition rate:

Max rate

  • Solution:

– Increase D by raising bath temperature – Increase bulk concentration of Cu

j

200mm high pillars plated at 3mm/min

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Embedded conductor for multilayer RDL

  • Photoresist process:

– Conductor lines stand above dielectric – With multiple layers, topography stack-up presents a problem for DOF in lithography

  • Embedded conductor:

– Dielectric is patterned: photosensitive polyimide or ablation – Trenches are filled to create conductor lines – Excess metal removed by CMP

Problem: CMP may not be practical for panel substrates

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Solution: modified TSV plating chemistry

  • Efficient bottom-up plating

Trenches are filled with minimal overburden, which can be stripped with deplating + wet etch

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Using TSV chemistry: effect of leveler

  • Needed: leveler-dominated plating in one

location, accelerator-dominated plating at another

  • TSV:

– Leveler is a large molecule, small diffusion coefficient – Very low concentration at beginning of plating, remains low throughout process

  • Embedded conductor:

– No significant separation at beginning of process – Geometric leveling and accelerator pileup create runaway effect at bottom of trench

Bottom of via Bottom of trench Bulk solution (top surface)

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Large via plus pad

  • Structure seen increasingly in RF filter

and OE device applications

  • Via with large dimensions: up to 70mm in

depth and diameter

  • Pad at the top of the via: to be plated to

5 to 20mm thickness

  • Requirements:

– Complete fill, no voids – Minimal dimple or mound over via – Flat pad, specified thickness

Seed layer deposition Photoresist patterning Plating Strip resist and seed layer

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Problems in plating large via + pad

  • Conformal plating: pad reaches

target thickness, via not filled

  • Sub-conformal: slower plating

at bottom, voids form

  • TSV chemistry: via fills and

forms mound, pad << target thickness

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Solution: less extreme leveler action

  • Leveler allows higher rate at

saturation

  • Reduced leveler at bottom of via

by combination of initial diffusion and geometric leveling

  • Faster plating to fill via, but some

deposition desired on pad

For arbitrary combinations of via size and pad thickness, plating + deplating may be required

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Integrated 3D inductor

  • Inductors in RF devices normally consist of flat

coils

– RDL process

  • Inclusion of increasing # of filters in mobile

devices creates a space crunch

  • Several groups have reported on 3D design

– Several orders of magnitude more inductance per unit area

  • Requires combination of RDL (top and bottom)

and high aspect ratio pillars

  • Depending on dielectric, resist-defined or TSV-like

process may be needed

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Summary

  • Possible Moore’s Law slowdown and 5G requirements are shifting

technology emphasis onto the package

  • ECD has a central role in this development
  • Meeting the requirements for package fabrication requires innovative

approaches in plating

  • The next 10 years should be very interesting!
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Our Vision

ENABLING THE DIGITAL WORLD

Our Mission

Together – We have the POWER and agility to drive changes We deliver the highest value and innovative solutions to our customers through products and solutions with advanced technologies and excellent quality. We aspire to make ASMPT a great work place, a great business partner and a great company built to last.

Thank You