CRYOGENIC AND RADIATION-HARD ASIC FOR INTERFACING LARGE FORMAT - - PowerPoint PPT Presentation

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CRYOGENIC AND RADIATION-HARD ASIC FOR INTERFACING LARGE FORMAT - - PowerPoint PPT Presentation

Nov 11, 2023 108 likes •448 views

ICSO 2014 Tenerife CRYOGENIC AND RADIATION-HARD ASIC FOR INTERFACING LARGE FORMAT NIR/SWIR DETECTOR ARRAYS P.Gao, B.Dupont, B.Dierickx, E.Mueller, G.Verbruggen , S.Gielis, R.Valvekens, About us Image sensors and periphery ASICs Founded

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SLIDE 1

CRYOGENIC AND RADIATION-HARD ASIC FOR INTERFACING LARGE FORMAT NIR/SWIR DETECTOR ARRAYS

P.Gao, B.Dupont, B.Dierickx, E.Mueller, G.Verbruggen, S.Gielis, R.Valvekens,

ICSO 2014 Tenerife

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SLIDE 2

About us

  • Image sensors and periphery ASICs
  • Founded 2006
  • Mechelen, Belgium
  • 17 p (10 designers)

2

Supplier of Custom designed Beyond “State of the Art” CMOS Image sensors and ASIC for

Space, Scientific, Industrial and Medical applications

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SLIDE 3

Outline

  • Motivation
  • Architecture and building block design
  • Design for Radiation hardness and Cryogenic

temperature

  • Test results
  • Conclusions & future work

11/2/2014 3 ASIC for LF NIR/SWIR detector array

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SLIDE 4

Outline

  • Motivation
  • Architecture and building block design
  • Design for Radiation hardness and Cryogenic

temperature

  • Test results
  • Conclusions & future work

11/2/2014 4 ASIC for LF NIR/SWIR detector array

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SLIDE 5

To operate an IR imagers Digital domain

Digital control core Memory & Clock Data Communication

Analog domain

Signal conditioning Analog to digital converter Regulated power supply Bias voltage/current references

Why an ASIC ?

11/2/2014 5 [Z.Zhao.SDA’05] ASIC for LF NIR/SWIR detector array

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SLIDE 6

The ASIC

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This development aims at providing the community with a IR imager accompany ASIC

  • Tailored to imagers (especially IR sensor)

– Easy to control – Simple to intergrade

  • Taking in consideration multiple IR detector manufacturers

specificities

  • Wide operating temperature range (77k – room T)
  • Able to drive multi-sensor/array systems
  • Radiation hard

– 1Mrad TID – 60MeVcm2 /mg SEU

ASIC for LF NIR/SWIR detector array

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SLIDE 7

Outline

  • Motivation
  • Architecture and building block design
  • Design for Radiation hardness and Cryogenic

temperature

  • Test results
  • Conclusions& future work

11/2/2014 7 ASIC for LF NIR/SWIR detector array

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SLIDE 8

Architecture

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SLIDE 9

Analog section

11/2/2014 9 Bandgap T sensor ASIC for LF NIR/SWIR detector array

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SLIDE 10

Supply

  • LDO

– Programmable output

  • 1,3…3.4V

– Stability: PM>60° – Output current 0-100mA

  • Bandgap

– 1.2V – 77K-300K

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SLIDE 11

Conversion channel

  • One ADC addressed 4 analog inputs in prototype ASIC
  • CDS

– Bypassable

  • Preamplifier (PA)

– Programmable gain from 0-30dB in 6dB step – Offset cancellation (8-bit) – Single to differential

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SLIDE 12

ADC

  • 16-bit, 100kHz, fully differential SAR ADC

– Hybrid feedback DAC – Low offset comparator auto zero

  • A calibration scheme is implemented

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SLIDE 13

Digital section

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SLIDE 14

Specifications

11/2/2014 14 Digital domain Master clock 0 – 200 MHz System level protocol 2 – 200 Mbit/s Space Wire ROIC digital control 32 ROIC monitoring and trigger inputs 8 Scheduler time granularity 10M updates/s Sequence nesting depth 8 ROIC programming channel 1 SPI ASIC for LF NIR/SWIR detector array

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SLIDE 15

Outline

  • Motivation
  • Architecture and building block design
  • Design for Radiation hardness and Cryogenic

temperature

  • Test results
  • Conclusions& future work

11/2/2014 15 ASIC for LF NIR/SWIR detector array

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SLIDE 16

Radiation hardness: digital

  • Synthetized digital logic

–DARE lib (IMEC & ESA)

  • 0.18 um CMOS 1P6M
  • Digital cell with TID, SEU, SEL tolerance
  • Allows custom mixed-signal design

–Redundancy

  • Hamming Codes
  • Parity check
  • Safe FSMs

–Watchdog Timers

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SLIDE 17

Radiation hardness: analog

DARE has a limited subset of analog component. Caeleste developed its own radhard cells

  • Analog and High Voltage logic standard cells
  • Full custom tactical cells

– Analog & mixed mode – TID & TnID hardness – SEL hardness – SEU hardness without TR – <20% increased Cin and power – <50% area increase

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Normal Caeleste mixed mode Caeleste RH

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SLIDE 18

Design for low temperature

  • Synthetized digital logic:

– A derating of speed, power, etc. of the library – SRAM

  • Analog custom design:

– Active component modeling – Component selection

11/2/2014 18 ASIC for LF NIR/SWIR detector array

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SLIDE 19

Cryogenic digital design

The DARE library has never been used at 77K before

  • Faster but risk for set-up and hold time violation.

– Adapted models based on characterization at 218K

  • SRAM has not been validated before

– Backup registers

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SLIDE 20

Cryogenic analog design

  • MOSFET modeling

– Vth: increase – Mobility: increase – MOS switch: low Ron

  • Passive components

– Highly doped non silicide poly Resistor for stability – MIM capacitors

  • Rely on ratios not absolutely values

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Transistor Vt NMOS: 0.68-0.91 PMOS: 0.75-0.97

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SLIDE 21

Outline

  • Motivation
  • Architecture and building blocks design
  • Design for Radiation hardness and Cryogenic

temperature

  • Test results
  • Conclusions

11/2/2014 21 ASIC for LF NIR/SWIR detector array

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SLIDE 22

Test setup

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Digital Controller Analog test board Precision DAC board ASIC COB Base plate

Unified design for: RT board CT board RT board CT board

+ +

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SLIDE 23

Bandgap and temperature sensor

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0,0 0,1 0,2 0,3 0,4 0,5 0,6 0,7 0,8 0,9 1,0 70 120 170 220 270 320

  • utput voltage (V)

Temperature (K)

T-sensor measurement

T coefficient: 3mV/K

1,05 1,1 1,15 1,2 1,25 1,3 1,35 50 100 150 200 250 300 350

  • utput valtage (V)

Temperature (K)

Bandgap measuement

T coefficient< 1mV/K

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SLIDE 24

Reference and Biases 10-bit

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  • 0,04
  • 0,03
  • 0,02
  • 0,01

0,01 0,02 0,03 0,04 200 400 600 800 1000

DNL(LSB) Input code

BIAS0 DNL

  • 0,4
  • 0,2

0,2 0,4 0,6 200 400 600 800 1000

INL(LSB) Input code

BIAS0 INL

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SLIDE 25
  • On chip SC current source.

– R range 10k – 70k ohm

R monitor

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Measured output voltage with 2MHz clock

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SLIDE 26

16-bit SAR ADC INL DNL

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  • INL DNL problem :

–Root cause is a AC coupling in the

layout: 2 fF cross-coupling

M5 M4

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SLIDE 27

ADC INL DNL

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  • ADC INL DNL problem analysis
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SLIDE 28

ADC INL DNL

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  • ADC INL DNL @ 50KHz fs
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SLIDE 29

Measurement summary

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Specs

Measurement result @ room T @ cryogenic T Supply voltage 3.5-3.6V Total current consumption 53mA 60.5mA Regulator PSRR > 40dB Regulator I out > 40mA Output impedance < 1Ω LDO output 1.3-3.4 V Analog rail to rail voltage 3.3 V Reference DAC INL 0.7LSB 1LSB Reference DAC DNL 0.06LSB 0.04LSB ADC noise 2.5LSB 2.1LSB ADC fs 50, 100, 200KHz ADC INL 78LSB (15LSB@50KHz) ADC DNL 76LSB (16LSB@50KHz) Monitor resistance range 10KΩ -70KΩ Number of digital outputs/ inputs 32 / 8 Digital output clock speed 0-10 MHz Serial interface speed 50KHz-50MHz SpaceWire bit rate 0-200 Mbps ASIC start-up time ≤50us Temperature range 77K-room T (Measured)

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SLIDE 30

Outline

  • Motivation
  • Architecture and building

block design

  • Design for Radiation hardness

and Cryogenic temperature

  • Test results
  • Conclusions& future work

11/2/2014 30 ASIC for LF NIR/SWIR detector array

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SLIDE 31

Conclusions

11/2/2014 31

  • Prototype accompany ASIC for (IR) detector arrays which

provide all functionalities has been demonstrated

– ADC problem founded and will solve in next iteration

  • Full function has been proven from cryogenic (77K) to

room temperature

– All Caeleste custom designed cells – Digital cells in DARE Lib. Including SRAM

  • Highly flexible for ROICs

– Highly programmable sequencer – Wide programmability and large dynamic ranges in analog acquisition chain

  • Beyond IR imagers

ASIC for LF NIR/SWIR detector array

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SLIDE 32

Next steps ?

11/2/2014 32

  • Larger ASIC with multiple channels (32 to 64)
  • Faster ADCs is now developing at Caeleste (up to

12MS/s with reduced resolution)

  • Irradiation testing
  • More discussion with instrument builders and IR sensor

manufacturers for further enhancements

ASIC for LF NIR/SWIR detector array

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SLIDE 33

Thank you!

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