CPU-specific optimization Example of a function that we want to - - PowerPoint PPT Presentation
1 2 CPU-specific optimization Example of a function that we want to optimize: Example of a target CPU core: adding 1000 integers mod 2 32 . ARM Cortex-M4F core inside LM4F120H5QR microcontroller Reference implementation: in Stellaris
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CPU-specific optimization Example of a target CPU core: ARM Cortex-M4F core inside LM4F120H5QR microcontroller in Stellaris LM4F120 Launchpad.
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Example of a function that we want to optimize: adding 1000 integers mod 232. Reference implementation:
int sum(int *x) { int result = 0; int i; for (i = 0;i < 1000;++i) result += x[i]; return result; }
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CPU-specific optimization Example of a target CPU core: Cortex-M4F core inside LM4F120H5QR microcontroller Stellaris LM4F120 Launchpad.
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Example of a function that we want to optimize: adding 1000 integers mod 232. Reference implementation:
int sum(int *x) { int result = 0; int i; for (i = 0;i < 1000;++i) result += x[i]; return result; }
Counting
static volatile *const = (void ... int beforesum int result int aftersum UARTprintf("sum result,aftersum-beforesum);
Output sho Change 1000
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rget CPU core: rtex-M4F core inside microcontroller LM4F120 Launchpad.
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Example of a function that we want to optimize: adding 1000 integers mod 232. Reference implementation:
int sum(int *x) { int result = 0; int i; for (i = 0;i < 1000;++i) result += x[i]; return result; }
Counting cycles:
static volatile unsigned *const DWT_CYCCNT = (void *) 0xE0001004; ... int beforesum = *DWT_CYCCNT; int result = sum(x); int aftersum = *DWT_CYCCNT; UARTprintf("sum %d result,aftersum-beforesum);
Output shows 8012 Change 1000 to 500:
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core: inside controller Launchpad.
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Example of a function that we want to optimize: adding 1000 integers mod 232. Reference implementation:
int sum(int *x) { int result = 0; int i; for (i = 0;i < 1000;++i) result += x[i]; return result; }
Counting cycles:
static volatile unsigned *const DWT_CYCCNT = (void *) 0xE0001004; ... int beforesum = *DWT_CYCCNT; int result = sum(x); int aftersum = *DWT_CYCCNT; UARTprintf("sum %d %d\n", result,aftersum-beforesum);
Output shows 8012 cycles. Change 1000 to 500: 4012.
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Example of a function that we want to optimize: adding 1000 integers mod 232. Reference implementation:
int sum(int *x) { int result = 0; int i; for (i = 0;i < 1000;++i) result += x[i]; return result; }
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Counting cycles:
static volatile unsigned int *const DWT_CYCCNT = (void *) 0xE0001004; ... int beforesum = *DWT_CYCCNT; int result = sum(x); int aftersum = *DWT_CYCCNT; UARTprintf("sum %d %d\n", result,aftersum-beforesum);
Output shows 8012 cycles. Change 1000 to 500: 4012.
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Example of a function e want to optimize: 1000 integers mod 232. Reference implementation:
sum(int *x) result = 0; i; (i = 0;i < 1000;++i) result += x[i]; return result;
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Counting cycles:
static volatile unsigned int *const DWT_CYCCNT = (void *) 0xE0001004; ... int beforesum = *DWT_CYCCNT; int result = sum(x); int aftersum = *DWT_CYCCNT; UARTprintf("sum %d %d\n", result,aftersum-beforesum);
Output shows 8012 cycles. Change 1000 to 500: 4012. “Okay, 8 Um, are really this
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function
gers mod 232. mentation:
0; 1000;++i) x[i];
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Counting cycles:
static volatile unsigned int *const DWT_CYCCNT = (void *) 0xE0001004; ... int beforesum = *DWT_CYCCNT; int result = sum(x); int aftersum = *DWT_CYCCNT; UARTprintf("sum %d %d\n", result,aftersum-beforesum);
Output shows 8012 cycles. Change 1000 to 500: 4012. “Okay, 8 cycles per Um, are microcontrollers really this slow at
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232. mentation:
1000;++i)
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Counting cycles:
static volatile unsigned int *const DWT_CYCCNT = (void *) 0xE0001004; ... int beforesum = *DWT_CYCCNT; int result = sum(x); int aftersum = *DWT_CYCCNT; UARTprintf("sum %d %d\n", result,aftersum-beforesum);
Output shows 8012 cycles. Change 1000 to 500: 4012. “Okay, 8 cycles per addition. Um, are microcontrollers really this slow at addition?”
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Counting cycles:
static volatile unsigned int *const DWT_CYCCNT = (void *) 0xE0001004; ... int beforesum = *DWT_CYCCNT; int result = sum(x); int aftersum = *DWT_CYCCNT; UARTprintf("sum %d %d\n", result,aftersum-beforesum);
Output shows 8012 cycles. Change 1000 to 500: 4012.
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“Okay, 8 cycles per addition. Um, are microcontrollers really this slow at addition?”
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Counting cycles:
static volatile unsigned int *const DWT_CYCCNT = (void *) 0xE0001004; ... int beforesum = *DWT_CYCCNT; int result = sum(x); int aftersum = *DWT_CYCCNT; UARTprintf("sum %d %d\n", result,aftersum-beforesum);
Output shows 8012 cycles. Change 1000 to 500: 4012.
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“Okay, 8 cycles per addition. Um, are microcontrollers really this slow at addition?” Bad approach: Apply random “optimizations” (and tweak compiler options) until you get bored/frustrated. Keep the fastest results.
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Counting cycles:
static volatile unsigned int *const DWT_CYCCNT = (void *) 0xE0001004; ... int beforesum = *DWT_CYCCNT; int result = sum(x); int aftersum = *DWT_CYCCNT; UARTprintf("sum %d %d\n", result,aftersum-beforesum);
Output shows 8012 cycles. Change 1000 to 500: 4012.
4
“Okay, 8 cycles per addition. Um, are microcontrollers really this slow at addition?” Bad approach: Apply random “optimizations” (and tweak compiler options) until you get bored/frustrated. Keep the fastest results. Try -Os: 8012 cycles.
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Counting cycles:
static volatile unsigned int *const DWT_CYCCNT = (void *) 0xE0001004; ... int beforesum = *DWT_CYCCNT; int result = sum(x); int aftersum = *DWT_CYCCNT; UARTprintf("sum %d %d\n", result,aftersum-beforesum);
Output shows 8012 cycles. Change 1000 to 500: 4012.
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“Okay, 8 cycles per addition. Um, are microcontrollers really this slow at addition?” Bad approach: Apply random “optimizations” (and tweak compiler options) until you get bored/frustrated. Keep the fastest results. Try -Os: 8012 cycles. Try -O1: 8012 cycles.
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Counting cycles:
static volatile unsigned int *const DWT_CYCCNT = (void *) 0xE0001004; ... int beforesum = *DWT_CYCCNT; int result = sum(x); int aftersum = *DWT_CYCCNT; UARTprintf("sum %d %d\n", result,aftersum-beforesum);
Output shows 8012 cycles. Change 1000 to 500: 4012.
4
“Okay, 8 cycles per addition. Um, are microcontrollers really this slow at addition?” Bad approach: Apply random “optimizations” (and tweak compiler options) until you get bored/frustrated. Keep the fastest results. Try -Os: 8012 cycles. Try -O1: 8012 cycles. Try -O2: 8012 cycles.
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Counting cycles:
static volatile unsigned int *const DWT_CYCCNT = (void *) 0xE0001004; ... int beforesum = *DWT_CYCCNT; int result = sum(x); int aftersum = *DWT_CYCCNT; UARTprintf("sum %d %d\n", result,aftersum-beforesum);
Output shows 8012 cycles. Change 1000 to 500: 4012.
4
“Okay, 8 cycles per addition. Um, are microcontrollers really this slow at addition?” Bad approach: Apply random “optimizations” (and tweak compiler options) until you get bored/frustrated. Keep the fastest results. Try -Os: 8012 cycles. Try -O1: 8012 cycles. Try -O2: 8012 cycles. Try -O3: 8012 cycles.
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Counting cycles:
volatile unsigned int *const DWT_CYCCNT (void *) 0xE0001004; beforesum = *DWT_CYCCNT; result = sum(x); aftersum = *DWT_CYCCNT; UARTprintf("sum %d %d\n", result,aftersum-beforesum);
Output shows 8012 cycles. Change 1000 to 500: 4012.
4
“Okay, 8 cycles per addition. Um, are microcontrollers really this slow at addition?” Bad approach: Apply random “optimizations” (and tweak compiler options) until you get bored/frustrated. Keep the fastest results. Try -Os: 8012 cycles. Try -O1: 8012 cycles. Try -O2: 8012 cycles. Try -O3: 8012 cycles. Try moving
int sum(int { int result int i; for (i result return }
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unsigned int DWT_CYCCNT 0xE0001004; *DWT_CYCCNT; sum(x); *DWT_CYCCNT; %d %d\n", result,aftersum-beforesum);
8012 cycles. 500: 4012.
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“Okay, 8 cycles per addition. Um, are microcontrollers really this slow at addition?” Bad approach: Apply random “optimizations” (and tweak compiler options) until you get bored/frustrated. Keep the fastest results. Try -Os: 8012 cycles. Try -O1: 8012 cycles. Try -O2: 8012 cycles. Try -O3: 8012 cycles. Try moving the pointer:
int sum(int *x) { int result = 0; int i; for (i = 0;i < result += *x++; return result; }
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int *DWT_CYCCNT; *DWT_CYCCNT; %d\n", result,aftersum-beforesum);
cycles. 4012.
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“Okay, 8 cycles per addition. Um, are microcontrollers really this slow at addition?” Bad approach: Apply random “optimizations” (and tweak compiler options) until you get bored/frustrated. Keep the fastest results. Try -Os: 8012 cycles. Try -O1: 8012 cycles. Try -O2: 8012 cycles. Try -O3: 8012 cycles. Try moving the pointer:
int sum(int *x) { int result = 0; int i; for (i = 0;i < 1000;++i) result += *x++; return result; }
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“Okay, 8 cycles per addition. Um, are microcontrollers really this slow at addition?” Bad approach: Apply random “optimizations” (and tweak compiler options) until you get bored/frustrated. Keep the fastest results. Try -Os: 8012 cycles. Try -O1: 8012 cycles. Try -O2: 8012 cycles. Try -O3: 8012 cycles.
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Try moving the pointer:
int sum(int *x) { int result = 0; int i; for (i = 0;i < 1000;++i) result += *x++; return result; }
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“Okay, 8 cycles per addition. Um, are microcontrollers really this slow at addition?” Bad approach: Apply random “optimizations” (and tweak compiler options) until you get bored/frustrated. Keep the fastest results. Try -Os: 8012 cycles. Try -O1: 8012 cycles. Try -O2: 8012 cycles. Try -O3: 8012 cycles.
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Try moving the pointer:
int sum(int *x) { int result = 0; int i; for (i = 0;i < 1000;++i) result += *x++; return result; }
8010 cycles.
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, 8 cycles per addition. re microcontrollers this slow at addition?” approach: random “optimizations” weak compiler options)
the fastest results. : 8012 cycles. : 8012 cycles. : 8012 cycles. : 8012 cycles.
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Try moving the pointer:
int sum(int *x) { int result = 0; int i; for (i = 0;i < 1000;++i) result += *x++; return result; }
8010 cycles. Try counting
int sum(int { int result int i; for (i result return }
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per addition. controllers at addition?” “optimizations” compiler options) red/frustrated. results. cycles. cycles. cycles. cycles.
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Try moving the pointer:
int sum(int *x) { int result = 0; int i; for (i = 0;i < 1000;++i) result += *x++; return result; }
8010 cycles. Try counting down:
int sum(int *x) { int result = 0; int i; for (i = 1000;i result += *x++; return result; }
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addition. addition?” tions”
red/frustrated.
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Try moving the pointer:
int sum(int *x) { int result = 0; int i; for (i = 0;i < 1000;++i) result += *x++; return result; }
8010 cycles. Try counting down:
int sum(int *x) { int result = 0; int i; for (i = 1000;i > 0;--i) result += *x++; return result; }
5
Try moving the pointer:
int sum(int *x) { int result = 0; int i; for (i = 0;i < 1000;++i) result += *x++; return result; }
8010 cycles.
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Try counting down:
int sum(int *x) { int result = 0; int i; for (i = 1000;i > 0;--i) result += *x++; return result; }
5
Try moving the pointer:
int sum(int *x) { int result = 0; int i; for (i = 0;i < 1000;++i) result += *x++; return result; }
8010 cycles.
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Try counting down:
int sum(int *x) { int result = 0; int i; for (i = 1000;i > 0;--i) result += *x++; return result; }
8010 cycles.
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moving the pointer:
sum(int *x) result = 0; i; (i = 0;i < 1000;++i) result += *x++; return result;
cycles.
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Try counting down:
int sum(int *x) { int result = 0; int i; for (i = 1000;i > 0;--i) result += *x++; return result; }
8010 cycles. Try using
int sum(int { int result int *y while result return }
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pointer:
0; 1000;++i) *x++;
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Try counting down:
int sum(int *x) { int result = 0; int i; for (i = 1000;i > 0;--i) result += *x++; return result; }
8010 cycles. Try using an end p
int sum(int *x) { int result = 0; int *y = x + 1000; while (x != y) result += *x++; return result; }
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1000;++i)
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Try counting down:
int sum(int *x) { int result = 0; int i; for (i = 1000;i > 0;--i) result += *x++; return result; }
8010 cycles. Try using an end pointer:
int sum(int *x) { int result = 0; int *y = x + 1000; while (x != y) result += *x++; return result; }
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Try counting down:
int sum(int *x) { int result = 0; int i; for (i = 1000;i > 0;--i) result += *x++; return result; }
8010 cycles.
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Try using an end pointer:
int sum(int *x) { int result = 0; int *y = x + 1000; while (x != y) result += *x++; return result; }
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Try counting down:
int sum(int *x) { int result = 0; int i; for (i = 1000;i > 0;--i) result += *x++; return result; }
8010 cycles.
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Try using an end pointer:
int sum(int *x) { int result = 0; int *y = x + 1000; while (x != y) result += *x++; return result; }
8010 cycles.
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counting down:
sum(int *x) result = 0; i; (i = 1000;i > 0;--i) result += *x++; return result;
cycles.
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Try using an end pointer:
int sum(int *x) { int result = 0; int *y = x + 1000; while (x != y) result += *x++; return result; }
8010 cycles. Back to
int sum(int { int result int i; for (i result result } return }
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wn:
0; 1000;i > 0;--i) *x++;
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Try using an end pointer:
int sum(int *x) { int result = 0; int *y = x + 1000; while (x != y) result += *x++; return result; }
8010 cycles. Back to original. T
int sum(int *x) { int result = 0; int i; for (i = 0;i < result += x[i]; result += x[i } return result; }
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0;--i)
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Try using an end pointer:
int sum(int *x) { int result = 0; int *y = x + 1000; while (x != y) result += *x++; return result; }
8010 cycles. Back to original. Try unrolling:
int sum(int *x) { int result = 0; int i; for (i = 0;i < 1000;i += result += x[i]; result += x[i + 1]; } return result; }
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Try using an end pointer:
int sum(int *x) { int result = 0; int *y = x + 1000; while (x != y) result += *x++; return result; }
8010 cycles.
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Back to original. Try unrolling:
int sum(int *x) { int result = 0; int i; for (i = 0;i < 1000;i += 2) { result += x[i]; result += x[i + 1]; } return result; }
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Try using an end pointer:
int sum(int *x) { int result = 0; int *y = x + 1000; while (x != y) result += *x++; return result; }
8010 cycles.
8
Back to original. Try unrolling:
int sum(int *x) { int result = 0; int i; for (i = 0;i < 1000;i += 2) { result += x[i]; result += x[i + 1]; } return result; }
5016 cycles.
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using an end pointer:
sum(int *x) result = 0; *y = x + 1000; (x != y) result += *x++; return result;
cycles.
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Back to original. Try unrolling:
int sum(int *x) { int result = 0; int i; for (i = 0;i < 1000;i += 2) { result += x[i]; result += x[i + 1]; } return result; }
5016 cycles.
int sum(int { int result int i; for (i result result result result result } return }
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pointer:
0; 1000; *x++;
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Back to original. Try unrolling:
int sum(int *x) { int result = 0; int i; for (i = 0;i < 1000;i += 2) { result += x[i]; result += x[i + 1]; } return result; }
5016 cycles.
int sum(int *x) { int result = 0; int i; for (i = 0;i < result += x[i]; result += x[i result += x[i result += x[i result += x[i } return result; }
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Back to original. Try unrolling:
int sum(int *x) { int result = 0; int i; for (i = 0;i < 1000;i += 2) { result += x[i]; result += x[i + 1]; } return result; }
5016 cycles.
int sum(int *x) { int result = 0; int i; for (i = 0;i < 1000;i += result += x[i]; result += x[i + 1]; result += x[i + 2]; result += x[i + 3]; result += x[i + 4]; } return result; }
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Back to original. Try unrolling:
int sum(int *x) { int result = 0; int i; for (i = 0;i < 1000;i += 2) { result += x[i]; result += x[i + 1]; } return result; }
5016 cycles.
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int sum(int *x) { int result = 0; int i; for (i = 0;i < 1000;i += 5) { result += x[i]; result += x[i + 1]; result += x[i + 2]; result += x[i + 3]; result += x[i + 4]; } return result; }
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to original. Try unrolling:
sum(int *x) result = 0; i; (i = 0;i < 1000;i += 2) { result += x[i]; result += x[i + 1]; return result;
cycles.
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int sum(int *x) { int result = 0; int i; for (i = 0;i < 1000;i += 5) { result += x[i]; result += x[i + 1]; result += x[i + 2]; result += x[i + 3]; result += x[i + 4]; } return result; }
4016 cycles
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0; 1000;i += 2) { x[i]; x[i + 1];
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int sum(int *x) { int result = 0; int i; for (i = 0;i < 1000;i += 5) { result += x[i]; result += x[i + 1]; result += x[i + 2]; result += x[i + 3]; result += x[i + 4]; } return result; }
4016 cycles. Are w
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unrolling:
+= 2) {
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int sum(int *x) { int result = 0; int i; for (i = 0;i < 1000;i += 5) { result += x[i]; result += x[i + 1]; result += x[i + 2]; result += x[i + 3]; result += x[i + 4]; } return result; }
4016 cycles. Are we done no
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int sum(int *x) { int result = 0; int i; for (i = 0;i < 1000;i += 5) { result += x[i]; result += x[i + 1]; result += x[i + 2]; result += x[i + 3]; result += x[i + 4]; } return result; }
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4016 cycles. Are we done now?
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int sum(int *x) { int result = 0; int i; for (i = 0;i < 1000;i += 5) { result += x[i]; result += x[i + 1]; result += x[i + 2]; result += x[i + 3]; result += x[i + 4]; } return result; }
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4016 cycles. Are we done now? Most random “optimizations” that we tried seem useless. Can spend time trying more. Does frustration level tell us that we’re close to optimal?
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int sum(int *x) { int result = 0; int i; for (i = 0;i < 1000;i += 5) { result += x[i]; result += x[i + 1]; result += x[i + 2]; result += x[i + 3]; result += x[i + 4]; } return result; }
10
4016 cycles. Are we done now? Most random “optimizations” that we tried seem useless. Can spend time trying more. Does frustration level tell us that we’re close to optimal? Good approach: Figure out lower bound for cycles spent on arithmetic etc. Understand gap between lower bound and observed time. Let’s try this approach.
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sum(int *x) result = 0; i; (i = 0;i < 1000;i += 5) { result += x[i]; result += x[i + 1]; result += x[i + 2]; result += x[i + 3]; result += x[i + 4]; return result;
10
4016 cycles. Are we done now? Most random “optimizations” that we tried seem useless. Can spend time trying more. Does frustration level tell us that we’re close to optimal? Good approach: Figure out lower bound for cycles spent on arithmetic etc. Understand gap between lower bound and observed time. Let’s try this approach. Find “ARM Technical Rely on Wikip M4F = M4 Manual sa “implements architecture Points to Architecture which defines e.g., “ADD” First manual ADD tak
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0; 1000;i += 5) { x[i]; x[i + 1]; x[i + 2]; x[i + 3]; x[i + 4];
10
4016 cycles. Are we done now? Most random “optimizations” that we tried seem useless. Can spend time trying more. Does frustration level tell us that we’re close to optimal? Good approach: Figure out lower bound for cycles spent on arithmetic etc. Understand gap between lower bound and observed time. Let’s try this approach. Find “ARM Cortex-M4 Technical Reference Rely on Wikipedia M4F = M4 + floating-p Manual says that Co “implements the ARMv7E-M architecture profile”. Points to the “ARMv7-M Architecture Reference which defines instructions: e.g., “ADD” for 32-bit First manual says that ADD takes just 1 cycle.
9
+= 5) {
10
4016 cycles. Are we done now? Most random “optimizations” that we tried seem useless. Can spend time trying more. Does frustration level tell us that we’re close to optimal? Good approach: Figure out lower bound for cycles spent on arithmetic etc. Understand gap between lower bound and observed time. Let’s try this approach. Find “ARM Cortex-M4 Processo Technical Reference Manual”. Rely on Wikipedia comment M4F = M4 + floating-point Manual says that Cortex-M4 “implements the ARMv7E-M architecture profile”. Points to the “ARMv7-M Architecture Reference Manual”, which defines instructions: e.g., “ADD” for 32-bit addition. First manual says that ADD takes just 1 cycle.
10
4016 cycles. Are we done now? Most random “optimizations” that we tried seem useless. Can spend time trying more. Does frustration level tell us that we’re close to optimal? Good approach: Figure out lower bound for cycles spent on arithmetic etc. Understand gap between lower bound and observed time. Let’s try this approach.
11
Find “ARM Cortex-M4 Processor Technical Reference Manual”. Rely on Wikipedia comment that M4F = M4 + floating-point unit. Manual says that Cortex-M4 “implements the ARMv7E-M architecture profile”. Points to the “ARMv7-M Architecture Reference Manual”, which defines instructions: e.g., “ADD” for 32-bit addition. First manual says that ADD takes just 1 cycle.
10
random “optimizations” e tried seem useless. end time trying more. frustration level tell us e’re close to optimal? approach:
spent on arithmetic etc. Understand gap between bound and observed time. try this approach.
11
Find “ARM Cortex-M4 Processor Technical Reference Manual”. Rely on Wikipedia comment that M4F = M4 + floating-point unit. Manual says that Cortex-M4 “implements the ARMv7E-M architecture profile”. Points to the “ARMv7-M Architecture Reference Manual”, which defines instructions: e.g., “ADD” for 32-bit addition. First manual says that ADD takes just 1 cycle. Inputs and “integer has 16 integer special-purp and “program Each eleme be “loaded” Basic load Manual sa a note ab Then mo instruction address not then it saves
10
we done now? “optimizations” seem useless. trying more. level tell us to optimal? bound for arithmetic etc. between
approach.
11
Find “ARM Cortex-M4 Processor Technical Reference Manual”. Rely on Wikipedia comment that M4F = M4 + floating-point unit. Manual says that Cortex-M4 “implements the ARMv7E-M architecture profile”. Points to the “ARMv7-M Architecture Reference Manual”, which defines instructions: e.g., “ADD” for 32-bit addition. First manual says that ADD takes just 1 cycle. Inputs and output “integer registers”. has 16 integer registers, special-purpose “stack and “program counter”. Each element of x be “loaded” into a Basic load instruction: Manual says 2 cycles a note about “pipelining”. Then more explanation: instruction is also address not based then it saves 1 cycle.
10
now? “optimizations” useless. re. us
r etc. time.
11
Find “ARM Cortex-M4 Processor Technical Reference Manual”. Rely on Wikipedia comment that M4F = M4 + floating-point unit. Manual says that Cortex-M4 “implements the ARMv7E-M architecture profile”. Points to the “ARMv7-M Architecture Reference Manual”, which defines instructions: e.g., “ADD” for 32-bit addition. First manual says that ADD takes just 1 cycle. Inputs and output of ADD a “integer registers”. ARMv7- has 16 integer registers, including special-purpose “stack pointer” and “program counter”. Each element of x array needs be “loaded” into a register. Basic load instruction: LDR. Manual says 2 cycles but adds a note about “pipelining”. Then more explanation: if next instruction is also LDR (with address not based on first LDR then it saves 1 cycle.
11
Find “ARM Cortex-M4 Processor Technical Reference Manual”. Rely on Wikipedia comment that M4F = M4 + floating-point unit. Manual says that Cortex-M4 “implements the ARMv7E-M architecture profile”. Points to the “ARMv7-M Architecture Reference Manual”, which defines instructions: e.g., “ADD” for 32-bit addition. First manual says that ADD takes just 1 cycle.
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Inputs and output of ADD are “integer registers”. ARMv7-M has 16 integer registers, including special-purpose “stack pointer” and “program counter”. Each element of x array needs to be “loaded” into a register. Basic load instruction: LDR. Manual says 2 cycles but adds a note about “pipelining”. Then more explanation: if next instruction is also LDR (with address not based on first LDR) then it saves 1 cycle.
11
“ARM Cortex-M4 Processor echnical Reference Manual”.
M4 + floating-point unit. Manual says that Cortex-M4 “implements the ARMv7E-M rchitecture profile”. to the “ARMv7-M Architecture Reference Manual”, defines instructions: “ADD” for 32-bit addition. manual says that takes just 1 cycle.
12
Inputs and output of ADD are “integer registers”. ARMv7-M has 16 integer registers, including special-purpose “stack pointer” and “program counter”. Each element of x array needs to be “loaded” into a register. Basic load instruction: LDR. Manual says 2 cycles but adds a note about “pipelining”. Then more explanation: if next instruction is also LDR (with address not based on first LDR) then it saves 1 cycle. n consecutive takes only (“more multiple pipelined Can achieve in other but nothing Lower boun 2n + 1 cycles, n cycles Why observed non-consecutive costs of
11
rtex-M4 Processor Reference Manual”. edia comment that floating-point unit. that Cortex-M4 ARMv7E-M rofile”. “ARMv7-M Reference Manual”, instructions: 32-bit addition. ys that 1 cycle.
12
Inputs and output of ADD are “integer registers”. ARMv7-M has 16 integer registers, including special-purpose “stack pointer” and “program counter”. Each element of x array needs to be “loaded” into a register. Basic load instruction: LDR. Manual says 2 cycles but adds a note about “pipelining”. Then more explanation: if next instruction is also LDR (with address not based on first LDR) then it saves 1 cycle. n consecutive LDRs takes only n + 1 cycles (“more multiple LDRs pipelined together”). Can achieve this sp in other ways (LDRD, but nothing seems Lower bound for n 2n + 1 cycles, including n cycles of arithmetic. Why observed time non-consecutive LDR costs of manipulating
11
Processor Manual”. comment that
rtex-M4 ARMv7E-M Manual”, addition.
12
Inputs and output of ADD are “integer registers”. ARMv7-M has 16 integer registers, including special-purpose “stack pointer” and “program counter”. Each element of x array needs to be “loaded” into a register. Basic load instruction: LDR. Manual says 2 cycles but adds a note about “pipelining”. Then more explanation: if next instruction is also LDR (with address not based on first LDR) then it saves 1 cycle. n consecutive LDRs takes only n + 1 cycles (“more multiple LDRs can b pipelined together”). Can achieve this speed in other ways (LDRD, LDM) but nothing seems faster. Lower bound for n LDR + n ADD: 2n + 1 cycles, including n cycles of arithmetic. Why observed time is higher: non-consecutive LDRs; costs of manipulating i.
12
Inputs and output of ADD are “integer registers”. ARMv7-M has 16 integer registers, including special-purpose “stack pointer” and “program counter”. Each element of x array needs to be “loaded” into a register. Basic load instruction: LDR. Manual says 2 cycles but adds a note about “pipelining”. Then more explanation: if next instruction is also LDR (with address not based on first LDR) then it saves 1 cycle.
13
n consecutive LDRs takes only n + 1 cycles (“more multiple LDRs can be pipelined together”). Can achieve this speed in other ways (LDRD, LDM) but nothing seems faster. Lower bound for n LDR + n ADD: 2n + 1 cycles, including n cycles of arithmetic. Why observed time is higher: non-consecutive LDRs; costs of manipulating i.
12
and output of ADD are “integer registers”. ARMv7-M integer registers, including ecial-purpose “stack pointer” rogram counter”. element of x array needs to “loaded” into a register. load instruction: LDR. Manual says 2 cycles but adds about “pipelining”. more explanation: if next instruction is also LDR (with address not based on first LDR) saves 1 cycle.
13
n consecutive LDRs takes only n + 1 cycles (“more multiple LDRs can be pipelined together”). Can achieve this speed in other ways (LDRD, LDM) but nothing seems faster. Lower bound for n LDR + n ADD: 2n + 1 cycles, including n cycles of arithmetic. Why observed time is higher: non-consecutive LDRs; costs of manipulating i. 2281 cycles
y = x + p = x result = loop: xi9 = xi8 = xi7 = xi6 = xi5 = xi4 = xi3 = xi2 =
12
registers”. ARMv7-M registers, including “stack pointer” counter”. x array needs to a register. instruction: LDR. cycles but adds “pipelining”. explanation: if next also LDR (with based on first LDR) cycle.
13
n consecutive LDRs takes only n + 1 cycles (“more multiple LDRs can be pipelined together”). Can achieve this speed in other ways (LDRD, LDM) but nothing seems faster. Lower bound for n LDR + n ADD: 2n + 1 cycles, including n cycles of arithmetic. Why observed time is higher: non-consecutive LDRs; costs of manipulating i. 2281 cycles using ldr.w
y = x + 4000 p = x result = 0 loop: xi9 = *(uint32 xi8 = *(uint32 xi7 = *(uint32 xi6 = *(uint32 xi5 = *(uint32 xi4 = *(uint32 xi3 = *(uint32 xi2 = *(uint32
12
are ARMv7-M including
needs to register. DR. adds next (with LDR)
13
n consecutive LDRs takes only n + 1 cycles (“more multiple LDRs can be pipelined together”). Can achieve this speed in other ways (LDRD, LDM) but nothing seems faster. Lower bound for n LDR + n ADD: 2n + 1 cycles, including n cycles of arithmetic. Why observed time is higher: non-consecutive LDRs; costs of manipulating i. 2281 cycles using ldr.w:
y = x + 4000 p = x result = 0 loop: xi9 = *(uint32 *) (p + xi8 = *(uint32 *) (p + xi7 = *(uint32 *) (p + xi6 = *(uint32 *) (p + xi5 = *(uint32 *) (p + xi4 = *(uint32 *) (p + xi3 = *(uint32 *) (p + xi2 = *(uint32 *) (p +
13
n consecutive LDRs takes only n + 1 cycles (“more multiple LDRs can be pipelined together”). Can achieve this speed in other ways (LDRD, LDM) but nothing seems faster. Lower bound for n LDR + n ADD: 2n + 1 cycles, including n cycles of arithmetic. Why observed time is higher: non-consecutive LDRs; costs of manipulating i.
14
2281 cycles using ldr.w:
y = x + 4000 p = x result = 0 loop: xi9 = *(uint32 *) (p + 76) xi8 = *(uint32 *) (p + 72) xi7 = *(uint32 *) (p + 68) xi6 = *(uint32 *) (p + 64) xi5 = *(uint32 *) (p + 60) xi4 = *(uint32 *) (p + 56) xi3 = *(uint32 *) (p + 52) xi2 = *(uint32 *) (p + 48)
13
consecutive LDRs
re multiple LDRs can be elined together”). achieve this speed
nothing seems faster. bound for n LDR + n ADD: cycles, including cycles of arithmetic.
non-consecutive LDRs;
14
2281 cycles using ldr.w:
y = x + 4000 p = x result = 0 loop: xi9 = *(uint32 *) (p + 76) xi8 = *(uint32 *) (p + 72) xi7 = *(uint32 *) (p + 68) xi6 = *(uint32 *) (p + 64) xi5 = *(uint32 *) (p + 60) xi4 = *(uint32 *) (p + 56) xi3 = *(uint32 *) (p + 52) xi2 = *(uint32 *) (p + 48) xi1 = xi0 = result result result result result result result result result result xi9 = xi8 = xi7 =
13
Rs cycles LDRs can be together”). speed (LDRD, LDM) seems faster. n LDR + n ADD: including rithmetic. time is higher: LDRs; manipulating i.
14
2281 cycles using ldr.w:
y = x + 4000 p = x result = 0 loop: xi9 = *(uint32 *) (p + 76) xi8 = *(uint32 *) (p + 72) xi7 = *(uint32 *) (p + 68) xi6 = *(uint32 *) (p + 64) xi5 = *(uint32 *) (p + 60) xi4 = *(uint32 *) (p + 56) xi3 = *(uint32 *) (p + 52) xi2 = *(uint32 *) (p + 48) xi1 = *(uint32 xi0 = *(uint32 result += xi9 result += xi8 result += xi7 result += xi6 result += xi5 result += xi4 result += xi3 result += xi2 result += xi1 result += xi0 xi9 = *(uint32 xi8 = *(uint32 xi7 = *(uint32
13
be LDM) n ADD: higher:
14
2281 cycles using ldr.w:
y = x + 4000 p = x result = 0 loop: xi9 = *(uint32 *) (p + 76) xi8 = *(uint32 *) (p + 72) xi7 = *(uint32 *) (p + 68) xi6 = *(uint32 *) (p + 64) xi5 = *(uint32 *) (p + 60) xi4 = *(uint32 *) (p + 56) xi3 = *(uint32 *) (p + 52) xi2 = *(uint32 *) (p + 48) xi1 = *(uint32 *) (p + xi0 = *(uint32 *) (p + result += xi9 result += xi8 result += xi7 result += xi6 result += xi5 result += xi4 result += xi3 result += xi2 result += xi1 result += xi0 xi9 = *(uint32 *) (p + xi8 = *(uint32 *) (p + xi7 = *(uint32 *) (p +
14
2281 cycles using ldr.w:
y = x + 4000 p = x result = 0 loop: xi9 = *(uint32 *) (p + 76) xi8 = *(uint32 *) (p + 72) xi7 = *(uint32 *) (p + 68) xi6 = *(uint32 *) (p + 64) xi5 = *(uint32 *) (p + 60) xi4 = *(uint32 *) (p + 56) xi3 = *(uint32 *) (p + 52) xi2 = *(uint32 *) (p + 48)
15
xi1 = *(uint32 *) (p + 44) xi0 = *(uint32 *) (p + 40) result += xi9 result += xi8 result += xi7 result += xi6 result += xi5 result += xi4 result += xi3 result += xi2 result += xi1 result += xi0 xi9 = *(uint32 *) (p + 36) xi8 = *(uint32 *) (p + 32) xi7 = *(uint32 *) (p + 28)
14
cycles using ldr.w:
4000 = 0 *(uint32 *) (p + 76) *(uint32 *) (p + 72) *(uint32 *) (p + 68) *(uint32 *) (p + 64) *(uint32 *) (p + 60) *(uint32 *) (p + 56) *(uint32 *) (p + 52) *(uint32 *) (p + 48)
15
xi1 = *(uint32 *) (p + 44) xi0 = *(uint32 *) (p + 40) result += xi9 result += xi8 result += xi7 result += xi6 result += xi5 result += xi4 result += xi3 result += xi2 result += xi1 result += xi0 xi9 = *(uint32 *) (p + 36) xi8 = *(uint32 *) (p + 32) xi7 = *(uint32 *) (p + 28) xi6 = xi5 = xi4 = xi3 = xi2 = xi1 = xi0 = result result result result result result result result
14
using ldr.w:
*) (p + 76) *) (p + 72) *) (p + 68) *) (p + 64) *) (p + 60) *) (p + 56) *) (p + 52) *) (p + 48)
15
xi1 = *(uint32 *) (p + 44) xi0 = *(uint32 *) (p + 40) result += xi9 result += xi8 result += xi7 result += xi6 result += xi5 result += xi4 result += xi3 result += xi2 result += xi1 result += xi0 xi9 = *(uint32 *) (p + 36) xi8 = *(uint32 *) (p + 32) xi7 = *(uint32 *) (p + 28) xi6 = *(uint32 xi5 = *(uint32 xi4 = *(uint32 xi3 = *(uint32 xi2 = *(uint32 xi1 = *(uint32 xi0 = *(uint32 result += xi9 result += xi8 result += xi7 result += xi6 result += xi5 result += xi4 result += xi3 result += xi2
14
76) 72) 68) 64) 60) 56) 52) 48)
15
xi1 = *(uint32 *) (p + 44) xi0 = *(uint32 *) (p + 40) result += xi9 result += xi8 result += xi7 result += xi6 result += xi5 result += xi4 result += xi3 result += xi2 result += xi1 result += xi0 xi9 = *(uint32 *) (p + 36) xi8 = *(uint32 *) (p + 32) xi7 = *(uint32 *) (p + 28) xi6 = *(uint32 *) (p + xi5 = *(uint32 *) (p + xi4 = *(uint32 *) (p + xi3 = *(uint32 *) (p + xi2 = *(uint32 *) (p + xi1 = *(uint32 *) (p + xi0 = *(uint32 *) p; p result += xi9 result += xi8 result += xi7 result += xi6 result += xi5 result += xi4 result += xi3 result += xi2
15
xi1 = *(uint32 *) (p + 44) xi0 = *(uint32 *) (p + 40) result += xi9 result += xi8 result += xi7 result += xi6 result += xi5 result += xi4 result += xi3 result += xi2 result += xi1 result += xi0 xi9 = *(uint32 *) (p + 36) xi8 = *(uint32 *) (p + 32) xi7 = *(uint32 *) (p + 28)
16
xi6 = *(uint32 *) (p + 24) xi5 = *(uint32 *) (p + 20) xi4 = *(uint32 *) (p + 16) xi3 = *(uint32 *) (p + 12) xi2 = *(uint32 *) (p + 8) xi1 = *(uint32 *) (p + 4) xi0 = *(uint32 *) p; p += 160 result += xi9 result += xi8 result += xi7 result += xi6 result += xi5 result += xi4 result += xi3 result += xi2
15
*(uint32 *) (p + 44) *(uint32 *) (p + 40) result += xi9 result += xi8 result += xi7 result += xi6 result += xi5 result += xi4 result += xi3 result += xi2 result += xi1 result += xi0 *(uint32 *) (p + 36) *(uint32 *) (p + 32) *(uint32 *) (p + 28)
16
xi6 = *(uint32 *) (p + 24) xi5 = *(uint32 *) (p + 20) xi4 = *(uint32 *) (p + 16) xi3 = *(uint32 *) (p + 12) xi2 = *(uint32 *) (p + 8) xi1 = *(uint32 *) (p + 4) xi0 = *(uint32 *) p; p += 160 result += xi9 result += xi8 result += xi7 result += xi6 result += xi5 result += xi4 result += xi3 result += xi2 result result xi9 = xi8 = xi7 = xi6 = xi5 = xi4 = xi3 = xi2 = xi1 = xi0 = result result result
15
*) (p + 44) *) (p + 40) *) (p + 36) *) (p + 32) *) (p + 28)
16
xi6 = *(uint32 *) (p + 24) xi5 = *(uint32 *) (p + 20) xi4 = *(uint32 *) (p + 16) xi3 = *(uint32 *) (p + 12) xi2 = *(uint32 *) (p + 8) xi1 = *(uint32 *) (p + 4) xi0 = *(uint32 *) p; p += 160 result += xi9 result += xi8 result += xi7 result += xi6 result += xi5 result += xi4 result += xi3 result += xi2 result += xi1 result += xi0 xi9 = *(uint32 xi8 = *(uint32 xi7 = *(uint32 xi6 = *(uint32 xi5 = *(uint32 xi4 = *(uint32 xi3 = *(uint32 xi2 = *(uint32 xi1 = *(uint32 xi0 = *(uint32 result += xi9 result += xi8 result += xi7
15
44) 40) 36) 32) 28)
16
xi6 = *(uint32 *) (p + 24) xi5 = *(uint32 *) (p + 20) xi4 = *(uint32 *) (p + 16) xi3 = *(uint32 *) (p + 12) xi2 = *(uint32 *) (p + 8) xi1 = *(uint32 *) (p + 4) xi0 = *(uint32 *) p; p += 160 result += xi9 result += xi8 result += xi7 result += xi6 result += xi5 result += xi4 result += xi3 result += xi2 result += xi1 result += xi0 xi9 = *(uint32 *) (p - xi8 = *(uint32 *) (p - xi7 = *(uint32 *) (p - xi6 = *(uint32 *) (p - xi5 = *(uint32 *) (p - xi4 = *(uint32 *) (p - xi3 = *(uint32 *) (p - xi2 = *(uint32 *) (p - xi1 = *(uint32 *) (p - xi0 = *(uint32 *) (p - result += xi9 result += xi8 result += xi7
16
xi6 = *(uint32 *) (p + 24) xi5 = *(uint32 *) (p + 20) xi4 = *(uint32 *) (p + 16) xi3 = *(uint32 *) (p + 12) xi2 = *(uint32 *) (p + 8) xi1 = *(uint32 *) (p + 4) xi0 = *(uint32 *) p; p += 160 result += xi9 result += xi8 result += xi7 result += xi6 result += xi5 result += xi4 result += xi3 result += xi2
17
result += xi1 result += xi0 xi9 = *(uint32 *) (p - 4) xi8 = *(uint32 *) (p - 8) xi7 = *(uint32 *) (p - 12) xi6 = *(uint32 *) (p - 16) xi5 = *(uint32 *) (p - 20) xi4 = *(uint32 *) (p - 24) xi3 = *(uint32 *) (p - 28) xi2 = *(uint32 *) (p - 32) xi1 = *(uint32 *) (p - 36) xi0 = *(uint32 *) (p - 40) result += xi9 result += xi8 result += xi7
16
*(uint32 *) (p + 24) *(uint32 *) (p + 20) *(uint32 *) (p + 16) *(uint32 *) (p + 12) *(uint32 *) (p + 8) *(uint32 *) (p + 4) *(uint32 *) p; p += 160 result += xi9 result += xi8 result += xi7 result += xi6 result += xi5 result += xi4 result += xi3 result += xi2
17
result += xi1 result += xi0 xi9 = *(uint32 *) (p - 4) xi8 = *(uint32 *) (p - 8) xi7 = *(uint32 *) (p - 12) xi6 = *(uint32 *) (p - 16) xi5 = *(uint32 *) (p - 20) xi4 = *(uint32 *) (p - 24) xi3 = *(uint32 *) (p - 28) xi2 = *(uint32 *) (p - 32) xi1 = *(uint32 *) (p - 36) xi0 = *(uint32 *) (p - 40) result += xi9 result += xi8 result += xi7 result result result result result result result xi9 = xi8 = xi7 = xi6 = xi5 = xi4 = xi3 = xi2 =
16
*) (p + 24) *) (p + 20) *) (p + 16) *) (p + 12) *) (p + 8) *) (p + 4) *) p; p += 160
17
result += xi1 result += xi0 xi9 = *(uint32 *) (p - 4) xi8 = *(uint32 *) (p - 8) xi7 = *(uint32 *) (p - 12) xi6 = *(uint32 *) (p - 16) xi5 = *(uint32 *) (p - 20) xi4 = *(uint32 *) (p - 24) xi3 = *(uint32 *) (p - 28) xi2 = *(uint32 *) (p - 32) xi1 = *(uint32 *) (p - 36) xi0 = *(uint32 *) (p - 40) result += xi9 result += xi8 result += xi7 result += xi6 result += xi5 result += xi4 result += xi3 result += xi2 result += xi1 result += xi0 xi9 = *(uint32 xi8 = *(uint32 xi7 = *(uint32 xi6 = *(uint32 xi5 = *(uint32 xi4 = *(uint32 xi3 = *(uint32 xi2 = *(uint32
16
24) 20) 16) 12) 8) 4) += 160
17
result += xi1 result += xi0 xi9 = *(uint32 *) (p - 4) xi8 = *(uint32 *) (p - 8) xi7 = *(uint32 *) (p - 12) xi6 = *(uint32 *) (p - 16) xi5 = *(uint32 *) (p - 20) xi4 = *(uint32 *) (p - 24) xi3 = *(uint32 *) (p - 28) xi2 = *(uint32 *) (p - 32) xi1 = *(uint32 *) (p - 36) xi0 = *(uint32 *) (p - 40) result += xi9 result += xi8 result += xi7 result += xi6 result += xi5 result += xi4 result += xi3 result += xi2 result += xi1 result += xi0 xi9 = *(uint32 *) (p - xi8 = *(uint32 *) (p - xi7 = *(uint32 *) (p - xi6 = *(uint32 *) (p - xi5 = *(uint32 *) (p - xi4 = *(uint32 *) (p - xi3 = *(uint32 *) (p - xi2 = *(uint32 *) (p -
17
result += xi1 result += xi0 xi9 = *(uint32 *) (p - 4) xi8 = *(uint32 *) (p - 8) xi7 = *(uint32 *) (p - 12) xi6 = *(uint32 *) (p - 16) xi5 = *(uint32 *) (p - 20) xi4 = *(uint32 *) (p - 24) xi3 = *(uint32 *) (p - 28) xi2 = *(uint32 *) (p - 32) xi1 = *(uint32 *) (p - 36) xi0 = *(uint32 *) (p - 40) result += xi9 result += xi8 result += xi7
18
result += xi6 result += xi5 result += xi4 result += xi3 result += xi2 result += xi1 result += xi0 xi9 = *(uint32 *) (p - 44) xi8 = *(uint32 *) (p - 48) xi7 = *(uint32 *) (p - 52) xi6 = *(uint32 *) (p - 56) xi5 = *(uint32 *) (p - 60) xi4 = *(uint32 *) (p - 64) xi3 = *(uint32 *) (p - 68) xi2 = *(uint32 *) (p - 72)
17
result += xi1 result += xi0 *(uint32 *) (p - 4) *(uint32 *) (p - 8) *(uint32 *) (p - 12) *(uint32 *) (p - 16) *(uint32 *) (p - 20) *(uint32 *) (p - 24) *(uint32 *) (p - 28) *(uint32 *) (p - 32) *(uint32 *) (p - 36) *(uint32 *) (p - 40) result += xi9 result += xi8 result += xi7
18
result += xi6 result += xi5 result += xi4 result += xi3 result += xi2 result += xi1 result += xi0 xi9 = *(uint32 *) (p - 44) xi8 = *(uint32 *) (p - 48) xi7 = *(uint32 *) (p - 52) xi6 = *(uint32 *) (p - 56) xi5 = *(uint32 *) (p - 60) xi4 = *(uint32 *) (p - 64) xi3 = *(uint32 *) (p - 68) xi2 = *(uint32 *) (p - 72) xi1 = xi0 = result result result result result result result result result result goto loop
17
*) (p - 4) *) (p - 8) *) (p - 12) *) (p - 16) *) (p - 20) *) (p - 24) *) (p - 28) *) (p - 32) *) (p - 36) *) (p - 40)
18
result += xi6 result += xi5 result += xi4 result += xi3 result += xi2 result += xi1 result += xi0 xi9 = *(uint32 *) (p - 44) xi8 = *(uint32 *) (p - 48) xi7 = *(uint32 *) (p - 52) xi6 = *(uint32 *) (p - 56) xi5 = *(uint32 *) (p - 60) xi4 = *(uint32 *) (p - 64) xi3 = *(uint32 *) (p - 68) xi2 = *(uint32 *) (p - 72) xi1 = *(uint32 xi0 = *(uint32 result += xi9 result += xi8 result += xi7 result += xi6 result += xi5 result += xi4 result += xi3 result += xi2 result += xi1 result += xi0 =? goto loop if !=
17
4) 8) 12) 16) 20) 24) 28) 32) 36) 40)
18
result += xi6 result += xi5 result += xi4 result += xi3 result += xi2 result += xi1 result += xi0 xi9 = *(uint32 *) (p - 44) xi8 = *(uint32 *) (p - 48) xi7 = *(uint32 *) (p - 52) xi6 = *(uint32 *) (p - 56) xi5 = *(uint32 *) (p - 60) xi4 = *(uint32 *) (p - 64) xi3 = *(uint32 *) (p - 68) xi2 = *(uint32 *) (p - 72) xi1 = *(uint32 *) (p - xi0 = *(uint32 *) (p - result += xi9 result += xi8 result += xi7 result += xi6 result += xi5 result += xi4 result += xi3 result += xi2 result += xi1 result += xi0 =? p - y goto loop if !=
18
result += xi6 result += xi5 result += xi4 result += xi3 result += xi2 result += xi1 result += xi0 xi9 = *(uint32 *) (p - 44) xi8 = *(uint32 *) (p - 48) xi7 = *(uint32 *) (p - 52) xi6 = *(uint32 *) (p - 56) xi5 = *(uint32 *) (p - 60) xi4 = *(uint32 *) (p - 64) xi3 = *(uint32 *) (p - 68) xi2 = *(uint32 *) (p - 72)
19
xi1 = *(uint32 *) (p - 76) xi0 = *(uint32 *) (p - 80) result += xi9 result += xi8 result += xi7 result += xi6 result += xi5 result += xi4 result += xi3 result += xi2 result += xi1 result += xi0 =? p - y goto loop if !=
18
result += xi6 result += xi5 result += xi4 result += xi3 result += xi2 result += xi1 result += xi0 *(uint32 *) (p - 44) *(uint32 *) (p - 48) *(uint32 *) (p - 52) *(uint32 *) (p - 56) *(uint32 *) (p - 60) *(uint32 *) (p - 64) *(uint32 *) (p - 68) *(uint32 *) (p - 72)
19
xi1 = *(uint32 *) (p - 76) xi0 = *(uint32 *) (p - 80) result += xi9 result += xi8 result += xi7 result += xi6 result += xi5 result += xi4 result += xi3 result += xi2 result += xi1 result += xi0 =? p - y goto loop if !=
Wikipedia: even perfo
performance
18
*) (p - 44) *) (p - 48) *) (p - 52) *) (p - 56) *) (p - 60) *) (p - 64) *) (p - 68) *) (p - 72)
19
xi1 = *(uint32 *) (p - 76) xi0 = *(uint32 *) (p - 80) result += xi9 result += xi8 result += xi7 result += xi6 result += xi5 result += xi4 result += xi3 result += xi2 result += xi1 result += xi0 =? p - y goto loop if !=
Wikipedia: “By the even performance
performance of human
18
44) 48) 52) 56) 60) 64) 68) 72)
19
xi1 = *(uint32 *) (p - 76) xi0 = *(uint32 *) (p - 80) result += xi9 result += xi8 result += xi7 result += xi6 result += xi5 result += xi4 result += xi3 result += xi2 result += xi1 result += xi0 =? p - y goto loop if !=
Wikipedia: “By the late 1990s even performance sensitive co
performance of human experts.
19
xi1 = *(uint32 *) (p - 76) xi0 = *(uint32 *) (p - 80) result += xi9 result += xi8 result += xi7 result += xi6 result += xi5 result += xi4 result += xi3 result += xi2 result += xi1 result += xi0 =? p - y goto loop if !=
20
Wikipedia: “By the late 1990s for even performance sensitive code,
performance of human experts.”
19
xi1 = *(uint32 *) (p - 76) xi0 = *(uint32 *) (p - 80) result += xi9 result += xi8 result += xi7 result += xi6 result += xi5 result += xi4 result += xi3 result += xi2 result += xi1 result += xi0 =? p - y goto loop if !=
20
Wikipedia: “By the late 1990s for even performance sensitive code,
performance of human experts.” Reality: The fastest software today relies on human experts understanding the CPU. Cannot trust compiler to
Cannot trust compiler to
Cannot trust compiler to
19
*(uint32 *) (p - 76) *(uint32 *) (p - 80) result += xi9 result += xi8 result += xi7 result += xi6 result += xi5 result += xi4 result += xi3 result += xi2 result += xi1 result += xi0 =? p - y loop if !=
20
Wikipedia: “By the late 1990s for even performance sensitive code,
performance of human experts.” Reality: The fastest software today relies on human experts understanding the CPU. Cannot trust compiler to
Cannot trust compiler to
Cannot trust compiler to
The big CPUs are farther and from naive
19
*) (p - 76) *) (p - 80) p - y
20
Wikipedia: “By the late 1990s for even performance sensitive code,
performance of human experts.” Reality: The fastest software today relies on human experts understanding the CPU. Cannot trust compiler to
Cannot trust compiler to
Cannot trust compiler to
The big picture CPUs are evolving farther and farther from naive models
19
76) 80)
20
Wikipedia: “By the late 1990s for even performance sensitive code,
performance of human experts.” Reality: The fastest software today relies on human experts understanding the CPU. Cannot trust compiler to
Cannot trust compiler to
Cannot trust compiler to
The big picture CPUs are evolving farther and farther away from naive models of CPUs.
20
Wikipedia: “By the late 1990s for even performance sensitive code,
performance of human experts.” Reality: The fastest software today relies on human experts understanding the CPU. Cannot trust compiler to
Cannot trust compiler to
Cannot trust compiler to
21
The big picture CPUs are evolving farther and farther away from naive models of CPUs.
20
Wikipedia: “By the late 1990s for even performance sensitive code,
performance of human experts.” Reality: The fastest software today relies on human experts understanding the CPU. Cannot trust compiler to
Cannot trust compiler to
Cannot trust compiler to
21
The big picture CPUs are evolving farther and farther away from naive models of CPUs. Minor optimization challenges:
Major optimization challenges:
the ring; the mesh.
20
edia: “By the late 1990s for erformance sensitive code,
rmance of human experts.” y: The fastest software relies on human experts understanding the CPU. Cannot trust compiler to
Cannot trust compiler to
Cannot trust compiler to
21
The big picture CPUs are evolving farther and farther away from naive models of CPUs. Minor optimization challenges:
Major optimization challenges:
the ring; the mesh.
CPU design f0
❇ ❇ ❇ g0 ⑤ ⑤ ⑤ ⑤
∧
h1 Gates ∧ : product
20
the late 1990s for rmance sensitive code, compilers exceeded the human experts.” test software human experts the CPU. compiler to instruction selection. compiler to instruction scheduling. compiler to allocation.
21
The big picture CPUs are evolving farther and farther away from naive models of CPUs. Minor optimization challenges:
Major optimization challenges:
the ring; the mesh.
CPU design in a nutshell f0
❇ ❇ ❇ g0 ⑤ ⑤ ⑤ ⑤ ◗ ◗ ◗ ◗ ◗ ◗ ◗ ◗ ♠♠♠♠♠♠♠♠♠
∧
❊ ❊ ❊ ❊ ② ② ② ②
∧
❊ ❊ ❊ ❊
∧
② ② ②
∧
② ② ② ② ❊ ❊ ❊ ❊
∧
h1 h3 Gates ∧ : a; b → 1 product h0 + 2h1 +
20
1990s for code, exceeded the erts.” are erts selection. scheduling. cation.
21
The big picture CPUs are evolving farther and farther away from naive models of CPUs. Minor optimization challenges:
Major optimization challenges:
the ring; the mesh.
CPU design in a nutshell f0
❇ ❇ ❇ g0 ⑤ ⑤ ⑤ ⑤
◗ ◗ ◗ ◗ ◗ ◗ ◗ ◗ g1 ♠♠♠♠♠♠♠♠♠
❆ ❆ ❆ f1 ⑥ ⑥ ⑥ ⑥
❊ ❊ ❊ ❊
∧
② ② ② ②
∧
❊ ❊ ❊ ❊
∧
② ② ② ② ②
∧
☞☞☞☞☞☞☞☞
∧
② ② ② ②
❊ ❊ ❊ ❊
∧
h1 h3 h2 Gates ∧ : a; b → 1 − ab computing product h0 + 2h1 + 4h2 + 8h
21
The big picture CPUs are evolving farther and farther away from naive models of CPUs. Minor optimization challenges:
Major optimization challenges:
the ring; the mesh.
22
CPU design in a nutshell f0
❇ ❇ ❇ g0 ⑤ ⑤ ⑤ ⑤
◗ ◗ ◗ ◗ ◗ ◗ ◗ ◗ g1 ♠♠♠♠♠♠♠♠♠
❆ ❆ ❆ f1 ⑥ ⑥ ⑥ ⑥
❊ ❊ ❊ ❊
∧
② ② ② ②
∧
❊ ❊ ❊ ❊
∧
② ② ② ② ②
∧
☞☞☞☞☞☞☞☞
∧
② ② ② ②
❊ ❊ ❊ ❊
∧
h1 h3 h2 Gates ∧ : a; b → 1 − ab computing product h0 + 2h1 + 4h2 + 8h3
21
big picture are evolving and farther away naive models of CPUs.
elining. erscalar processing.
ectorization. Many threads; many cores. memory hierarchy; ring; the mesh. rger-scale parallelism. rger-scale networking.
22
CPU design in a nutshell f0
❇ ❇ ❇ g0 ⑤ ⑤ ⑤ ⑤
◗ ◗ ◗ ◗ ◗ ◗ ◗ ◗ g1 ♠♠♠♠♠♠♠♠♠
❆ ❆ ❆ f1 ⑥ ⑥ ⑥ ⑥
❊ ❊ ❊ ❊
∧
② ② ② ②
∧
❊ ❊ ❊ ❊
∧
② ② ② ② ②
∧
☞☞☞☞☞☞☞☞
∧
② ② ② ②
❊ ❊ ❊ ❊
∧
h1 h3 h2 Gates ∧ : a; b → 1 − ab computing product h0 + 2h1 + 4h2 + 8h3
Electricit percolate If f0; f1; g then h0; a few moments
21
evolving rther away dels of CPUs. ion challenges: rocessing. tion challenges: many cores. hierarchy; mesh. parallelism. networking.
22
CPU design in a nutshell f0
❇ ❇ ❇ g0 ⑤ ⑤ ⑤ ⑤
◗ ◗ ◗ ◗ ◗ ◗ ◗ ◗ g1 ♠♠♠♠♠♠♠♠♠
❆ ❆ ❆ f1 ⑥ ⑥ ⑥ ⑥
❊ ❊ ❊ ❊
∧
② ② ② ②
∧
❊ ❊ ❊ ❊
∧
② ② ② ② ②
∧
☞☞☞☞☞☞☞☞
∧
② ② ② ②
❊ ❊ ❊ ❊
∧
h1 h3 h2 Gates ∧ : a; b → 1 − ab computing product h0 + 2h1 + 4h2 + 8h3
Electricity takes time percolate through If f0; f1; g0; g1 are stab then h0; h1; h2; h3 a few moments later.
21
CPUs. challenges: challenges: res.
22
CPU design in a nutshell f0
❇ ❇ ❇ g0 ⑤ ⑤ ⑤ ⑤
◗ ◗ ◗ ◗ ◗ ◗ ◗ ◗ g1 ♠♠♠♠♠♠♠♠♠
❆ ❆ ❆ f1 ⑥ ⑥ ⑥ ⑥
❊ ❊ ❊ ❊
∧
② ② ② ②
∧
❊ ❊ ❊ ❊
∧
② ② ② ② ②
∧
☞☞☞☞☞☞☞☞
∧
② ② ② ②
❊ ❊ ❊ ❊
∧
h1 h3 h2 Gates ∧ : a; b → 1 − ab computing product h0 + 2h1 + 4h2 + 8h3
Electricity takes time to percolate through wires and If f0; f1; g0; g1 are stable then h0; h1; h2; h3 are stable a few moments later.
22
CPU design in a nutshell f0
❇ ❇ ❇ g0 ⑤ ⑤ ⑤ ⑤
◗ ◗ ◗ ◗ ◗ ◗ ◗ ◗ g1 ♠♠♠♠♠♠♠♠♠
❆ ❆ ❆ f1 ⑥ ⑥ ⑥ ⑥
❊ ❊ ❊ ❊
∧
② ② ② ②
∧
❊ ❊ ❊ ❊
∧
② ② ② ② ②
∧
☞☞☞☞☞☞☞☞
∧
② ② ② ②
❊ ❊ ❊ ❊
∧
h1 h3 h2 Gates ∧ : a; b → 1 − ab computing product h0 + 2h1 + 4h2 + 8h3
23
Electricity takes time to percolate through wires and gates. If f0; f1; g0; g1 are stable then h0; h1; h2; h3 are stable a few moments later.
22
CPU design in a nutshell f0
❇ ❇ ❇ g0 ⑤ ⑤ ⑤ ⑤
◗ ◗ ◗ ◗ ◗ ◗ ◗ ◗ g1 ♠♠♠♠♠♠♠♠♠
❆ ❆ ❆ f1 ⑥ ⑥ ⑥ ⑥
❊ ❊ ❊ ❊
∧
② ② ② ②
∧
❊ ❊ ❊ ❊
∧
② ② ② ② ②
∧
☞☞☞☞☞☞☞☞
∧
② ② ② ②
❊ ❊ ❊ ❊
∧
h1 h3 h2 Gates ∧ : a; b → 1 − ab computing product h0 + 2h1 + 4h2 + 8h3
23
Electricity takes time to percolate through wires and gates. If f0; f1; g0; g1 are stable then h0; h1; h2; h3 are stable a few moments later. Build circuit with more gates to multiply (e.g.) 32-bit integers: ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ❄ ❄ ❄ ❄ ❄ ❄ ❄ ❄ ❄ ❄ ❄ ❄ ❄ ❄ ❄ ❄ ❄ ❄ ❄ (Details omitted.)
22
design in a nutshell
◗ ◗ ◗ ◗ ◗ ◗ ◗ ◗ g1 ♠♠♠♠♠♠♠♠♠
❆ ❆ ❆ f1 ⑥ ⑥ ⑥ ⑥
❊ ❊ ❊ ❊
∧
② ② ② ②
∧
❊ ❊ ❊ ❊
∧
② ② ② ② ②
∧
☞☞☞☞☞☞☞☞
∧
② ② ② ②
❊ ❊ ❊ ❊
∧
h3 h2
∧ : a; b → 1 − ab computing
duct h0 + 2h1 + 4h2 + 8h3 integers f0 + 2f1; g0 + 2g1.
23
Electricity takes time to percolate through wires and gates. If f0; f1; g0; g1 are stable then h0; h1; h2; h3 are stable a few moments later. Build circuit with more gates to multiply (e.g.) 32-bit integers: ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ❄ ❄ ❄ ❄ ❄ ❄ ❄ ❄ ❄ ❄ ❄ ❄ ❄ ❄ ❄ ❄ ❄ ❄ ❄ (Details omitted.) Build circuit 32-bit integer given 4-bit and 32-bit
22
nutshell
◗ g1 ♠♠
❆ ❆ ❆ f1 ⑥ ⑥ ⑥ ⑥
② ②
∧
② ② ②
∧
☞☞☞☞☞☞☞☞
❊ ❊
∧
1 − ab computing + 4h2 + 8h3 2f1; g0 + 2g1.
23
Electricity takes time to percolate through wires and gates. If f0; f1; g0; g1 are stable then h0; h1; h2; h3 are stable a few moments later. Build circuit with more gates to multiply (e.g.) 32-bit integers: ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ❄ ❄ ❄ ❄ ❄ ❄ ❄ ❄ ❄ ❄ ❄ ❄ ❄ ❄ ❄ ❄ ❄ ❄ ❄ (Details omitted.) Build circuit to compute 32-bit integer ri given 4-bit integer and 32-bit integers
22
f1
computing 8h3 g1.
23
Electricity takes time to percolate through wires and gates. If f0; f1; g0; g1 are stable then h0; h1; h2; h3 are stable a few moments later. Build circuit with more gates to multiply (e.g.) 32-bit integers: ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ❄ ❄ ❄ ❄ ❄ ❄ ❄ ❄ ❄ ❄ ❄ ❄ ❄ ❄ ❄ ❄ ❄ ❄ ❄ (Details omitted.) Build circuit to compute 32-bit integer ri given 4-bit integer i and 32-bit integers r0; r1; : : :
23
Electricity takes time to percolate through wires and gates. If f0; f1; g0; g1 are stable then h0; h1; h2; h3 are stable a few moments later. Build circuit with more gates to multiply (e.g.) 32-bit integers: ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ❄ ❄ ❄ ❄ ❄ ❄ ❄ ❄ ❄ ❄ ❄ ❄ ❄ ❄ ❄ ❄ ❄ ❄ ❄ (Details omitted.)
24
Build circuit to compute 32-bit integer ri given 4-bit integer i and 32-bit integers r0; r1; : : : ; r15:
23
Electricity takes time to percolate through wires and gates. If f0; f1; g0; g1 are stable then h0; h1; h2; h3 are stable a few moments later. Build circuit with more gates to multiply (e.g.) 32-bit integers: ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ❄ ❄ ❄ ❄ ❄ ❄ ❄ ❄ ❄ ❄ ❄ ❄ ❄ ❄ ❄ ❄ ❄ ❄ ❄ (Details omitted.)
24
Build circuit to compute 32-bit integer ri given 4-bit integer i and 32-bit integers r0; r1; : : : ; r15:
Build circuit for “register write”: r0; : : : ; r15; s; i → r′
0; : : : ; r′ 15
where r′
j = rj except r′ i = s.
23
Electricity takes time to percolate through wires and gates. If f0; f1; g0; g1 are stable then h0; h1; h2; h3 are stable a few moments later. Build circuit with more gates to multiply (e.g.) 32-bit integers: ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ❄ ❄ ❄ ❄ ❄ ❄ ❄ ❄ ❄ ❄ ❄ ❄ ❄ ❄ ❄ ❄ ❄ ❄ ❄ (Details omitted.)
24
Build circuit to compute 32-bit integer ri given 4-bit integer i and 32-bit integers r0; r1; : : : ; r15:
Build circuit for “register write”: r0; : : : ; r15; s; i → r′
0; : : : ; r′ 15
where r′
j = rj except r′ i = s.
Build circuit for addition. Etc.
23
Electricity takes time to ercolate through wires and gates. ; g0; g1 are stable
0; h1; h2; h3 are stable
moments later. circuit with more gates multiply (e.g.) 32-bit integers: ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ❄ ❄ ❄ ❄ ❄ ❄ ❄ ❄ ❄ ❄ ❄ ❄ ❄ (Details omitted.)
24
Build circuit to compute 32-bit integer ri given 4-bit integer i and 32-bit integers r0; r1; : : : ; r15:
Build circuit for “register write”: r0; : : : ; r15; s; i → r′
0; : : : ; r′ 15
where r′
j = rj except r′ i = s.
Build circuit for addition. Etc. r0; : : : ; r15 where r′
‘
23
time to through wires and gates. re stable
3 are stable
later. with more gates (e.g.) 32-bit integers: ⑧ ❄ .)
24
Build circuit to compute 32-bit integer ri given 4-bit integer i and 32-bit integers r0; r1; : : : ; r15:
Build circuit for “register write”: r0; : : : ; r15; s; i → r′
0; : : : ; r′ 15
where r′
j = rj except r′ i = s.
Build circuit for addition. Etc. r0; : : : ; r15; i; j; k → where r′
‘ = r‘ except
⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ❄ ❄ ❄ ❄ ❄ ❄ ❄ ❄ ❄ ❄ ❄ ❄ ❄
23
and gates. stable gates integers:
24
Build circuit to compute 32-bit integer ri given 4-bit integer i and 32-bit integers r0; r1; : : : ; r15:
Build circuit for “register write”: r0; : : : ; r15; s; i → r′
0; : : : ; r′ 15
where r′
j = rj except r′ i = s.
Build circuit for addition. Etc. r0; : : : ; r15; i; j; k → r′
0; : : : ; r15
where r′
‘ = r‘ except r′ i = rjr
⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ❄ ❄ ❄ ❄ ❄ ❄ ❄ ❄ ❄ ❄ ❄ ❄ ❄
24
Build circuit to compute 32-bit integer ri given 4-bit integer i and 32-bit integers r0; r1; : : : ; r15:
Build circuit for “register write”: r0; : : : ; r15; s; i → r′
0; : : : ; r′ 15
where r′
j = rj except r′ i = s.
Build circuit for addition. Etc.
25
r0; : : : ; r15; i; j; k → r′
0; : : : ; r′ 15
where r′
‘ = r‘ except r′ i = rjrk:
⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ❄ ❄ ❄ ❄ ❄ ❄ ❄ ❄ ❄ ❄ ❄ ❄ ❄
24
circuit to compute integer ri 4-bit integer i 32-bit integers r0; r1; : : : ; r15:
circuit for “register write”: ; r15; s; i → r′
0; : : : ; r′ 15
r′
j = rj except r′ i = s.
circuit for addition. Etc.
25
r0; : : : ; r15; i; j; k → r′
0; : : : ; r′ 15
where r′
‘ = r‘ except r′ i = rjrk:
⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ❄ ❄ ❄ ❄ ❄ ❄ ❄ ❄ ❄ ❄ ❄ ❄ ❄
Add mor More arithmetic: replace ( (“×”; i; j (“+”; i; j
24
compute integer i integers r0; r1; : : : ; r15:
“register write”: r′
0; : : : ; r′ 15
except r′
i = s.
25
r0; : : : ; r15; i; j; k → r′
0; : : : ; r′ 15
where r′
‘ = r‘ except r′ i = rjrk:
⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ❄ ❄ ❄ ❄ ❄ ❄ ❄ ❄ ❄ ❄ ❄ ❄ ❄
Add more flexibilit More arithmetic: replace (i; j; k) with (“×”; i; j; k) and (“+”; i; j; k) and m
24
: : ; r15: write”:
′ 15
s. Etc.
25
r0; : : : ; r15; i; j; k → r′
0; : : : ; r′ 15
where r′
‘ = r‘ except r′ i = rjrk:
⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ❄ ❄ ❄ ❄ ❄ ❄ ❄ ❄ ❄ ❄ ❄ ❄ ❄
Add more flexibility. More arithmetic: replace (i; j; k) with (“×”; i; j; k) and (“+”; i; j; k) and more options.
25
r0; : : : ; r15; i; j; k → r′
0; : : : ; r′ 15
where r′
‘ = r‘ except r′ i = rjrk:
⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ❄ ❄ ❄ ❄ ❄ ❄ ❄ ❄ ❄ ❄ ❄ ❄ ❄
26
Add more flexibility. More arithmetic: replace (i; j; k) with (“×”; i; j; k) and (“+”; i; j; k) and more options.
25
r0; : : : ; r15; i; j; k → r′
0; : : : ; r′ 15
where r′
‘ = r‘ except r′ i = rjrk:
⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ❄ ❄ ❄ ❄ ❄ ❄ ❄ ❄ ❄ ❄ ❄ ❄ ❄
26
Add more flexibility. More arithmetic: replace (i; j; k) with (“×”; i; j; k) and (“+”; i; j; k) and more options. More (but slower) storage: “load” from and “store” to larger “RAM” arrays.
25
r0; : : : ; r15; i; j; k → r′
0; : : : ; r′ 15
where r′
‘ = r‘ except r′ i = rjrk:
⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ❄ ❄ ❄ ❄ ❄ ❄ ❄ ❄ ❄ ❄ ❄ ❄ ❄
26
Add more flexibility. More arithmetic: replace (i; j; k) with (“×”; i; j; k) and (“+”; i; j; k) and more options. More (but slower) storage: “load” from and “store” to larger “RAM” arrays. “Instruction fetch”: p → op; ip; jp; kp; p′.
25
r0; : : : ; r15; i; j; k → r′
0; : : : ; r′ 15
where r′
‘ = r‘ except r′ i = rjrk:
⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ❄ ❄ ❄ ❄ ❄ ❄ ❄ ❄ ❄ ❄ ❄ ❄ ❄
26
Add more flexibility. More arithmetic: replace (i; j; k) with (“×”; i; j; k) and (“+”; i; j; k) and more options. More (but slower) storage: “load” from and “store” to larger “RAM” arrays. “Instruction fetch”: p → op; ip; jp; kp; p′. “Instruction decode”: decompression of compressed format for op; ip; jp; kp; p′.
25
; r15; i; j; k → r′
0; : : : ; r′ 15
r′
‘ = r‘ except r′ i = rjrk:
⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ❄ ❄ ❄ ❄ ❄ ❄ ❄ ❄ ❄ ❄ ❄ ❄ ❄
26
Add more flexibility. More arithmetic: replace (i; j; k) with (“×”; i; j; k) and (“+”; i; j; k) and more options. More (but slower) storage: “load” from and “store” to larger “RAM” arrays. “Instruction fetch”: p → op; ip; jp; kp; p′. “Instruction decode”: decompression of compressed format for op; ip; jp; kp; p′. Build “flip-flops” storing ( Hook (p; flip-flops Hook outputs into the At each flip-flops with the Clock needs for electricit all the w from flip-flops
25
→ r′
0; : : : ; r′ 15
except r′
i = rjrk:
⑧ ⑧ ❄ ❄
26
Add more flexibility. More arithmetic: replace (i; j; k) with (“×”; i; j; k) and (“+”; i; j; k) and more options. More (but slower) storage: “load” from and “store” to larger “RAM” arrays. “Instruction fetch”: p → op; ip; jp; kp; p′. “Instruction decode”: decompression of compressed format for op; ip; jp; kp; p′. Build “flip-flops” storing (p; r0; : : : ; r Hook (p; r0; : : : ; r15 flip-flops into circuit Hook outputs (p′; into the same flip-flops. At each “clock tick”, flip-flops are overwritten with the outputs. Clock needs to be for electricity to percolate all the way through from flip-flops to flip-flops.
25
; r′
15
rjrk:
26
Add more flexibility. More arithmetic: replace (i; j; k) with (“×”; i; j; k) and (“+”; i; j; k) and more options. More (but slower) storage: “load” from and “store” to larger “RAM” arrays. “Instruction fetch”: p → op; ip; jp; kp; p′. “Instruction decode”: decompression of compressed format for op; ip; jp; kp; p′. Build “flip-flops” storing (p; r0; : : : ; r15). Hook (p; r0; : : : ; r15) flip-flops into circuit inputs. Hook outputs (p′; r′
0; : : : ; r′ 15
into the same flip-flops. At each “clock tick”, flip-flops are overwritten with the outputs. Clock needs to be slow enou for electricity to percolate all the way through the circuit, from flip-flops to flip-flops.
26
Add more flexibility. More arithmetic: replace (i; j; k) with (“×”; i; j; k) and (“+”; i; j; k) and more options. More (but slower) storage: “load” from and “store” to larger “RAM” arrays. “Instruction fetch”: p → op; ip; jp; kp; p′. “Instruction decode”: decompression of compressed format for op; ip; jp; kp; p′.
27
Build “flip-flops” storing (p; r0; : : : ; r15). Hook (p; r0; : : : ; r15) flip-flops into circuit inputs. Hook outputs (p′; r′
0; : : : ; r′ 15)
into the same flip-flops. At each “clock tick”, flip-flops are overwritten with the outputs. Clock needs to be slow enough for electricity to percolate all the way through the circuit, from flip-flops to flip-flops.
26
more flexibility. arithmetic: replace (i; j; k) with i; j; k) and i; j; k) and more options. (but slower) storage: from and “store” to “RAM” arrays. “Instruction fetch”: ; ip; jp; kp; p′. “Instruction decode”: decompression of compressed for op; ip; jp; kp; p′.
27
Build “flip-flops” storing (p; r0; : : : ; r15). Hook (p; r0; : : : ; r15) flip-flops into circuit inputs. Hook outputs (p′; r′
0; : : : ; r′ 15)
into the same flip-flops. At each “clock tick”, flip-flops are overwritten with the outputs. Clock needs to be slow enough for electricity to percolate all the way through the circuit, from flip-flops to flip-flops. Now have
flip-flops fetch deco register read
⑧ ❄
register write
Further flexibilit e.g., logic
26
flexibility. rithmetic: with more options. er) storage: “store” to rrays. fetch”: ; p′. decode”:
; jp; kp; p′.
27
Build “flip-flops” storing (p; r0; : : : ; r15). Hook (p; r0; : : : ; r15) flip-flops into circuit inputs. Hook outputs (p′; r′
0; : : : ; r′ 15)
into the same flip-flops. At each “clock tick”, flip-flops are overwritten with the outputs. Clock needs to be slow enough for electricity to percolate all the way through the circuit, from flip-flops to flip-flops. Now have semi-flexible
flip-flops insn fetch insn decode register read register read
⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ❄ ❄ ❄ ❄ ❄ ❄ ❄
register write
Further flexibility is e.g., logic instructions.
26
rage: to ressed
27
Build “flip-flops” storing (p; r0; : : : ; r15). Hook (p; r0; : : : ; r15) flip-flops into circuit inputs. Hook outputs (p′; r′
0; : : : ; r′ 15)
into the same flip-flops. At each “clock tick”, flip-flops are overwritten with the outputs. Clock needs to be slow enough for electricity to percolate all the way through the circuit, from flip-flops to flip-flops. Now have semi-flexible CPU:
flip-flops insn fetch insn decode register read register read
⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ❄ ❄ ❄ ❄ ❄ ❄ ❄
register write
Further flexibility is useful: e.g., logic instructions.
27
Build “flip-flops” storing (p; r0; : : : ; r15). Hook (p; r0; : : : ; r15) flip-flops into circuit inputs. Hook outputs (p′; r′
0; : : : ; r′ 15)
into the same flip-flops. At each “clock tick”, flip-flops are overwritten with the outputs. Clock needs to be slow enough for electricity to percolate all the way through the circuit, from flip-flops to flip-flops.
28
Now have semi-flexible CPU:
flip-flops insn fetch insn decode register read register read
⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ❄ ❄ ❄ ❄ ❄ ❄ ❄
register write
Further flexibility is useful: e.g., logic instructions.
27
“flip-flops” (p; r0; : : : ; r15). (p; r0; : : : ; r15) flip-flops into circuit inputs.
0; : : : ; r′ 15)
the same flip-flops. each “clock tick”, flip-flops are overwritten the outputs. needs to be slow enough lectricity to percolate way through the circuit, flip-flops to flip-flops.
28
Now have semi-flexible CPU:
flip-flops insn fetch insn decode register read register read
⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ❄ ❄ ❄ ❄ ❄ ❄ ❄
register write
Further flexibility is useful: e.g., logic instructions. “Pipelining”
flip-flops fetch flip-flops deco flip-flops register read flip-flops
⑧ ❄
flip-flops register write
27
: ; r15). r15) circuit inputs.
′; r′ 0; : : : ; r′ 15)
flip-flops. tick”,
e slow enough percolate through the circuit, flip-flops.
28
Now have semi-flexible CPU:
flip-flops insn fetch insn decode register read register read
⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ❄ ❄ ❄ ❄ ❄ ❄ ❄
register write
Further flexibility is useful: e.g., logic instructions. “Pipelining” allows
flip-flops insn fetch flip-flops insn decode flip-flops register read register read flip-flops
⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ❄ ❄ ❄ ❄ ❄ ❄ ❄
flip-flops register write
27
inputs.
′ 15)
circuit, flip-flops.
28
Now have semi-flexible CPU:
flip-flops insn fetch insn decode register read register read
⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ❄ ❄ ❄ ❄ ❄ ❄ ❄
register write
Further flexibility is useful: e.g., logic instructions. “Pipelining” allows faster clo
flip-flops insn fetch stage flip-flops insn decode stage flip-flops register read register read stage flip-flops
⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ❄ ❄ ❄ ❄ ❄ ❄ ❄
stage flip-flops register write stage
28
Now have semi-flexible CPU:
flip-flops insn fetch insn decode register read register read
⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ❄ ❄ ❄ ❄ ❄ ❄ ❄
register write
Further flexibility is useful: e.g., logic instructions.
29
“Pipelining” allows faster clock:
flip-flops insn fetch stage 1 flip-flops insn decode stage 2 flip-flops register read register read stage 3 flip-flops
⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ❄ ❄ ❄ ❄ ❄ ❄ ❄
stage 4 flip-flops register write stage 5
28
have semi-flexible CPU:
flip-flops insn fetch insn decode register read register read
⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ❄ ❄ ❄ ❄ ❄ ❄ ❄
register write
urther flexibility is useful: logic instructions.
29
“Pipelining” allows faster clock:
flip-flops insn fetch stage 1 flip-flops insn decode stage 2 flip-flops register read register read stage 3 flip-flops
⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ❄ ❄ ❄ ❄ ❄ ❄ ❄
stage 4 flip-flops register write stage 5
Goal: Stage
Instruction reads next feeds p′ After next instruction uncompresses while instruction reads another Some extra Also extra preserve e.g., stall
28
semi-flexible CPU:
register
y is useful: instructions.
29
“Pipelining” allows faster clock:
flip-flops insn fetch stage 1 flip-flops insn decode stage 2 flip-flops register read register read stage 3 flip-flops
⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ❄ ❄ ❄ ❄ ❄ ❄ ❄
stage 4 flip-flops register write stage 5
Goal: Stage n handles
Instruction fetch reads next instruction, feeds p′ back, sends After next clock tick, instruction decode uncompresses this while instruction fetch reads another instru Some extra flip-flop Also extra area to preserve instruction e.g., stall on read-after-write.
28
CPU: useful:
29
“Pipelining” allows faster clock:
flip-flops insn fetch stage 1 flip-flops insn decode stage 2 flip-flops register read register read stage 3 flip-flops
⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ❄ ❄ ❄ ❄ ❄ ❄ ❄
stage 4 flip-flops register write stage 5
Goal: Stage n handles instruction
Instruction fetch reads next instruction, feeds p′ back, sends instruction. After next clock tick, instruction decode uncompresses this instruction, while instruction fetch reads another instruction. Some extra flip-flop area. Also extra area to preserve instruction semantics: e.g., stall on read-after-write.
29
“Pipelining” allows faster clock:
flip-flops insn fetch stage 1 flip-flops insn decode stage 2 flip-flops register read register read stage 3 flip-flops
⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ❄ ❄ ❄ ❄ ❄ ❄ ❄
stage 4 flip-flops register write stage 5
30
Goal: Stage n handles instruction
Instruction fetch reads next instruction, feeds p′ back, sends instruction. After next clock tick, instruction decode uncompresses this instruction, while instruction fetch reads another instruction. Some extra flip-flop area. Also extra area to preserve instruction semantics: e.g., stall on read-after-write.
29
elining” allows faster clock:
flip-flops insn fetch stage 1 flip-flops insn decode stage 2 flip-flops register read register read stage 3 flip-flops
⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ❄ ❄ ❄ ❄ ❄ ❄ ❄
stage 4 flip-flops register write stage 5
30
Goal: Stage n handles instruction
Instruction fetch reads next instruction, feeds p′ back, sends instruction. After next clock tick, instruction decode uncompresses this instruction, while instruction fetch reads another instruction. Some extra flip-flop area. Also extra area to preserve instruction semantics: e.g., stall on read-after-write. “Superscala
fetch deco register read register read register write
29
ws faster clock:
stage 1 stage 2 register stage 3 stage 4 stage 5
30
Goal: Stage n handles instruction
Instruction fetch reads next instruction, feeds p′ back, sends instruction. After next clock tick, instruction decode uncompresses this instruction, while instruction fetch reads another instruction. Some extra flip-flop area. Also extra area to preserve instruction semantics: e.g., stall on read-after-write. “Superscalar” processing:
flip-flops insn fetch insn fetch flip-flops insn decode insn decode flip-flops register read register read register read flip-flops
⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ❄ ❄ ❄ ❄ ❄ ❄ ❄
flip-flops register write register write
29
clock:
stage 1 stage 2 stage 3 stage 4 stage 5
30
Goal: Stage n handles instruction
Instruction fetch reads next instruction, feeds p′ back, sends instruction. After next clock tick, instruction decode uncompresses this instruction, while instruction fetch reads another instruction. Some extra flip-flop area. Also extra area to preserve instruction semantics: e.g., stall on read-after-write. “Superscalar” processing:
flip-flops insn fetch insn fetch flip-flops insn decode insn decode flip-flops register read register read register read register read flip-flops
⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ❄ ❄ ❄ ❄ ❄ ❄ ❄
flip-flops register write register write
30
Goal: Stage n handles instruction
Instruction fetch reads next instruction, feeds p′ back, sends instruction. After next clock tick, instruction decode uncompresses this instruction, while instruction fetch reads another instruction. Some extra flip-flop area. Also extra area to preserve instruction semantics: e.g., stall on read-after-write.
31
“Superscalar” processing:
flip-flops insn fetch insn fetch flip-flops insn decode insn decode flip-flops register read register read register read register read flip-flops
⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ❄ ❄ ❄ ❄ ❄ ❄ ❄
flip-flops register write register write
30
Stage n handles instruction tick after stage n − 1. Instruction fetch next instruction,
′ back, sends instruction.
next clock tick, instruction decode uncompresses this instruction, instruction fetch another instruction. extra flip-flop area. extra area to reserve instruction semantics: stall on read-after-write.
31
“Superscalar” processing:
flip-flops insn fetch insn fetch flip-flops insn decode insn decode flip-flops register read register read register read register read flip-flops
⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ❄ ❄ ❄ ❄ ❄ ❄ ❄
flip-flops register write register write
“Vector” Expand each into n-vecto ARM “NEON” Intel “AVX2” Intel “AVX-512” GPUs have
30
handles instruction stage n − 1. instruction, sends instruction. tick, de this instruction, fetch instruction. flip-flop area. to instruction semantics: read-after-write.
31
“Superscalar” processing:
flip-flops insn fetch insn fetch flip-flops insn decode insn decode flip-flops register read register read register read register read flip-flops
⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ❄ ❄ ❄ ❄ ❄ ❄ ❄
flip-flops register write register write
“Vector” processing: Expand each 32-bit into n-vector of 32-bit ARM “NEON” has Intel “AVX2” has n Intel “AVX-512” has GPUs have larger n
30
instruction instruction. instruction, semantics: read-after-write.
31
“Superscalar” processing:
flip-flops insn fetch insn fetch flip-flops insn decode insn decode flip-flops register read register read register read register read flip-flops
⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ❄ ❄ ❄ ❄ ❄ ❄ ❄
flip-flops register write register write
“Vector” processing: Expand each 32-bit integer into n-vector of 32-bit integers. ARM “NEON” has n = 4; Intel “AVX2” has n = 8; Intel “AVX-512” has n = 16; GPUs have larger n.
31
“Superscalar” processing:
flip-flops insn fetch insn fetch flip-flops insn decode insn decode flip-flops register read register read register read register read flip-flops
⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ❄ ❄ ❄ ❄ ❄ ❄ ❄
flip-flops register write register write
32
“Vector” processing: Expand each 32-bit integer into n-vector of 32-bit integers. ARM “NEON” has n = 4; Intel “AVX2” has n = 8; Intel “AVX-512” has n = 16; GPUs have larger n.
31
“Superscalar” processing:
flip-flops insn fetch insn fetch flip-flops insn decode insn decode flip-flops register read register read register read register read flip-flops
⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ❄ ❄ ❄ ❄ ❄ ❄ ❄
flip-flops register write register write
32
“Vector” processing: Expand each 32-bit integer into n-vector of 32-bit integers. ARM “NEON” has n = 4; Intel “AVX2” has n = 8; Intel “AVX-512” has n = 16; GPUs have larger n. n× speedup if n× arithmetic circuits, n× read/write circuits. Benefit: Amortizes insn circuits.
31
“Superscalar” processing:
flip-flops insn fetch insn fetch flip-flops insn decode insn decode flip-flops register read register read register read register read flip-flops
⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ❄ ❄ ❄ ❄ ❄ ❄ ❄
flip-flops register write register write
32
“Vector” processing: Expand each 32-bit integer into n-vector of 32-bit integers. ARM “NEON” has n = 4; Intel “AVX2” has n = 8; Intel “AVX-512” has n = 16; GPUs have larger n. n× speedup if n× arithmetic circuits, n× read/write circuits. Benefit: Amortizes insn circuits. Huge effect on higher-level algorithms and data structures.
31
erscalar” processing:
flip-flops insn fetch insn fetch flip-flops insn decode insn decode flip-flops register read register read register read flip-flops
⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ⑧ ❄ ❄ ❄ ❄ ❄ ❄ ❄
flip-flops register write register write
32
“Vector” processing: Expand each 32-bit integer into n-vector of 32-bit integers. ARM “NEON” has n = 4; Intel “AVX2” has n = 8; Intel “AVX-512” has n = 16; GPUs have larger n. n× speedup if n× arithmetic circuits, n× read/write circuits. Benefit: Amortizes insn circuits. Huge effect on higher-level algorithms and data structures. Network How exp Input: arra Each numb represented Output: in increasing represented same multise
31
rocessing:
flip-flops insn fetch flip-flops insn decode flip-flops register read register read flip-flops flip-flops register write
32
“Vector” processing: Expand each 32-bit integer into n-vector of 32-bit integers. ARM “NEON” has n = 4; Intel “AVX2” has n = 8; Intel “AVX-512” has n = 16; GPUs have larger n. n× speedup if n× arithmetic circuits, n× read/write circuits. Benefit: Amortizes insn circuits. Huge effect on higher-level algorithms and data structures. Network on chip: the How expensive is so Input: array of n numb Each number in ˘ 1 represented in bina Output: array of n in increasing order, represented in bina same multiset as input.
31
register
32
“Vector” processing: Expand each 32-bit integer into n-vector of 32-bit integers. ARM “NEON” has n = 4; Intel “AVX2” has n = 8; Intel “AVX-512” has n = 16; GPUs have larger n. n× speedup if n× arithmetic circuits, n× read/write circuits. Benefit: Amortizes insn circuits. Huge effect on higher-level algorithms and data structures. Network on chip: the mesh How expensive is sorting? Input: array of n numbers. Each number in ˘ 1; 2; : : : ; n2 represented in binary. Output: array of n numbers, in increasing order, represented in binary; same multiset as input.
32
“Vector” processing: Expand each 32-bit integer into n-vector of 32-bit integers. ARM “NEON” has n = 4; Intel “AVX2” has n = 8; Intel “AVX-512” has n = 16; GPUs have larger n. n× speedup if n× arithmetic circuits, n× read/write circuits. Benefit: Amortizes insn circuits. Huge effect on higher-level algorithms and data structures.
33
Network on chip: the mesh How expensive is sorting? Input: array of n numbers. Each number in ˘ 1; 2; : : : ; n2¯ , represented in binary. Output: array of n numbers, in increasing order, represented in binary; same multiset as input.
32
“Vector” processing: Expand each 32-bit integer into n-vector of 32-bit integers. ARM “NEON” has n = 4; Intel “AVX2” has n = 8; Intel “AVX-512” has n = 16; GPUs have larger n. n× speedup if n× arithmetic circuits, n× read/write circuits. Benefit: Amortizes insn circuits. Huge effect on higher-level algorithms and data structures.
33
Network on chip: the mesh How expensive is sorting? Input: array of n numbers. Each number in ˘ 1; 2; : : : ; n2¯ , represented in binary. Output: array of n numbers, in increasing order, represented in binary; same multiset as input. Metric: seconds used by circuit of area n1+o(1). For simplicity assume n = 4k.
32
r” processing: Expand each 32-bit integer
“NEON” has n = 4; “AVX2” has n = 8; “AVX-512” has n = 16; have larger n. eedup if rithmetic circuits, read/write circuits. Benefit: Amortizes insn circuits. effect on higher-level rithms and data structures.
33
Network on chip: the mesh How expensive is sorting? Input: array of n numbers. Each number in ˘ 1; 2; : : : ; n2¯ , represented in binary. Output: array of n numbers, in increasing order, represented in binary; same multiset as input. Metric: seconds used by circuit of area n1+o(1). For simplicity assume n = 4k. Spread a square mesh each of a with nea × × × × × × × × × × × × × × × × × × × × × × × × × × × × × ×
32
cessing: 32-bit integer 32-bit integers. has n = 4; has n = 8; has n = 16; rger n. circuits, circuits. rtizes insn circuits. higher-level data structures.
33
Network on chip: the mesh How expensive is sorting? Input: array of n numbers. Each number in ˘ 1; 2; : : : ; n2¯ , represented in binary. Output: array of n numbers, in increasing order, represented in binary; same multiset as input. Metric: seconds used by circuit of area n1+o(1). For simplicity assume n = 4k. Spread array across square mesh of n small each of area no(1), with near-neighbor × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × ×
32
integer integers. 16; circuits. higher-level structures.
33
Network on chip: the mesh How expensive is sorting? Input: array of n numbers. Each number in ˘ 1; 2; : : : ; n2¯ , represented in binary. Output: array of n numbers, in increasing order, represented in binary; same multiset as input. Metric: seconds used by circuit of area n1+o(1). For simplicity assume n = 4k. Spread array across square mesh of n small cells, each of area no(1), with near-neighbor wiring: × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × ×
33
Network on chip: the mesh How expensive is sorting? Input: array of n numbers. Each number in ˘ 1; 2; : : : ; n2¯ , represented in binary. Output: array of n numbers, in increasing order, represented in binary; same multiset as input. Metric: seconds used by circuit of area n1+o(1). For simplicity assume n = 4k.
34
Spread array across square mesh of n small cells, each of area no(1), with near-neighbor wiring: × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × ×
33
rk on chip: the mesh expensive is sorting? array of n numbers. number in ˘ 1; 2; : : : ; n2¯ , resented in binary. Output: array of n numbers, increasing order, resented in binary; multiset as input. Metric: seconds used by
simplicity assume n = 4k.
34
Spread array across square mesh of n small cells, each of area no(1), with near-neighbor wiring: × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × Sort row in n0:5+o
3 1 4 1 1 3 1 4
1 3 1 4 1 1 3 4
equals
33
chip: the mesh is sorting? numbers. ˘ 1; 2; : : : ; n2¯ , binary.
rder, binary; as input. used by
1+o(1).
assume n = 4k.
34
Spread array across square mesh of n small cells, each of area no(1), with near-neighbor wiring: × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × Sort row of n0:5 cells in n0:5+o(1) seconds:
3 1 4 1 5 9 2 6 → 1 3 1 4 5 9 2 6
1 3 1 4 5 9 2 6 → 1 1 3 4 5 2 9 6
equals row length.
33
mesh ers. ; n2¯ , ers, 4k.
34
Spread array across square mesh of n small cells, each of area no(1), with near-neighbor wiring: × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × Sort row of n0:5 cells in n0:5+o(1) seconds:
3 1 4 1 5 9 2 6 → 1 3 1 4 5 9 2 6
1 3 1 4 5 9 2 6 → 1 1 3 4 5 2 9 6
equals row length.
34
Spread array across square mesh of n small cells, each of area no(1), with near-neighbor wiring: × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × ×
35
Sort row of n0:5 cells in n0:5+o(1) seconds:
3 1 4 1 5 9 2 6 → 1 3 1 4 5 9 2 6
1 3 1 4 5 9 2 6 → 1 1 3 4 5 2 9 6
equals row length.
34
Spread array across square mesh of n small cells, each of area no(1), with near-neighbor wiring: × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × ×
35
Sort row of n0:5 cells in n0:5+o(1) seconds:
3 1 4 1 5 9 2 6 → 1 3 1 4 5 9 2 6
1 3 1 4 5 9 2 6 → 1 1 3 4 5 2 9 6
equals row length. Sort each row, in parallel, in a total of n0:5+o(1) seconds.
34
array across mesh of n small cells,
near-neighbor wiring: × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × ×
35
Sort row of n0:5 cells in n0:5+o(1) seconds:
3 1 4 1 5 9 2 6 → 1 3 1 4 5 9 2 6
1 3 1 4 5 9 2 6 → 1 1 3 4 5 2 9 6
equals row length. Sort each row, in parallel, in a total of n0:5+o(1) seconds. Sort all n in n0:5+o
in parallel,
With prop left-to-right/right-to-left for each that this
34
across small cells,
(1),
× × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × × ×
35
Sort row of n0:5 cells in n0:5+o(1) seconds:
3 1 4 1 5 9 2 6 → 1 3 1 4 5 9 2 6
1 3 1 4 5 9 2 6 → 1 1 3 4 5 2 9 6
equals row length. Sort each row, in parallel, in a total of n0:5+o(1) seconds. Sort all n cells in n0:5+o(1) seconds:
in parallel, if n >
With proper choice left-to-right/right-to-left for each row, can p that this sorts whole
34
cells, × × × × × × × × × × × × × × × × × × × ×
35
Sort row of n0:5 cells in n0:5+o(1) seconds:
3 1 4 1 5 9 2 6 → 1 3 1 4 5 9 2 6
1 3 1 4 5 9 2 6 → 1 1 3 4 5 2 9 6
equals row length. Sort each row, in parallel, in a total of n0:5+o(1) seconds. Sort all n cells in n0:5+o(1) seconds:
in parallel, if n > 1.
With proper choice of left-to-right/right-to-left for each row, can prove that this sorts whole array.
35
Sort row of n0:5 cells in n0:5+o(1) seconds:
3 1 4 1 5 9 2 6 → 1 3 1 4 5 9 2 6
1 3 1 4 5 9 2 6 → 1 1 3 4 5 2 9 6
equals row length. Sort each row, in parallel, in a total of n0:5+o(1) seconds.
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Sort all n cells in n0:5+o(1) seconds:
in parallel, if n > 1.
With proper choice of left-to-right/right-to-left for each row, can prove that this sorts whole array.
35
w of n0:5 cells
5+o(1) seconds:
each pair in parallel. 4 1 5 9 2 6 → 1 4 5 9 2 6 alternate pairs in parallel. 1 4 5 9 2 6 → 3 4 5 2 9 6 eat until number of steps equals row length. each row, in parallel, total of n0:5+o(1) seconds.
36
Sort all n cells in n0:5+o(1) seconds:
in parallel, if n > 1.
With proper choice of left-to-right/right-to-left for each row, can prove that this sorts whole array. For example, this 8 × 3 1 4 5 3 5 2 3 8 3 3 8 2 8 1 6 9 5 1 7 4 9
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cells seconds: in parallel. 6 → 6 pairs in parallel. 6 → 6 number of steps length. in parallel,
5+o(1) seconds.
36
Sort all n cells in n0:5+o(1) seconds:
in parallel, if n > 1.
With proper choice of left-to-right/right-to-left for each row, can prove that this sorts whole array. For example, assume this 8 × 8 array is 3 1 4 1 5 9 5 3 5 8 9 7 2 3 8 4 6 2 3 3 8 3 2 7 2 8 8 4 1 1 6 9 3 9 9 5 1 5 8 2 7 4 9 4 4 5
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rallel. parallel. steps seconds.
36
Sort all n cells in n0:5+o(1) seconds:
in parallel, if n > 1.
With proper choice of left-to-right/right-to-left for each row, can prove that this sorts whole array. For example, assume that this 8 × 8 array is in cells: 3 1 4 1 5 9 2 6 5 3 5 8 9 7 9 3 2 3 8 4 6 2 6 4 3 3 8 3 2 7 9 5 2 8 8 4 1 9 7 1 6 9 3 9 9 3 7 5 1 5 8 2 9 7 4 9 4 4 5 9 2
36
Sort all n cells in n0:5+o(1) seconds:
in parallel, if n > 1.
With proper choice of left-to-right/right-to-left for each row, can prove that this sorts whole array.
37
For example, assume that this 8 × 8 array is in cells: 3 1 4 1 5 9 2 6 5 3 5 8 9 7 9 3 2 3 8 4 6 2 6 4 3 3 8 3 2 7 9 5 2 8 8 4 1 9 7 1 6 9 3 9 9 3 7 5 1 5 8 2 9 7 4 9 4 4 5 9 2
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ll n cells
5+o(1) seconds:
Recursively sort quadrants parallel, if n > 1. each column in parallel. each row in parallel. each column in parallel. each row in parallel. roper choice of left-to-right/right-to-left h row, can prove this sorts whole array.
37
For example, assume that this 8 × 8 array is in cells: 3 1 4 1 5 9 2 6 5 3 5 8 9 7 9 3 2 3 8 4 6 2 6 4 3 3 8 3 2 7 9 5 2 8 8 4 1 9 7 1 6 9 3 9 9 3 7 5 1 5 8 2 9 7 4 9 4 4 5 9 2 Recursively top →, b 1 1 2 3 3 3 3 4 4 5 8 8 1 1 4 4 3 7 6 5 9 9 8
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seconds: rt quadrants > 1. column in parallel. in parallel. column in parallel. in parallel.
left-to-right/right-to-left can prove whole array.
37
For example, assume that this 8 × 8 array is in cells: 3 1 4 1 5 9 2 6 5 3 5 8 9 7 9 3 2 3 8 4 6 2 6 4 3 3 8 3 2 7 9 5 2 8 8 4 1 9 7 1 6 9 3 9 9 3 7 5 1 5 8 2 9 7 4 9 4 4 5 9 2 Recursively sort quadrants, top →, bottom ← 1 1 2 3 2 2 3 3 3 3 4 5 3 4 4 5 6 6 5 8 8 8 9 9 1 1 2 2 4 4 3 2 5 4 7 6 5 5 9 8 9 9 8 8 9 9
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quadrants rallel. rallel. rallel. rallel. .
37
For example, assume that this 8 × 8 array is in cells: 3 1 4 1 5 9 2 6 5 3 5 8 9 7 9 3 2 3 8 4 6 2 6 4 3 3 8 3 2 7 9 5 2 8 8 4 1 9 7 1 6 9 3 9 9 3 7 5 1 5 8 2 9 7 4 9 4 4 5 9 2 Recursively sort quadrants, top →, bottom ←: 1 1 2 3 2 2 2 3 3 3 3 3 4 5 5 6 3 4 4 5 6 6 7 7 5 8 8 8 9 9 9 9 1 1 2 2 1 4 4 3 2 5 4 4 3 7 6 5 5 9 8 7 7 9 9 8 8 9 9 9 9
37
For example, assume that this 8 × 8 array is in cells: 3 1 4 1 5 9 2 6 5 3 5 8 9 7 9 3 2 3 8 4 6 2 6 4 3 3 8 3 2 7 9 5 2 8 8 4 1 9 7 1 6 9 3 9 9 3 7 5 1 5 8 2 9 7 4 9 4 4 5 9 2
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Recursively sort quadrants, top →, bottom ←: 1 1 2 3 2 2 2 3 3 3 3 3 4 5 5 6 3 4 4 5 6 6 7 7 5 8 8 8 9 9 9 9 1 1 2 2 1 4 4 3 2 5 4 4 3 7 6 5 5 9 8 7 7 9 9 8 8 9 9 9 9
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example, assume that × 8 array is in cells: 4 1 5 9 2 6 5 8 9 7 9 3 8 4 6 2 6 4 8 3 2 7 9 5 8 8 4 1 9 7 9 3 9 9 3 7 5 8 2 9 9 4 4 5 9 2
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Recursively sort quadrants, top →, bottom ←: 1 1 2 3 2 2 2 3 3 3 3 3 4 5 5 6 3 4 4 5 6 6 7 7 5 8 8 8 9 9 9 9 1 1 2 2 1 4 4 3 2 5 4 4 3 7 6 5 5 9 8 7 7 9 9 8 8 9 9 9 9 Sort each in parallel: 1 1 1 1 2 3 3 3 3 4 3 4 4 4 5 6 5 7 8 8 9 9 8
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assume that is in cells: 9 2 6 7 9 3 2 6 4 7 9 5 1 9 7 9 3 7 2 9 5 9 2
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Recursively sort quadrants, top →, bottom ←: 1 1 2 3 2 2 2 3 3 3 3 3 4 5 5 6 3 4 4 5 6 6 7 7 5 8 8 8 9 9 9 9 1 1 2 2 1 4 4 3 2 5 4 4 3 7 6 5 5 9 8 7 7 9 9 8 8 9 9 9 9 Sort each column in parallel: 1 1 2 2 1 1 2 2 2 2 3 3 3 3 4 4 3 4 3 3 5 5 4 4 4 5 6 6 5 6 5 5 9 8 7 8 8 8 9 9 9 9 8 8 9 9
37 38
Recursively sort quadrants, top →, bottom ←: 1 1 2 3 2 2 2 3 3 3 3 3 4 5 5 6 3 4 4 5 6 6 7 7 5 8 8 8 9 9 9 9 1 1 2 2 1 4 4 3 2 5 4 4 3 7 6 5 5 9 8 7 7 9 9 8 8 9 9 9 9 Sort each column in parallel: 1 1 2 2 1 1 1 2 2 2 2 2 3 3 3 3 3 4 4 4 3 3 4 3 3 5 5 5 6 4 4 4 5 6 6 7 7 5 6 5 5 9 8 7 7 7 8 8 8 9 9 9 9 9 9 8 8 9 9 9 9
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Recursively sort quadrants, top →, bottom ←: 1 1 2 3 2 2 2 3 3 3 3 3 4 5 5 6 3 4 4 5 6 6 7 7 5 8 8 8 9 9 9 9 1 1 2 2 1 4 4 3 2 5 4 4 3 7 6 5 5 9 8 7 7 9 9 8 8 9 9 9 9
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Sort each column in parallel: 1 1 2 2 1 1 1 2 2 2 2 2 3 3 3 3 3 4 4 4 3 3 4 3 3 5 5 5 6 4 4 4 5 6 6 7 7 5 6 5 5 9 8 7 7 7 8 8 8 9 9 9 9 9 9 8 8 9 9 9 9
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Recursively sort quadrants, , bottom ←: 2 3 2 2 2 3 3 3 4 5 5 6 4 5 6 6 7 7 8 8 9 9 9 9 2 2 1 3 2 5 4 4 3 5 5 9 8 7 7 8 8 9 9 9 9
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Sort each column in parallel: 1 1 2 2 1 1 1 2 2 2 2 2 3 3 3 3 3 4 4 4 3 3 4 3 3 5 5 5 6 4 4 4 5 6 6 7 7 5 6 5 5 9 8 7 7 7 8 8 8 9 9 9 9 9 9 8 8 9 9 9 9 Sort each alternately 3 2 2 3 3 3 6 5 5 4 4 4 9 8 7 7 8 8 9 9 9
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quadrants, ←: 2 2 3 5 5 6 6 7 7 9 9 9 2 1 4 4 3 8 7 7 9 9 9
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Sort each column in parallel: 1 1 2 2 1 1 1 2 2 2 2 2 3 3 3 3 3 4 4 4 3 3 4 3 3 5 5 5 6 4 4 4 5 6 6 7 7 5 6 5 5 9 8 7 7 7 8 8 8 9 9 9 9 9 9 8 8 9 9 9 9 Sort each row in pa alternately ←, →: 1 1 1 3 2 2 2 2 2 3 3 3 3 3 4 6 5 5 5 4 3 4 4 4 5 6 6 9 8 7 7 6 5 7 8 8 8 9 9 9 9 9 9 9 9
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quadrants,
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Sort each column in parallel: 1 1 2 2 1 1 1 2 2 2 2 2 3 3 3 3 3 4 4 4 3 3 4 3 3 5 5 5 6 4 4 4 5 6 6 7 7 5 6 5 5 9 8 7 7 7 8 8 8 9 9 9 9 9 9 8 8 9 9 9 9 Sort each row in parallel, alternately ←, →: 1 1 1 2 2 3 2 2 2 2 2 1 1 3 3 3 3 3 4 4 4 6 5 5 5 4 3 3 3 4 4 4 5 6 6 7 7 9 8 7 7 6 5 5 5 7 8 8 8 9 9 9 9 9 9 9 9 9 9 8 8
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Sort each column in parallel: 1 1 2 2 1 1 1 2 2 2 2 2 3 3 3 3 3 4 4 4 3 3 4 3 3 5 5 5 6 4 4 4 5 6 6 7 7 5 6 5 5 9 8 7 7 7 8 8 8 9 9 9 9 9 9 8 8 9 9 9 9
40
Sort each row in parallel, alternately ←, →: 1 1 1 2 2 3 2 2 2 2 2 1 1 3 3 3 3 3 4 4 4 6 5 5 5 4 3 3 3 4 4 4 5 6 6 7 7 9 8 7 7 6 5 5 5 7 8 8 8 9 9 9 9 9 9 9 9 9 9 8 8
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each column rallel: 2 2 1 2 2 2 2 2 3 3 3 4 4 4 3 3 3 5 5 5 6 4 5 6 6 7 7 5 5 9 8 7 7 8 8 9 9 9 9 8 8 9 9 9 9
40
Sort each row in parallel, alternately ←, →: 1 1 1 2 2 3 2 2 2 2 2 1 1 3 3 3 3 3 4 4 4 6 5 5 5 4 3 3 3 4 4 4 5 6 6 7 7 9 8 7 7 6 5 5 5 7 8 8 8 9 9 9 9 9 9 9 9 9 9 8 8 Sort each in parallel: 3 2 2 3 3 3 4 4 4 6 5 5 7 8 7 9 8 8 9 9 9
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column 2 1 2 2 3 4 4 3 5 5 6 6 7 7 8 7 7 9 9 9 9 9 9
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Sort each row in parallel, alternately ←, →: 1 1 1 2 2 3 2 2 2 2 2 1 1 3 3 3 3 3 4 4 4 6 5 5 5 4 3 3 3 4 4 4 5 6 6 7 7 9 8 7 7 6 5 5 5 7 8 8 8 9 9 9 9 9 9 9 9 9 9 8 8 Sort each column in parallel: 1 1 1 3 2 2 2 2 2 3 3 3 3 3 3 4 4 4 5 4 4 6 5 5 5 6 5 7 8 7 7 6 6 9 8 8 8 9 9 9 9 9 9 9 9
39 40
Sort each row in parallel, alternately ←, →: 1 1 1 2 2 3 2 2 2 2 2 1 1 3 3 3 3 3 4 4 4 6 5 5 5 4 3 3 3 4 4 4 5 6 6 7 7 9 8 7 7 6 5 5 5 7 8 8 8 9 9 9 9 9 9 9 9 9 9 8 8 Sort each column in parallel: 1 1 1 1 1 3 2 2 2 2 2 2 2 3 3 3 3 3 3 3 3 4 4 4 5 4 4 4 4 6 5 5 5 6 5 5 5 7 8 7 7 6 6 7 7 9 8 8 8 9 9 8 8 9 9 9 9 9 9 9 9
40
Sort each row in parallel, alternately ←, →: 1 1 1 2 2 3 2 2 2 2 2 1 1 3 3 3 3 3 4 4 4 6 5 5 5 4 3 3 3 4 4 4 5 6 6 7 7 9 8 7 7 6 5 5 5 7 8 8 8 9 9 9 9 9 9 9 9 9 9 8 8
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Sort each column in parallel: 1 1 1 1 1 3 2 2 2 2 2 2 2 3 3 3 3 3 3 3 3 4 4 4 5 4 4 4 4 6 5 5 5 6 5 5 5 7 8 7 7 6 6 7 7 9 8 8 8 9 9 8 8 9 9 9 9 9 9 9 9
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each row in parallel, alternately ←, →: 1 1 1 2 2 2 2 2 2 1 1 3 3 3 4 4 4 5 5 4 3 3 3 4 5 6 6 7 7 7 7 6 5 5 5 8 8 9 9 9 9 9 9 9 9 8 8
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Sort each column in parallel: 1 1 1 1 1 3 2 2 2 2 2 2 2 3 3 3 3 3 3 3 3 4 4 4 5 4 4 4 4 6 5 5 5 6 5 5 5 7 8 7 7 6 6 7 7 9 8 8 8 9 9 8 8 9 9 9 9 9 9 9 9 Sort each ← or → 2 2 2 3 3 3 4 4 4 5 5 5 6 6 7 8 8 8 9 9 9
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parallel, : 1 2 2 2 1 1 4 4 4 3 3 3 6 7 7 5 5 5 9 9 9 9 8 8
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Sort each column in parallel: 1 1 1 1 1 3 2 2 2 2 2 2 2 3 3 3 3 3 3 3 3 4 4 4 5 4 4 4 4 6 5 5 5 6 5 5 5 7 8 7 7 6 6 7 7 9 8 8 8 9 9 8 8 9 9 9 9 9 9 9 9 Sort each row in pa ← or → as desired: 1 1 1 2 2 2 2 2 2 3 3 3 3 3 3 4 4 4 4 4 4 5 5 5 5 5 5 6 6 7 7 7 7 8 8 8 8 8 9 9 9 9 9 9 9
40 41
Sort each column in parallel: 1 1 1 1 1 3 2 2 2 2 2 2 2 3 3 3 3 3 3 3 3 4 4 4 5 4 4 4 4 6 5 5 5 6 5 5 5 7 8 7 7 6 6 7 7 9 8 8 8 9 9 8 8 9 9 9 9 9 9 9 9 Sort each row in parallel, ← or → as desired: 1 1 1 1 1 2 2 2 2 2 2 2 3 3 3 3 3 3 3 3 3 4 4 4 4 4 4 4 5 5 5 5 5 5 5 6 6 6 6 7 7 7 7 7 8 8 8 8 8 8 9 9 9 9 9 9 9 9 9 9 9
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Sort each column in parallel: 1 1 1 1 1 3 2 2 2 2 2 2 2 3 3 3 3 3 3 3 3 4 4 4 5 4 4 4 4 6 5 5 5 6 5 5 5 7 8 7 7 6 6 7 7 9 8 8 8 9 9 8 8 9 9 9 9 9 9 9 9
42
Sort each row in parallel, ← or → as desired: 1 1 1 1 1 2 2 2 2 2 2 2 3 3 3 3 3 3 3 3 3 4 4 4 4 4 4 4 5 5 5 5 5 5 5 6 6 6 6 7 7 7 7 7 8 8 8 8 8 8 9 9 9 9 9 9 9 9 9 9 9
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each column rallel: 1 1 1 1 1 2 2 2 2 2 2 3 3 3 3 3 3 4 5 4 4 4 4 5 5 6 5 5 5 7 7 6 6 7 7 8 8 9 9 8 8 9 9 9 9 9 9
42
Sort each row in parallel, ← or → as desired: 1 1 1 1 1 2 2 2 2 2 2 2 3 3 3 3 3 3 3 3 3 4 4 4 4 4 4 4 5 5 5 5 5 5 5 6 6 6 6 7 7 7 7 7 8 8 8 8 8 8 9 9 9 9 9 9 9 9 9 9 9 Chips are towards parallelism GPUs: pa Old Xeon New Xeon
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column 1 1 1 2 2 2 3 3 3 4 4 4 5 5 5 6 7 7 9 8 8 9 9 9
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Sort each row in parallel, ← or → as desired: 1 1 1 1 1 2 2 2 2 2 2 2 3 3 3 3 3 3 3 3 3 4 4 4 4 4 4 4 5 5 5 5 5 5 5 6 6 6 6 7 7 7 7 7 8 8 8 8 8 8 9 9 9 9 9 9 9 9 9 9 9 Chips are in fact evolving towards having this parallelism and communication. GPUs: parallel + global Old Xeon Phi: parallel New Xeon Phi: pa
41 42
Sort each row in parallel, ← or → as desired: 1 1 1 1 1 2 2 2 2 2 2 2 3 3 3 3 3 3 3 3 3 4 4 4 4 4 4 4 5 5 5 5 5 5 5 6 6 6 6 7 7 7 7 7 8 8 8 8 8 8 9 9 9 9 9 9 9 9 9 9 9 Chips are in fact evolving towards having this much parallelism and communication. GPUs: parallel + global RAM. Old Xeon Phi: parallel + ring. New Xeon Phi: parallel + mesh.
42
Sort each row in parallel, ← or → as desired: 1 1 1 1 1 2 2 2 2 2 2 2 3 3 3 3 3 3 3 3 3 4 4 4 4 4 4 4 5 5 5 5 5 5 5 6 6 6 6 7 7 7 7 7 8 8 8 8 8 8 9 9 9 9 9 9 9 9 9 9 9
43
Chips are in fact evolving towards having this much parallelism and communication. GPUs: parallel + global RAM. Old Xeon Phi: parallel + ring. New Xeon Phi: parallel + mesh.
42
Sort each row in parallel, ← or → as desired: 1 1 1 1 1 2 2 2 2 2 2 2 3 3 3 3 3 3 3 3 3 4 4 4 4 4 4 4 5 5 5 5 5 5 5 6 6 6 6 7 7 7 7 7 8 8 8 8 8 8 9 9 9 9 9 9 9 9 9 9 9
43
Chips are in fact evolving towards having this much parallelism and communication. GPUs: parallel + global RAM. Old Xeon Phi: parallel + ring. New Xeon Phi: parallel + mesh. Algorithm designers don’t even get the right exponent without taking this into account.
42
Sort each row in parallel, ← or → as desired: 1 1 1 1 1 2 2 2 2 2 2 2 3 3 3 3 3 3 3 3 3 4 4 4 4 4 4 4 5 5 5 5 5 5 5 6 6 6 6 7 7 7 7 7 8 8 8 8 8 8 9 9 9 9 9 9 9 9 9 9 9
43
Chips are in fact evolving towards having this much parallelism and communication. GPUs: parallel + global RAM. Old Xeon Phi: parallel + ring. New Xeon Phi: parallel + mesh. Algorithm designers don’t even get the right exponent without taking this into account. Shock waves from subroutines into high-level algorithm design.