CPU Modeling Chapter 10 Part II 1 Parwan Accumulator ENTITY - - PowerPoint PPT Presentation

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CPU Modeling Chapter 10 Part II 1 Parwan Accumulator ENTITY - - PowerPoint PPT Presentation

Nov 05, 2022 368 likes •581 views

CPU Modeling Chapter 10 Part II 1 Parwan Accumulator ENTITY accumulator_unit IS PORT( i8:IN byte; o8: OUT byte; load,zero,clk:IN BIT ); END; 2 Parwan Accumulator ARCHIECTURE dataflow OF accumulator_unit IS BEGIN

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SLIDE 1

1

CPU Modeling

Chapter 10 Part II

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SLIDE 2

2

Parwan Accumulator

ENTITY accumulator_unit IS PORT( i8:IN byte;

  • 8: OUT byte;

load,zero,clk:IN BIT ); END;

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SLIDE 3

3

Parwan Accumulator

ARCHIECTURE dataflow OF accumulator_unit IS BEGIN

Enable:BLOCK(load=‘1’) BEGIN

clocking:BLOCK((clk=‘1’ AND NOT clk’STABLE) AND GUARD) BEGIN

  • 8<=GUARDED “00000000” WHEN zero=‘1’ ELSE i8;

END;

END BLOCK;

END;

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SLIDE 4

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Parwan IR

ENTITY instruction_register IS PORT( i8:IN byte;

  • 8: OUT byte;

load,clk:IN BIT ); END;

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SLIDE 5

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Parwan IR

ARCHIECTURE dataflow OF instruction_register IS

BEGIN

Enable:BLOCK(load=‘1’) BEGIN

clocking:BLOCK((clk=‘1’ AND NOT clk’STABLE) AND GUARD) BEGIN

  • 8<=GUARDED i8;

END;

END BLOCK;

END;

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SLIDE 6

6

Parwan PC

ENTITY program_counter_unit IS PORT( i12:IN twelve;

  • 12: OUT twelve;

increment,load_page:IN BIT load_offset,reset,clk:IN BIT ); END;

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SLIDE 7

7

Parwan PC

ARCHIECTURE behavioral OF program_counter_unit IS BEGIN PROCESS(clk) VARIABLE internal_state:twelve:=zero_12; BEGIN if(clk=‘0’) THEN IF(reset=‘1’) THEN internal_state:=zero_12; ELSIF(increment=‘1’) THEN internal_state:=inc(internal_state); ELSE

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SLIDE 8

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Parwan PC

IF(load_pgae=‘1’) THEN internal_state(11 downto 8):=i12(11 downto 8); END IF; IF(load_offset=‘1’) THEN internal_state(7 downto 0):=i12(7 downto 0); END IF; END IF:

  • 12<=internal_state;

END IF; END PROCESS; END;

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SLIDE 9

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Parwna AR

ENTITY memory_address_register_unit IS PORT( i12:IN twelve;

  • 12: OUT twelve;

increment,load_page:IN BIT load_offset,clk:IN BIT ); END;

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SLIDE 10

10

Parwna AR

ARCHIECTURE behavioral OF memory_address_register_unit IS BEGIN PROCESS(clk) VARIABLE internal_state:twelve:=zero_12; BEGIN if(clk=‘0’) THEN IF(load_pgae=‘1’) THEN internal_state(11 downto 8):=i12(11 downto 8); END IF; IF(load_offset=‘1’) THEN internal_state(7 downto 0):=i12(7 downto 0); END IF;

  • 12<=internal_state;

END IF; END PROCESS; END;

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SLIDE 11

11

Parwan Data Section

ENTITY par_data_path IS PORT( clk: IN BIT;

  • -registers controls

load_ac,zero_ac,load_ir,increment_pc: IN qit; load_page_pc,load_offset_pc,reset_pc: IN qit; load_page_mar,load_offset_mar: IN qit; load_sr,cm_carry_sr: IN qit;

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SLIDE 12

12

Parwan Data Section

pc_on_mar_page_bus,ir_on_mar_page_bus: IN qit; pc_on_mar_offset_bus,ir_on_mar_offset_bus: IN qit; pc_offset_on_dbus,obus_on_dbus: IN qit; databus_on_dbus,mar_on_adbus: IN qit; dbus_on_data_bus: IN qit;

  • -logic unit functions

arith_shift_left,arith_shift_right,alu_and : IN qit; alu_not,alu_a,alu_b,alu_add,alu_sub: IN qit;

  • -outputs

ir_lines : OUT byte; status : OUT nibble ); END;

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SLIDE 13

13

Parwan Data Section

ARCHIECTURE structural OF par_data_path IS SIGNAL alu_a_input:byte; SIGNAL pc_out,mar_out:twelve; SIGNAL dbus:wired_byte BUS; SIGNAL alu_flags,shu_flags,sr_out:nibble; SIGNAL mar_bus:wired_twelve BUS; SIGNAL mar_input:twelve; …

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SLIDE 14

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Parwan Data Section

BEGIN

  • -bus connections

Dbus1:alu_a_inp<=qit_vector(dbus); Dbus2:BLOCK(dbus_on_mar_offset_bus=‘1’) BEGIN mar_bus(7 downto 0)<=GUARDED dbus; END BLOCK; Dbus2:BLOCK(dbus_on_databus=‘1’) BEGIN databus<=GUARDED dbus; END BLOCK;

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15

Parwan Data Section

  • -bus connections

Mar_bus1:mar_inp<=qit_vector(mar_bus);

  • bus1:BLOCK(obus_on_dbus=‘1’)

BEGIN dbus<=GUARDED wired_qit_vector(obus); END BLOCK; databus1:BLOCK(databus_on_dbus=‘1’) BEGIN dbus<=GUARDED databus; END BLOCK;

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SLIDE 16

16

Parwan Data Section

  • -register connections

R1:ENTITY WRK.accumulator_unit PORT MAP(obus,ac_out,load_ac,zero_ac,clk); R2:ENTITY WRK.instruction_register PORT MAP(obus,ir_out,load_ir,clk); ir1:ir_lines<=ir_out; ir2: BLOCK(ir_on_mar_page_bus=‘1’) BEGIN

mar_bus(11 downto 8)<=GUARDED wired_qit_vector(ir_out(3 downto 0));

END BLOCK;

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Parwan Data Section

  • -register connections

R3:ENTITY WRK.program_counter_unit PORT MAP(mar_out,pc_out,incrementpc,load_page_pc,load_offset_pc,reset_pc,clk); pc1: BLOCK(pc_on_mar_page_bus=‘1’) BEGIN mar_bus(11 downto 8)<=GUARDED wired_qit_vector(pc_out(11 downto 8)); END BLOCK; pc2: BLOCK(pc_on_mar_offset_bus=‘1’) BEGIN mar_bus(7 downto 0)<=GUARDED wired_qit_vector(pc_out(7 downto 0)); END BLOCK; pc3: BLOCK(pc_offset_on_dbus=‘1’) BEGIN adbus<=GUARDED mar_out; END BLOCK;

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SLIDE 18

18

Parwan Data Section

  • -register connections

R4:ENTITY WRK.memory_address_register_unit PORT MAP(mar_inp,mar_out,load_page_mar,load_offset_mar,clk); mar1: BLOCK(mar_on_dbus=‘1’) BEGIN adbus<=GUARDED mar_out; END BLOCK;

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SLIDE 19

19

Parwan Data Section

  • -register connections

R5:ENTITY WRK. Status_register PORT MAP(shu_flags,sr_out,load_sr,cm_carry_sr,clk); sr1: status<=sr_out;

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SLIDE 20

20

Parwan Data Section

  • -subcomponents

I1:ENTITY WRK. alu PORT MAP(alu_a_inp,ac_out,alu_and,alu_not,alu_a,alu_add,alu_add, alu_sub,sr_out,alu_out,alu_flags); I2:ENTITY WRK. shu PORT MAP(alu_out,arith_shift_left,arith_shift_right,alu_flags,obus, shu_flags); END structural;