Computer Organization Introduction CS301 Prof. Szajda Fall 2017 - - PowerPoint PPT Presentation

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Computer Organization Introduction CS301 Prof. Szajda Fall 2017 - - PowerPoint PPT Presentation

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Computer Organization Introduction CS301 Prof. Szajda Fall 2017 Course Logistics Prof Szajda w Jepson 219 w dszajda@richmond.edu w 287-6671 Meeting Times w Lecture: TR 10:30-11:45 (in Jepson 231) w Lab: W 12:00-12:50 (in Jepson G30) w O

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SLIDE 1

Computer Organization

Introduction CS301

  • Prof. Szajda

Fall 2017

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SLIDE 2

Course Logistics

  • Prof Szajda

w Jepson 219 w dszajda@richmond.edu w 287-6671

  • Meeting Times

w Lecture: TR 10:30-11:45 (in Jepson 231) w Lab: W 12:00-12:50 (in Jepson G30) w Offjce Hours: § TBD

§ and by appointment

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SLIDE 3

Course Logistics

Grading

  • Two Tests

30%

  • Final Exam

25%

  • Labs

20%

  • Homework

10%

  • Final Programming

Project 15% Important Dates

  • Thurs., Oct. 5

w Exam 1

  • Thurs., Nov 16

w Exam 2

  • Thurs., Dec. 14

w Final Exam (9am-noon)

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SLIDE 4

Textbook

  • Computer Organization and Design:

The Hardware/Software Interface, 5th Edition, by Patterson and Hennessey

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SLIDE 5

Graded Work Policies

  • Collaboration

w You may discuss homework and other non-exam assignments with other students in this class w “Empty Hands” policy (see syllabus)

§ Must leave any discussion/communication without any written or otherwise recorded material § Must note who you worked with on assignment

  • Late Work is absolutely not accepted!

w It is diffjcult enough to keep up with grading in this course even when material is submitted on time!

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SLIDE 6

Attendance Policy

  • I expect you to attend class and to

participate (meaning, don’t come if you’re going to sleep)

  • DO NOT use your laptop/tablet/digital

device during class for any function other than taking notes. w Surf the web and read email on your own time

  • If you miss 4 or more days of class

(including labs), I can (and will) give you a grade of “V”

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SLIDE 7

Reading

  • Read over syllabus
  • Read Chapter 1
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SLIDE 8

What is this Course About?

  • How do we design today’s computer

systems?

w Intel Core i7 at 3.3 GHz w 6 cores – 2 threads each w 15 MB Shared cache w 64 GB Main Memory

  • Starting with something that

can only represent a 0 or a 1?

Transistor

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SLIDE 9

Basics Behind Lots of Processors

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SLIDE 10

High Level Info About Course

  • Required for major or minor
  • Prerequisite for many upper level

courses

w Material and skills you learn will be necessary for later courses Of course, what you get out of this course depends on the effort you put into it!

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SLIDE 11

Specific Topics

  • SW/HW Interface

w Assembly languages and instruction encoding

  • Processor Construction and Design

w How to build simple processor from simple circuits

  • Memory System Design

w How to construct a memory system that keeps processor fed

  • I/O Devices

w How processor interacts with disk, mouse, etc.

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SLIDE 12

Skill Development

  • Many of these are taught in CS240 and

will be further developed via assignments in this course

w Object oriented design w Systematic testing w Debugging with a debugger w Learning on your own

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SLIDE 13

Computer Architecture
 Overview

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SLIDE 14

What is a Computer?

Program software Write compilers Design assembly language Design processor Optimize layout, circuits, etc Design transistor technology Architecture

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SLIDE 15

Where do Logic Circuits Fit?

Program software Write compilers Design assembly language Design processor Optimize layout, circuits, etc Design transistor technology How do I put together registers, adders, SRAM, etc?

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SLIDE 16

Where do Logic Circuits Fit?

Program software Write compilers Design assembly language Design processor Optimize layout, circuits, etc Design transistor technology How do I design register files, adders, etc. out

  • f boolean

gates?

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SLIDE 17

Where do Logic Circuits Fit?

Program software Write compilers Design assembly language Design processor Optimize layout, circuits, etc Design transistor technology How do I design boolean gates

  • ut of

transistors and put them on silicon?

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SLIDE 18

What about Software?

Program software Write compilers Design assembly language Design processor Optimize layout, circuits, etc Design transistor technology Software

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SLIDE 19

Where do HW and SW Meet?

Program software Write compilers Design assembly language Design processor Optimize layout, circuits, etc Design transistor technology Hardware / Software Interface

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SLIDE 20

System Components

  • Processor

w Datapath w Control

  • Memory
  • Input and output (I/O)
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SLIDE 21

Anatomy of a Computer

Output device Input device Input device Network cable

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SLIDE 22

Mice

  • Optical mouse

w LED illuminates desktop w Small low-res camera w Basic image processor

§ Looks for x, y movement

w Buttons & wheel

  • Supersedes roller-

ball mechanical mouse

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SLIDE 23

Display

  • LCD screen: picture elements (pixels)

w Mirrors content of frame bufger memory

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SLIDE 24
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SLIDE 25

DIMM

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SLIDE 26

Nonvolatile Storage

  • Volatile main memory

w Loses instructions and data when power ofg

  • Non-volatile secondary memory

w Magnetic disk w Flash memory w Optical disk (CDROM, DVD)

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SLIDE 27

Networks

  • Communication and resource sharing
  • Local area network (LAN): Ethernet

w Within a building

  • Wide area network (WAN): the Internet
  • Wireless network: WiFi, Bluetooth
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SLIDE 28

Software Terminology

Instruction Set Architecture (ISA) Operating System vs. User program System Software: includes OS and compiler

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SLIDE 29

Software Terminology

  • Binary or executable

w Compiler w Assembler

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SLIDE 30
  • In order to build circuits that implement logic, we need voltage-

controlled switches

  • Control input = 1 à Switch is closed
  • Control input = 0 à Switch is open
  • This can be accomplished with electro-mechanical relays
  • Large, clunky, power-hungry
  • Transistors are a better way
  • Tiny, efficient, fast

Why binary?

A B Control

Source Drain Gate Three slides from http://oa-003.spu.edu/bolding/EE1210/070-NMOS-CMOS.ppt

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SLIDE 31

MOS Semiconductor

Silicon Bulk (p-type)

+ + + + + + + + + + + + + + + + + + + + + + +

e- e- e- e- e- e- e- e- e-

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

e- e- e- e- e-

Source

e- e- e- e-

Drain Gate

n-type Si n-type Si Source Wire Gate Wire

Oxide

P-type silicon: Excess positive charges (electron holes) N-type silicon: Excess negative charges (electrons) Oxide: Insulator Gate: Metal pad In this state, current (electrons) cannot flow between source and drain – switch is OPEN

Drain Wire

MOS: “Metal Oxide Semiconductor” this is nMOS (source/drain n-type)

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SLIDE 32

MOS Semiconductor

Silicon Bulk (p-type)

+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +

e- e- e- e- e-

Source

e- e- e- e-

Drain Gate

n-type Si n-type Si Source Wire Gate Wire

Oxide

+5V

+ + + + + + + + +

e- e- e-

Place a positive charge on the gate wire (gate = +5V) The gate’s positive charge attracts negatively-charged electrons This row of electrons forms a channel connecting the Source and Drain – Current can flow – Switch is CLOSED

Drain Wire

e-e-e-e-e- e-e-e-

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SLIDE 33

Transistors

  • Transistors

w Store 0 or 1 when on

  • r ofg

w Can connect transistors in series

  • r parallel to create

larger building blocks called gates

Pull-up pMOS
 transistor Pull-down
 nMOS transistor

GND +5V A Z

CMOS Inverter created from two transistors

CMOS: Complementary Metal Oxide Semiconductor

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SLIDE 34

Technology: Microprocessor Logic Density

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SLIDE 35

Technology: Microprocessor Logic Density

35

Source: http://www.nature.com/nature/journal/v479/n7373/full/nature10676.html

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SLIDE 36

36

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SLIDE 37

37

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SLIDE 38

Billion Transistor Chips

Intel Core i7 Extreme Edition - 2.27 billion transistors, 435 mm^2 area

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SLIDE 39

Growing Silicon

  • Silicon is a crystal grown in a

vat

  • It comes out the shape of a

cylinder

  • This is called an ingot
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SLIDE 40

Creating Chips

  • Sliced into thin discs

called wafers

  • Etch grooves and pour

metal, etc w 20 - 40 steps

  • Cut the wafer into dies
  • r chips
  • A flaw is called a defect
  • The percentage of good
  • nes is yield

wafer chip or die defect Yield: 8/10 = 80% (not realistic) Manufacturers secretive about yields, but can be as low as 30%

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SLIDE 41

Cost

  • Cost per die

w (CostPerWafer) / ((DiesPerWafer)*Yield)

  • Dies per wafer

w (Wafer area / Die area) – wasted edge space

  • Yield

w 1 / (1 + (DefectPerArea * DieArea/2))2

§ 2 in denominator is ``alpha’’ which is determined by number of masking levels used (a measure of manufacturing complexity)

  • Cheapest when yield is high and dies per wafer

are high

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SLIDE 42

Current Chip Trends

  • Shrinking Technology

w Reported in microns (width of wire) w Each generation allows more to fit in same space w Defect rate gradually falls in time with same technology

  • Increasing Area

w Yield – Increases chance of a defect on die w Dies/wafer –fewer dies, more wasted space