Cognitive Radio Platform Technology Ivan Seskar WINLAB Rutgers, - - PowerPoint PPT Presentation

WINLAB

Ivan Seskar Rutgers, The State University of New Jersey www.winlab.rutgers.edu seskar (at) winlab (dot) rutgers (dot) edu

Cognitive Radio Platform Technology

WINLAB

Complexity/Performance Tradeoffs

Protocol Complexity (degree of coordination) “Open Access”

+ smart radios

Hardware Complexity

Unlicensed band + simple coord protocols

Reactive Rate/Power Control Reactive Rate/Power Control Agile Wideband Radios Agile Wideband Radios Unlicensed Band with DCA (e.g. 802.11x) Unlicensed Band with DCA (e.g. 802.11x) Internet Server-based Spectrum Etiquette Internet Server-based Spectrum Etiquette Ad-hoc, Multi-hop Collaboration Ad-hoc, Multi-hop Collaboration Radio-level Spectrum Etiquette Protocol Radio-level Spectrum Etiquette Protocol

Static Assignme nt Static Assignme nt

Internet Spectrum Leasing Internet Spectrum Leasing

“cognitive radio” schemes

UWB, Spread Spectrum UWB, Spread Spectrum Cooperative Coding, Signal Processing Cooperative Coding, Signal Processing

Efficient operation requires radios that can:



Discover



Self-Organize into hierarchical networks



Cooperate



Collaborate

Problems with existing (experimental) platforms:



“Analog” issues: range (frequency, power), agility, cost, future proofing



“Digital” issues: power consumption, performance vs. flexibility, cost,

future proofing



Ease of “use” issues: how do we program/ control these platforms? L

• w

p

• w

e r F G P A ’ s

• r

m a s s i v e l y p a r a l l e l C P U s i n h a n d h e l d s ?

Do we wait for Moore’s law to catch up or we need new hardware architectures for CR?

WINLAB



Cost effective solution tailored for ISM/ UNII bands

 No on-board memory  Modest FPGA resources (Spartan

XC3S400)

 8-bit CPU  USB host transfer  Used as noise generator/ spectrum

sensor in Orbit

Low Cost Programmable Radio (LCPR)

WINLAB

WARP Platform (Rice University)



Xilinx Virtex-II Pro (Xilinx XC2VP70 ) FPGA



10/ 100 Ethernet



4 Daughtercard Slots



RS-232 UART



16-bit Digital I/ O



Radio dauthercard



2 x 160MS/ s 16-bit DAC



2 x 65MS/ s 14-bit dual-ADC



dual-band ISM/ UNII RF (2400-2500MHz, 4900- 5875MHz) - MIMO capable



20 or 40MHz baseband bandwidth

Design flows:

• Real-time – OFDM
• Non-real-time (interfaces for

MATLAB ) – SISO and MIMO

WINLAB

USRP/USRP2 with GNU Radio Platform



IF 0-100 MHz (50 MHz transmit)



128 MS/ s DAC



64 MS/ s ADC 

USB bus (W = 8 MHz)



Channelizer code in Altera Cyclone FPGA



2 RF board slots

“Pentium” based SDR: Open-source GNU Radio Software - signal processing code on host computer in C+ + (including FSK, PSK, AM, ASK, NBFM. WBFM, 802.11)



IF -200 MHz (80 MHz receive)



100 MS/ s 14-bit dual (IQ) ADCs 400 MS/ s 16-bit dual (IQ) DACs



Gigabit Ethernet (W = 25 MHz)



Bigger FPGA w/ Multipliers (Spartan 3) with 1 MB high-speed on-board SRAM and high speed serial expansion interface



1 RF board slot

Selection of RF daughtercards (DC-5.9 GHz): DC-30 MHz, 50-870 MHz (Rx

• nly), 800-2400 MHz (Rx only), 400-500 MHz, 800-1000 MHz, 1150-1450

MHz, 1500-2100 MHz, 2300-2900 MHz, 2400-2500+ 4900-5840 MHz

WINLAB

WiNC2R Platform



Two 400 MSPS, 14-bit A/ D channels



Two 500 MSPS, 16-bit DAC channels



Xilinx Virtex5, SX95T FPGA



1GB DDR2 DRAM



4MB QDR-II SRAM



8-lane PCI Express Host Interface



ISM/ UNII RF (2.4/ 5 GHz)

WINC2R System



Xilinx Virtex-5 LX50 FPGA



10/ 100/ 1000 Ethernet PHY



16 MB Flash



64 MB DDR2 SDRAM



Cypress USB 2.0 controller



10-bit LVDS receive and transmit interfaces Dual RF front-end:



12-bit 64 MS/ s ADC



12-bit 64 MS/ s DAC



ISM/ UNII RF (2.4/ 5 GHz)

WINLAB

Virtual Flow Pipelining Architecture



Hardware engine in charge

• f processing flow control



Hardware and software modules atomic modules controlled by hw engine



Properties:



Low complexity (gates)



High performance



Simple to program



High utilization of resources



Programmable processing of phy and higher layer at speed – target rate 500 Mbps



Event driven processing model



Virtualization support for controlled sharing of processing resources across multiprotocol flows



Simple programming model



System level: combining the hw/ sw functions modules to satisfy the protocol, performance and time constraints.



Software defined function

WINLAB

Cognitive Experiments at Scale

Urban 300 meters 500 meters Suburban 20 meters ORBIT Radio Grid Office 30 meters

Radio Mapping Concept for ORBIT Emulator 400-node Radio Grid Facility at WINLAB Tech Center Programmable ORBIT radio node URSP CR board

Current ORBIT sandbox with GNU radio

 ORBIT radio grid testbed currently supports ~15/USRP and

USRP2 (GNU) radios, 100 low-cost spectrum sensors, WARP and WinC2R platforms

 Plan to reach ~64 cognitive radio nodes (Q1 2009)

But how do we do large scale experiments in realistic environments?

• GENI advanced technology demonstrator of cognitive radio networks
• Nation-wide (experimental) cognitive radio spectrum allocation