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Click to edit Master title style A 32nm SoC Platform Technology with 2 nd Generation High-k/Metal Gate Transistors Optimized for Ultra Low Power Click to edit Master text styles Second level Third level C.-H. Jan, M. Agostinelli, M.

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Chia-Hong Jan/ IEDM ‘09, Baltimore, MD Chia-Hong Jan/ IEDM ‘09, Baltimore, MD

  • Dec. 9th, ‘09
  • Dec. 9th, ‘09

C.-H. Jan, M. Agostinelli, M. Buehler, Z.-P. Chen, S.-J. Choi, G. Curello, H. Deshpande, S. Gannavaram, W. Hafez, U. Jalan, M. Kang, P. Kolar, K. Komeyli,

  • A. Lake, N. Lazo, S.-H. Lee, T. Leo, J. Lin, N. Lindert, S. Ma, L. McGill, C.

Meining, A. Paliwal, J. Park, K. Phoa, I. Post, N. Pradhan, M. Prince, A. Rahman,

  • J. Rizk, L. Rockford, G. Sacks, H. Tashiro, C. Tsai, P. Vandervoorn, J. Xu, L.

Yang, J.-Y. Yeh, J. Yip, K. Zhang, P. Bai

A 32nm SoC Platform Technology with 2nd Generation High-k/Metal Gate Transistors Optimized for Ultra Low Power Logic Technology Development Technology Manufacturing Group Intel Corporation

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Chia-Hong Jan/ IEDM ‘09, Baltimore, MD Chia-Hong Jan/ IEDM ‘09, Baltimore, MD

  • Dec. 9th, ‘09
  • Dec. 9th, ‘09

Outline

32 nm High-k/Metal Gate SoC Technology 32 nm SoC Transistor Architecture 32 nm SoC Interconnects and Passives 32 nm SoC Embedded Memory Summary

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Chia-Hong Jan/ IEDM ‘09, Baltimore, MD Chia-Hong Jan/ IEDM ‘09, Baltimore, MD

  • Dec. 9th, ‘09
  • Dec. 9th, ‘09

32 nm High-k/Metal Gate Transistor 32 nm High-k/Metal Gate Transistor

2nd gen high-k/metal gate Replacement Metal Gate (RMG) Flow 4th gen strained silicon 20% performance improvement over 45 nm high-k/metal gate In high volume manufacturing production of multi-core CPU products in multiple fabs

SiGe SiGe Me Meta tal G l Gate te High-k High-k Silicon Silicon

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Chia-Hong Jan/ IEDM ‘09, Baltimore, MD Chia-Hong Jan/ IEDM ‘09, Baltimore, MD

  • Dec. 9th, ‘09
  • Dec. 9th, ‘09

Replacement Metal Gate (RMG) SOC Flow Replacement Metal Gate (RMG) SOC Flow

Isolation (wells, Vt) Dielectric growth Poly-Si dep Poly-Si patterning Logic S/D extension- HP/LP Spacer dep/patterning S/D formation Poly-Si Gate Removal Metal Gate Replacement Contact Formation

SOC Flow CPU Flow

SoC process flow is derived from the 2nd generation CPU RMG (Replacement Metal Gate) flow

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Chia-Hong Jan/ IEDM ‘09, Baltimore, MD Chia-Hong Jan/ IEDM ‘09, Baltimore, MD

  • Dec. 9th, ‘09
  • Dec. 9th, ‘09

Outline

32 nm High-k/Metal Gate SoC Technology 32 nm SoC Transistor Architecture 32 nm SoC Interconnects and Passives 32 nm SoC Embedded Memory Summary

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Chia-Hong Jan/ IEDM ‘09, Baltimore, MD Chia-Hong Jan/ IEDM ‘09, Baltimore, MD

  • Dec. 9th, ‘09
  • Dec. 9th, ‘09

Triple Transistor Architecture Triple Transistor Architecture

Logic Transistor Low Power Transistor HV I/O Transistor

(HP or SP) (LP) (1.8 V/2.5 V or 3.3 V)

A low cost implementation with three types of transistors “co-exist” on the same die:

Logic (HP or SP) Logic (HP or SP) : for burst CPU performance Low Po Low Powe wer (LP) r (LP) : for always-on-always-connected application and long battery life HV I/O HV I/O: for high voltage I/O

Take advantage of the low gate leakage of high-k/metal gate to avoid the traditional expensive “triple gate” approach

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Chia-Hong Jan/ IEDM ‘09, Baltimore, MD Chia-Hong Jan/ IEDM ‘09, Baltimore, MD

  • Dec. 9th, ‘09
  • Dec. 9th, ‘09

Transistors Summary Transistors Summary

Transistor Type

Logic

(option for HP or SP)

Low Power HV I/O

(option for 1.8 or 3.3 V)

HP SP LP 1.8/2.5 V 3.3V

EOT (nm) 0.95 0.95 0.95 ~ 4 ~ 7 Vdd (V) .75/ 1 .75/ 1 0.75/1.2 1.5 /1.8 1.5 /3.3 Pitch (nm) 112.5 112.5 126

  • min. 338
  • min. 450

Lgate (nm) 30 34 46 >140 >300 NMOS Idsat (mA/um) 1.53 @ 1 V 1.12 @ 1 V 0.71 @ 1 V 0.68 @1.8 V 0.7 @3.3 V PMOS Idsat (mA/um) 1.23 @ 1V 0.87 @ 1 V 0.55 @ 1 V 0.59 @1.8 V .6 @3.3 V Ioff (nA/um) 100 1 0.03 0.1 <0.01

Tightest minimum gate pitch for 32/28 nm processes

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Chia-Hong Jan/ IEDM ‘09, Baltimore, MD Chia-Hong Jan/ IEDM ‘09, Baltimore, MD

  • Dec. 9th, ‘09
  • Dec. 9th, ‘09

Logic and LP Transistors Dynamic Range Logic and LP Transistors Dynamic Range

10,000 x Logic and LP transistors cover 4 orders of magnitude (10,000 x) of leakage power to support a wide dynamic range SoC applications

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Chia-Hong Jan/ IEDM ‘09, Baltimore, MD Chia-Hong Jan/ IEDM ‘09, Baltimore, MD

  • Dec. 9th, ‘09
  • Dec. 9th, ‘09

Logic Transistors Ion-Ioff (HP/SP) Logic Transistors Ion-Ioff (HP/SP)

Highest reported drives for 32/28 nm SoC process at tightest gate pitch (112 nm) -1.53 mA/um (N) / 1.12 mA/um (P) at 100nA/um 20-35% improvement over 45 nm high-k/MG logic transistors

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Chia-Hong Jan/ IEDM ‘09, Baltimore, MD Chia-Hong Jan/ IEDM ‘09, Baltimore, MD

  • Dec. 9th, ‘09
  • Dec. 9th, ‘09

Logic/LP Transistors Vt vs. L Logic/LP Transistors Vt vs. L

Short channel effect, DIBL, Vt roll-off are well controlled SP Vt < 400 mV, LP Vt ~ 500 mV

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Chia-Hong Jan/ IEDM ‘09, Baltimore, MD Chia-Hong Jan/ IEDM ‘09, Baltimore, MD

  • Dec. 9th, ‘09
  • Dec. 9th, ‘09

Logic Transistor I-V Characteristics Logic Transistor I-V Characteristics

Well controlled transistor I-V characteristics – HP and SP Sub-threshold slope ~ 100mV/decade (HP), < 90 mV/decade (SP) DIBL – SP: 90 mV (N)/100 mV (P); HP: 130 mV (N)/140 mV (P)

Sub-threshold Id-Vd Characteristics

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Chia-Hong Jan/ IEDM ‘09, Baltimore, MD Chia-Hong Jan/ IEDM ‘09, Baltimore, MD

  • Dec. 9th, ‘09
  • Dec. 9th, ‘09

Low Power Transistors Ion-Ioff (LP) Low Power Transistors Ion-Ioff (LP)

Highest reported drive currents at lowest standby leakage (30pA/um, 1000x lower than HP) AND Low active power (0.75 V) with good performance

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Chia-Hong Jan/ IEDM ‘09, Baltimore, MD Chia-Hong Jan/ IEDM ‘09, Baltimore, MD

  • Dec. 9th, ‘09
  • Dec. 9th, ‘09

Low Power Transistor I-V Characteristics Low Power Transistor I-V Characteristics

Well controlled transistor I-V characteristics - LP Sub-threshold slope ~ < 85 mV/decade DIBL - 70 mV (N)/100 mV (P)

Sub-threshold Id-Vd Characteristics

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Chia-Hong Jan/ IEDM ‘09, Baltimore, MD Chia-Hong Jan/ IEDM ‘09, Baltimore, MD

  • Dec. 9th, ‘09
  • Dec. 9th, ‘09

Low Power Transistors Total Leakage Low Power Low Power Transistors Total Leakage Total Leakage

I gate ( on) On State Off State I junction I off I gate ( off)

ILKG = ½ ( “ON” State Leakage ) + ½ (“OFF” State Leakage ) = ½ ( Igate (ON) ) + ½ (SF x Ioff + Ijunc + Igate (OFF) )

All leakage components – Ioff, Igate(on), Igate(off) and Ijunction need to be mitigated for low power transistor

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Chia-Hong Jan/ IEDM ‘09, Baltimore, MD Chia-Hong Jan/ IEDM ‘09, Baltimore, MD

  • Dec. 9th, ‘09
  • Dec. 9th, ‘09

High Voltage Transistors (1.8/2.5 V or 3.3 V) High Voltage Transistors (1.8/2.5 V or 3.3 V)

SiGe SiGe

Metal Gate High-k

2nd gen high-k/metal gate I/O Transistors 1.8/2.5 V or 3.3 V options High-k/Oxide composite gate stack Min gate length = 140 nm (1.8 V) Min gate length = 300 nm (3.3 V)

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Chia-Hong Jan/ IEDM ‘09, Baltimore, MD Chia-Hong Jan/ IEDM ‘09, Baltimore, MD

  • Dec. 9th, ‘09
  • Dec. 9th, ‘09

Reliability – Logic and High Voltage Reliability – Logic and High Voltage

Robust NMOS and PMOS high k + metal gate logic and I/O transistors TDDB

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Chia-Hong Jan/ IEDM ‘09, Baltimore, MD Chia-Hong Jan/ IEDM ‘09, Baltimore, MD

  • Dec. 9th, ‘09
  • Dec. 9th, ‘09

Outline

32 nm High-k/Metal Gate SoC Technology 32 nm SoC Transistor Architecture 32 nm SoC Interconnects and Passives 32 nm SoC Embedded Memory Summary

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Chia-Hong Jan/ IEDM ‘09, Baltimore, MD Chia-Hong Jan/ IEDM ‘09, Baltimore, MD

  • Dec. 9th, ‘09
  • Dec. 9th, ‘09

32 nm SoC Interconnects

SOC interconnect system optimized for density and flexibility CPU

1 x pitch (2-5 layers) 1.5 x pitch (2-3 layers) 3 x pitch 4 x pitch 1 x pitch 1.5 x pitch 3 x pitch 5 x pitch 4 x pitch 2 x pitch 112 nm 169 nm 338 nm 450 nm 112 nm 169 nm 338 nm 450 nm 225 nm 504 nm Pitch Pitch

SOC

Optimized for RC Optimized for Density

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Chia-Hong Jan/ IEDM ‘09, Baltimore, MD Chia-Hong Jan/ IEDM ‘09, Baltimore, MD

  • Dec. 9th, ‘09
  • Dec. 9th, ‘09

32 nm SoC Interconnects – Thick Top Metal

Thick top metal for power delivery and I/O routing

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Chia-Hong Jan/ IEDM ‘09, Baltimore, MD Chia-Hong Jan/ IEDM ‘09, Baltimore, MD

  • Dec. 9th, ‘09
  • Dec. 9th, ‘09

1 10 100 0.1 1 10 100 Inductor Quality Factor Freq (GHz)

32 nm SoC High Q Inductors

M9 Inductor M8 Inductor

Quality Factor Comparison of M9 and M8 Inductors

Inductors Thick top metal ideal for high Q inductors (Q > 20)

6 nH inductor for 2.4 GHz Wi-Fi LNA 1 nH Inductor for VCO

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Chia-Hong Jan/ IEDM ‘09, Baltimore, MD Chia-Hong Jan/ IEDM ‘09, Baltimore, MD

  • Dec. 9th, ‘09
  • Dec. 9th, ‘09

32 nm SoC Capacitors and Resistors

10 10 100 100 10 1000 0.1 10

MFC Quality Factor Frequency ( GHz )

+15%

  • 15%
  • 10%

Resistance

  • 10%

Metal Finger Capacitor Q of Metal Finger Capacitor Precision Resistor Linear Resistor

Capacitors Resistors Rich high quality factor and high precision passives

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Chia-Hong Jan/ IEDM ‘09, Baltimore, MD Chia-Hong Jan/ IEDM ‘09, Baltimore, MD

  • Dec. 9th, ‘09
  • Dec. 9th, ‘09

Deep Nwell for Substrate Noise Isolation Deep Deep Nwell Nwell for Substrate Noise Isolation for Substrate Noise Isolation

50 dB substrate noise reduction measured on deep Nwell for noise sensitive analog circuits – ADC (Analog-Digital Converter), DAC (Digital-Analog Converter), PA (Power Amplifier) and VCO

Deep Nwell

N + N + N + Gate N + N +

P-well

N + N + Gate N +

Noise Hi k

Deep Nwell Architecture

High Freq Digital Circuits “Quiet” Analog Circuits

Substrate Noise Measurement

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Chia-Hong Jan/ IEDM ‘09, Baltimore, MD Chia-Hong Jan/ IEDM ‘09, Baltimore, MD

  • Dec. 9th, ‘09
  • Dec. 9th, ‘09

1/f Flicker Noise 1/f Flicker Noise

65 (poly/ox) /45/32 nm (high k/metal gate) 1/f flicker noise trend shows healthy Si/dielectric interfaces and no degradation from high-k/metal gate processing, critical for analog circuits

1E-14 1E-13 1E-12 1E-11 1E-10 1E-09

10 100 1000 10000 100000

Svg ( V2/um ) Frequency ( Hz )

NMOS 1/f Flicker Noise

65 nm Ox/Ply Vds=1.1V 45 nm Hi k/MG Vds=1.0V 32 nm Hi k/MG Vds=0.9V

1E-14 1E-13 1E-12 1E-11 1E-10 1E-09

10 100 1000 10000 100000

Svg ( V2/um ) Frequency ( Hz )

PMOS 1/f Flicker Noise

65 nm Ox/Ply Vds=1.1V 45 nm Hi k/MG Vds=1.0V 32 nm Hi k/MG Vds=0.9V

<Id

2>

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Chia-Hong Jan/ IEDM ‘09, Baltimore, MD Chia-Hong Jan/ IEDM ‘09, Baltimore, MD

  • Dec. 9th, ‘09
  • Dec. 9th, ‘09

Outline

32 nm High-k/Metal Gate SoC Technology 32 nm SoC Transistor Architecture 32 nm SoC Interconnects and Passives 32 nm SoC Embedded Memory Summary

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Chia-Hong Jan/ IEDM ‘09, Baltimore, MD Chia-Hong Jan/ IEDM ‘09, Baltimore, MD

  • Dec. 9th, ‘09
  • Dec. 9th, ‘09

Multiple SRAM bit cells offered for high speed, low voltage and high density SoC applications. Highest reported array density

6T SRAM Bit Cells 6T SRAM Bit Cells

0.199 um2 High Speed Low Voltage High Density 0.148 um2 4.62 Mb/mm2 0.171 um2 4.10 Mb/mm2 3.66 Mb/mm2

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Chia-Hong Jan/ IEDM ‘09, Baltimore, MD Chia-Hong Jan/ IEDM ‘09, Baltimore, MD

  • Dec. 9th, ‘09
  • Dec. 9th, ‘09

All bit cells are capable of supporting high performance needs. 32 nm LP can operate up to 2 GHz, 2x faster than 65 nm LP

6T SRAM Performance – Shmoo Plot 6T SRAM Performance – Shmoo Plot

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Chia-Hong Jan/ IEDM ‘09, Baltimore, MD Chia-Hong Jan/ IEDM ‘09, Baltimore, MD

  • Dec. 9th, ‘09
  • Dec. 9th, ‘09

Low bit cell leakages (< 20 pA/cells) at low retention Vccmin

6T SRAM Vccmin and Leakages 6T SRAM Vccmin and Leakages

0.171 um 2 Die photo of 6T SRAM test chip with 291 Mbits

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Chia-Hong Jan/ IEDM ‘09, Baltimore, MD Chia-Hong Jan/ IEDM ‘09, Baltimore, MD

  • Dec. 9th, ‘09
  • Dec. 9th, ‘09

32 nm Yield Trend – CPU and SoC 32 nm Yield Trend – CPU and SoC

90 nm 65 nm 45 nm 32 nm

2002 2003 2004 2005 2006 2007 2008 2009 2010

Defect Density

(log scale)

Higher Yield

SoC process has the same low defect density as CPU process CPU SoC

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Chia-Hong Jan/ IEDM ‘09, Baltimore, MD Chia-Hong Jan/ IEDM ‘09, Baltimore, MD

  • Dec. 9th, ‘09
  • Dec. 9th, ‘09

Outline

32 nm High-k/Metal Gate SoC Technology 32 nm SoC Transistor Architecture 32 nm SoC Interconnects and Passives 32 nm SoC Embedded Memory Summary

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Chia-Hong Jan/ IEDM ‘09, Baltimore, MD Chia-Hong Jan/ IEDM ‘09, Baltimore, MD

  • Dec. 9th, ‘09
  • Dec. 9th, ‘09

Summary Summary Summary

  • 32 nm high-k/metal gate technology has been optimized for

high performance/low power System-On-Chip (SOC) platform

  • A new triple transistor architecture provides record drive

currents and low leakages spanning 4 orders of magnitude

  • f leakage
  • Tightest reported gate pitch and highest reported SRAM

array density of any 32nm or 28nm technology

  • Other SOC device elements (resistors, inductors, capacitors,

diodes, and varactors) all exhibit well controlled performance and reliability

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Chia-Hong Jan/ IEDM ‘09, Baltimore, MD Chia-Hong Jan/ IEDM ‘09, Baltimore, MD

  • Dec. 9th, ‘09
  • Dec. 9th, ‘09

Acknowledgements

The authors gratefully acknowledge the many people in the following organizations at Intel who contributed to this work: Logic Technology Development Quality and Reliability Engineering Technology CAD Components Research Assembly & Test Technology Development Intel Labs/RIR

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Chia-Hong Jan/ IEDM ‘09, Baltimore, MD Chia-Hong Jan/ IEDM ‘09, Baltimore, MD

  • Dec. 9th, ‘09
  • Dec. 9th, ‘09

For further information on Intel's silicon technology, please visit our Technology & Research page at www.intel.com/technology