Chapter 4: Retiming Keshab K. Parhi Ret iming : Moving around - - PowerPoint PPT Presentation

Chapter 4: Retiming

Keshab K. Parhi

• Chap. 4

2

Ret iming : Moving around exist ing delays

• Does not alt er t he lat ency of t he syst em
• Reduces t he crit ical pat h of t he syst em
• Node Ret iming

5D D 3D 3D 2D

• Cut set Ret iming

A E D B C F 2D D D D D D

• Chap. 4

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Retiming

• Generalization of Pipelining
• Pipelining is Equivalent to Introducing

Many delays at the Input followed by Retiming

• Chap. 4

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• Ret iming Formulat ion

r(U) r (V) Source node Dest inat ion node U V ω Ret iming U V ω’ ω’ = ω + r(V) - r(U)

• Propert ies of ret iming

–The weight of t he ret imed pat h p = V0 --> V1 --> … ..Vk is given by ωr(p)= ω(p) + r (Vk) - r(V0) –Ret iming does not change t he number of delays in a cycle. –Ret iming does not alt er t he it erat ion bound in a DFG as t he number of delays in a cycle does not change –Adding t he const ant value j t o t he ret iming value of each node does not alt er t he number of delays in t he edges of t he ret imed graph.

• Ret iming is done t o meet t he f ollowing

– Clock period minimizat ion – Regist er minimizat ion

• Chap. 4

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• Ret iming f or clock period minimizat ion

– Feasibilit y const raint ω’(U,V) ≥ 0 ⇒ causalit y of t he syst em ⇒ ω(U,V) ≥ r(U) - r(V) (one inequalit y per edge) – Crit ical Pat h const raint r(U) - r(V) ≤ W(U,V) - 1 f or all vert ices U and V in t he graph such t hat D(U,V) > c where c = t arget clock period. The t wo quant it ies W(U,V) and D(U,V) are given as: W(U,V) = min{w(p) : U→V} D(U,V) = max{t (p) : U→V and w(p) = W(U,V) A B F C D E G (1) (1) (1) (1) (1) (1) (2) D D 2D

W(A,E) = 1 & D(A,E) = 5

• Chap. 4

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• Algorit hm t o comput e W(U,V) and D(U,V):
• Let M = t maxn, where t max is t he maximum comput at ion t ime of

t he nodes in G and n is t he # of nodes in G.

• Form a new graph G’ which is t he same as G except t he edge

weight s are replaced by w’(e) = Mw(e) – t (u) f or all edges UV.

• Solve f or all pair short est pat h problem on G’ by using Floyd

Warshall algorit hm. Let S’UV be t he short est pat h f orm U V.

• I f U ≠ V, t hen W(U,V) = S’UV/ M and D(U,V) = MW(U,V) -

S’UV + t (V). I f U = V, t hen W(U,V) = 0 and D(U,V) = t (U).

• Using W(U,V) and D(U,V) t he f easibilit y and crit ical pat h

const raint s are f ormulat ed t o give cert ain inequalit ies. The inequalit ies are solved using const raint graphs and if a f easible solut ion is obt ained t hen t he circuit can be clocked wit h a period ‘c’.

• Chap. 4

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• Solving a syst em of inequalit ies : Given M inequalit ies in N

variables where each inequalit y is of t he f orm r i – r j ≤ k f or int eger values of k. Draw a const raint graph Draw t he node i f or each of t he N variables r i, I = 1, 2, … , N. Draw t he node N+1. For each inequalit y r i – r j ≤ k , draw t he edge j i of lengt h k. For each node i, i = 1, 2, … , n, draw t he edge N+1 i f rom t he node N+1 t o node I wit h lengt h 0. Solve using a short est pat h algorit hm. The syst em of inequalit ies have a solut ion if f t he const raint graph cont ains no negat ive cycles. I f a solut ion exist s, one solut ion is where r i is t he minimum lengt h pat h f rom t he node N+1 t o node i.

• Chap. 4

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• K-slow t ransf ormat ion

– Replace each D by kD A B

D (1) (1) Clock A0→ B0 1 A1→ B1 2 A2→ B2

Af t er 2-slow t ransf ormat ion A B

2D (1) (1)

Titer= 2ut Clock A0→B0 1 2 A1→B1 3 4 A2→B2 Tclk= 2ut Titer= 2×2ut=4ut *I nput new samples every alt ernat e cycles. *null operat ions account f or odd clock cycles. *Hardware ut ilized only 50% t ime

• Chap. 4

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• Ret iming 2-slow graph

A B D D Tclk = 1ut Tit er = 2×1=2ut *Hardware Ut ilizat ion = 50 % *Hardware can be f ully ut ilized if t wo independent operat ions are available.

• Chap. 4

10 A 100 stage Lattice Filter with critical path 2 multiplications and 101 additions

The 2-slow version

2-Slow Lattice Filter (Fig. 4.7)

• Chap. 4

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A ret imed version of t he 2 slow circuit wit h crit ical pat h of 2 mult iplicat ions and 2 addit ions I f Tm = 2 u.t . and Ta = 1 u.t ., t hen Tclk = 6 u.t ., Tit er = 2X6 = 12 u.t . I n Original Lat t ice Filt er, T it er = 105 u.t . I t erat ion Period Bound = 7 u.t .

• Chap. 4

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Other Applications of Retiming

• Retiming for Register Minimization

(Section 4.4.3)

• Retiming for Folding (Chapter 6)
• Retiming for Power Reduction (Chap. 17)
• Retiming for Logic Synthesis (Beyond

Scope of This Class)

• Multi-Rate/Multi-Dimensional Retiming

(Denk/Parhi, Trans. VLSI, Dec. 98, Jun.99)