CS184a: Computer Architecture (Structures and Organization) Day15: - - PDF document

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CS184a: Computer Architecture (Structures and Organization) Day15: - - PDF document

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CS184a: Computer Architecture (Structures and Organization) Day15: November 13, 2000 Retiming Caltech CS184a Fall2000 -- DeHon 1 Previously Reviewed Pipelining basic assignments on Saw spatial designs efficient when reuse

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Caltech CS184a Fall2000 -- DeHon 1

CS184a: Computer Architecture (Structures and Organization)

Day15: November 13, 2000 Retiming

Caltech CS184a Fall2000 -- DeHon 2

Previously

  • Reviewed Pipelining

– basic assignments on

  • Saw spatial designs efficient

– when reuse logic at maximum frequency

  • Interconnect dominant delay

– and dominant area – heavy call to reuse to use efficiently

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Today

  • Systematic transformation for retiming

– maximize throughput – preserve semantics – “justify” mandatory registers in design

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Motivation

  • FPGAs (spatial computing)

– run efficiently when all resources reused rapidly

  • cycle time minimized
  • “Everything in the right place at the right

time.”

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Task

  • Move registers to:

– preserve semantics – Minimize path length between registers – (make path length 1 for maximum throughput

  • r reuse)

– Maximize reuse rate – …while minimizing number of registers required

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Simple Example

Path Length (L) = 4 Can we do better?

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Legal Register Moves

  • Retiming Lag/Lead

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Canonical Graph Representation

Separate arch for each path Weight edges by number of registers (weight nodes by delay through node)

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Critical Path Length

Critical Path: Length of longest path of zero weight nodes Compute in O(|E|) time by levelizing network: Topological sort, push path lengths forward until find register.

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Retiming Lag/Lead

Retiming: Assign a lag to every vertex

weight(e′) = weight(e) + lag(head(e))-lag(tail(e))

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Valid Retiming

  • Retiming is valid as long as:

– ∀e in graph

  • weight(e′) = weight(e) + lag(head(e))-lag(tail(e)) ≥ 0
  • Assuming original circuit was a valid

synchronous circuit, this guarantees:

– non-negative register weights on all edges

  • no travel backward in time :-)

– all cycles have strictly positive register counts – propagation delay on each vertex is non- negative (assumed 1 for today)

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Retiming Task

  • Move registers ≡ assign lags to nodes

– lags define all locally legal moves

  • Preserving non-negative edge weights

– (previous slide) – guarantees collection of lags remains consistent globally

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Retiming Transformation

  • N.B. -- unchanged by retiming

– number of registers around a cycle – delay along a cycle

  • Cycle of length P must have

– at least P/c registers on it – to be retimeable to cycle c

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Optimal Retiming

  • There is a retiming of

– graph G – w/ clock cycle c – iff G-1/c has no cycles with negative edge weights

  • G-α ≡ subtract α from each edge weight
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G-1/c

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Compute Retiming

  • Lag(v) = shortest path to I/O in G-1/c
  • Compute shortest paths in O(|V||E|)

– Bellman-Ford – also use to detect negative weight cycles when c too small

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Bellman Ford

  • For I←0 to N

– ui ←∞ (except ui=0 for IO)

  • For k←0 to N

– for ei,j∈E

  • ui ←min(ui ,uj+w(ei,j))
  • for ei,j∈E
  • if ui >uj+w(ei,j)

– cycles detected

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Apply to Example

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Apply: Find Lags

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Apply: Lags

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Apply: Move Registers

weight(e′) = weight(e) + lag(head(e))-lag(tail(e))

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Apply: Retimed

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Apply: Retimed Design

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Revise Example (fanout delay)

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Revised: Graph

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Revised: Graph

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Revised: C=1?

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Revised: C=2?

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Revised: Lag

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Revised: Lag

Take ceiling to convert to integer lags:

  • 1
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Revised: Apply Lag

  • 1

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Revised: Apply Lag

1 1 1 1 1 1 1 1

  • 1
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Revised: Retimed

1 1 1 1 1 1 1 1

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Pipelining

  • Can use this retiming to pipeline
  • Assume have enough (infinite supply) of

registers at edge of circuit

  • Retime them into circuit
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C>1 ==> Pipeline

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Add Registers

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Pipeline Retiming: Lag

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Pipelined Retimed

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Real Cycle

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Real Cycle

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Cycle C=1?

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Cycle C=2?

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Cycle: C-slow

Cycle=c ⇒ C-slow network has Cycle=1

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2-slow Cycle ⇒ C=1

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2-Slow Lags

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2-Slow Retime

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Retimed 2-Slow Cycle

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C-Slow applicable?

  • Available parallelism

– solve C identical, independent problems

  • e.g. process packets (blocks) separately
  • e.g. independent regions in images
  • Commutative operators

– e.g. max example

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Max Example

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Max Example

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Monday Lecture Stopped Here

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HSRA Retiming

  • HSRA

– adds mandatory pipelining to interconnect

  • One additional twist

– long, pipelined interconnect

  • ⇒ need more than one

register on paths

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Accommodating HSRA Interconnect Delays

  • Add buffers to LUT→LUT path to match

interconnect register requirements

  • Retime to C=1 as before
  • Buffer chains force enough registers to

cover interconnect delays

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Accommodating HSRA Interconnect Delays

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Big Ideas [MSB Ideas]

  • Retiming important to

– minimize cycles – efficiently utilize spatial architectures

  • Optimally solvable in O(|V||E|) time
  • Tells us

– pipelining required – C-slow – where to move registers