Sequential Networks: Timing and Retiming CSE 140: Components and - PowerPoint PPT Presentation

Lecture 10: Sequential Networks: Timing and Retiming CSE 140: Components and Design Techniques for Digital Systems Diba Mirza Dept. of Computer Science and Engineering University of California, San Diego 1

So far …. Combinational CLK Logic-level analysis

This lecture … Combinational CLK • Our seemingly logically correct design can go wrong • How can we design a circuit that works under real constraints?

Timing Constraints of flip flops • The input to a flip-flop should be stable for a period of time around the rising edge of the clock Q D Q’ CLK 4

Input Constraints: Set up and hold time CLK Q D Q’ D t setup t hold I. Setup time: t setup t a Time before the clock edge that data must be stable (i.e. not change) II. Hold time: t hold Time after the clock edge that data must be stable Aperture time: t a Time around clock edge that data must be stable ( t a = t setup + t hold ) 5

PIQ: Which of the following signals can cause a setup-time violation for this flip flop? Q(t) Q D(t) D A. The input signal D(t) Q’ B. The output signal Q(t) C. Both A and B CLK D. None of the above 6

Output characteristics of flip flops Q D Q’ I. Minimum delay of Q Time after the clock edge for which Q is sure to not change II. Maximum delay of Q Time after the clock edge following which Q is sure to have stabilized 7

Output characteristics of flip flops CLK Q D Q Q’ t ccq t pcq I. Min delay of flip flop, also called Contamination delay or min CLK to Q delay: t ccq Time after clock edge that Q might be unstable (i.e., start changing) II. Max delay of flip flop, also called Propagation delay or maximum CLK to Q delay: t pcq Time after clock edge that the output Q is guaranteed to be stable (i.e., to stop changing) 8

Fact 1: Once a flip flop has been ‘built’ we are stuck with its timing characteristics: t setup , t hold, t ccq, t pcq Q1 D2 D1 R1 R2 Combinational CLK CLK Now let’s look at the timing characteristics of the combinational part 9

Combinational Logic Timing I. Min delay of a gate, also called Contamination delay: t cd Minimum time from when an input changes until the output starts to change II. Max delay of a gate, also called Propagation delay: t pd Maximum time from when an input changes until the output is guaranteed to reach its final value (i.e., stop changing) 10

Combinational Logic: Output timing constraints A B Y C D PI Q: Which path in the above circuit determines the contamination delay of the circuit (assuming the delay of all the gates is the same)? A. Green path B. Red path C. Both D. Neither 11

Combinational Logic: Output timing constraints A B Y C D PI Q: Which path in the above circuit determines the propagation delay of the circuit (assuming the delay of all the gates is the same)? A. Green path B. Red path C. Both D. Neither 12

Timing Issues • If the input to a flip flop doesn’t stabilize in time BEFORE the rising edge of the clock we have a setup time violation CLK CLK Q1 D2 C L R1 R2 (a) T c CLK Q1 D2 (b) 13

Why would the input (D2) not stabilize in time? • D2 changes because of Q1 • Flip flop has maximum delay, Q1 stabilizes after this maximum delay from the clock edge • The combinational circuit has a maximum delay, so even after Q1 has stabilized, D2 takes a while to stabilize • If D2 doesn’t stabilize on time we have a setup violation CLK CLK Q1 D2 C L R1 R2 (a) T c CLK Q1 D2 14 (b)

Timing Issues • If the input to a flip flop changes too quickly AFTER the rising edge of the clock we have a hold time violation CLK CLK Q1 D2 C L R1 R2 (a) T c CLK Q1 D2 (b) 15

Why would the input (D2) change too quickly? • D2 changes because of Q1 • Flip flop has minimum delay, Q1 will start changing only after this minimum delay • The combinational circuit has a minimum delay, after which the output of CL (D2) will start reacting to a changing input. • If D2 starts changing too quickly we have a hold time violation CLK CLK Q1 D2 C L R1 R2 (a) T c CLK Q1 D2 16 (b)

Why timing in Sequential Circuits can go wrong? Which of the following violations would occur if the min delay of R1 was 0 and the combinational circuit was just a wire? A. Hold time violation for R2 CLK CLK B. Setup violation for R2 Q1 D2 C. Hold time violation for R1 C L D. Setup violation for R1 R1 R2 (a) E. None of the above T c CLK Q1 D2 (b) 17

Meeting the hold time constraint • Input to a flip-flop comes from the output of another flip flop, through a combinational circuit • The flipflop and combinational circuit have a min and max delay CLK CLK Q1 D2 C L R1 R2 (a) To meet the hold time constraint: T c t hold < min delay(flipflop) + min delay(combinational) CLK Q1 D2 (b) 18

Why timing in Sequential Circuits can go wrong? • Input to a flip-flop comes from the output of another flip flop, through a combinational circuit • The flipflop and combinational circuit have a min and max delay CLK CLK Q1 D2 C L Which of the following violations would occur if the max delay of R1 was 0 and the R1 R2 (a) max delay of the combinational circuit T c was equal to the clock period CLK A. Hold time violation for R2 B. Setup violation for R2 Q1 C. Hold time violation for R1 D. Setup violation for R1 D2 E. None of the above (b) 19

Meeting the setup time constraint • Input to a flip-flop comes from the output of another flip flop, through a combinational circuit • The flipflop and combinational circuit have a min and max delay CLK CLK Q1 D2 C L R1 R2 (a) To meet the setup time constraint: T c T c ≥ max delay(flipflop) + max delay(combinational)+ t setup CLK Q1 D2 (b) 20

Formalizing the hold time constraint in Sequential Circuits CLK CLK Q1 D2 C To meet the hold time constraint: L R1 R2 t hold < min delay(flipflop) + min delay(combinational) CLK t hold < t ccq + t cd Q1 D2 t ccq t cd t hold 21

Formalizing the setup time constraints in Sequential Circuits To meet the setup time constraint: CLK CLK Q1 D2 C L T c ≥ max delay(flipflop) + R1 R2 max delay(combinational)+ t setup T c T c ≥ t pcq + t pd + t setup CLK Q1 D2 t pcq t pd t setup 22

Timing Analysis Timing Characteristics t ccq = 30 ps t pcq = 50 ps CLK CLK A t setup = 60 ps B t hold = 70 ps X' X C t pd = 35 ps Y' Y D t cd = 25 ps t pd (CL)= t cd (CL)= Setup time constraint: Hold time constraint: T c ≥ t ccq + t cd (CL)> t hold ? f c = 1/ T c = 23

Timing Analysis Timing Characteristics t ccq = 30 ps t pcq = 50 ps CLK CLK A t setup = 60 ps B t hold = 70 ps X' X C t pd = 35 ps Y' Y D t cd = 25 ps t pd = 3 x 35 ps = 105 ps t cd = 25 ps Setup time constraint: Hold time constraint: T c ≥ (50 + 105 + 60) ps = 215 ps t ccq + t cd > t hold ? f c = 1/ T c = 4.65 GHz (30 + 25) ps > 70 ps ? No! 24

Fixing Hold Time Violation Timing Characteristics Add buffers to the short paths: t ccq = 30 ps t pcq = 50 ps CLK CLK t setup = 60 ps A t hold = 70 ps B X' X C t pd = 35 ps Y' Y D t cd = 25 ps t pd = t cd = Setup time constraint: Hold time constraint: T c ≥ t ccq + t cd > t hold ? f c = 25

Fixing Hold Time Violation Add buffers to the short paths: Timing Characteristics t ccq = 30 ps t pcq = 50 ps CLK CLK t setup = 60 ps A t hold = 70 ps B X' X C t pd = 35 ps Y' Y D t cd = 25 ps t pd = 3 x 35 ps = 105 ps t cd = 2 x 25 ps = 50 ps Setup time constraint: Hold time constraint: T c ≥ (50 + 105 + 60) ps = 215 ps t ccq + t cd > t hold ? f c = 1/ T c = 4.65 GHz (30 + 50) ps > 70 ps ? Yes! 26

Midterm review • SR latch 27

SR latch timing diagrams 28

What do inputs A & B do? 29

FSM design example • Design an overlapping finite string pattern recognizer – output is 1 whenever the input sequences 101 and 011 are observed 30

Sequential circuit design Next state Output Present State W=0 W=1 Z 00 0 10 11 01 00 00 0 10 10 00 0 11 10 00 1 31

FSM Design Example • Write the state table and implement the following state machine: 32