Challenges and Opportunities April 12, 2010 Boris Murmann - - PowerPoint PPT Presentation

Mixed-Signal Group Murmann Mixed-Signal Group Murmann

Digitizing the Analog World: Challenges and Opportunities

April 12, 2010 Boris Murmann murmann@stanford.edu

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Murmann Mixed-Signal Group

Research Overview

Signal Processing A/D D/A Signal Conditioning Signal Conditioning

Transducers, Antennas, Cables, ...

Digital enhancement algorithms High-performance and low- power A/D and D/A converters Sensor interfaces MEMS

Spin-Valve

Biomolecule detection Neural prosthetics Medical ultrasound

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Research Examples

 High-performance A/D converters  Neural prosthetics  MEMS accelerometers  Large area electronics

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Digitally Assisted A/D Converters

Signal Processing A/D D/A Signal Conditioning Signal Conditioning

Analog Media and Transducers

Digital Analog

CLK

Additional digital processing for performance enhancement

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ADC for a “Digital” Serial Link



No analog error accumulation and better scalability



Need efficient high-speed ADC, typically > 10GS/s

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ADC1 ADC2 ADCN

text

X(t) Y[n]

Time-Interleaving

1 2 N

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 Popular way to increase ADC throuhgput

ADC1 ADC2 ADCN X(t) Y[n]

G1 Voff_2 G2 Voff_N GN Voff_1 text

Imperfections

1 2 N

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 Mismatches result in signal distortion



Gain



Offset



Timing Skew

Our Focus: Timing Skew

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1 2



(2-channel example)

Digital Backend ADC1 ADC2 ADCN X(t) ADCCal Y[n] Clock

Skew Calibration Using Extra ADC



Statistics-based skew measurement in digital backend



Correction through analog adjustments

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1 2 N Cal 1 2

Digitally adjustable delay cells

N

Timing of Auxiliary ADC Phase

1 2 N Cal 1 2 N Cal 1 2

Digital Backend ADC1 ADC2 ADCN X(t) ADCCal Y[n] Clock

11 1 2 N Cal

Calibration Scheme



For each channel, adjust delay cells until correlation between calibration ADC output and each slice are maximized



ADCCal can be 1-bit and “slow”

12 ADC1 ADC2 ADCN X(t) ADCCal Y[n] Clock Max

1 2 N Cal 1 2

 R()

 Removed pre-publication experimental data…

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MEMS Accelerometer

 Capacitance change ~10 fF/g  Desired resolution ~10 mg for airbags and ESP



Must resolve capacitance changes of ~100 aF

 Problem: Drift in parasitic bondwire capacitance CMOS

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Sigma-Delta Interface

IN

a m k bs ms  

2

1 x x C   C

V C

A  V S/H Lead Compensator

Dig

V

mech

F Force- Balancing Decimator

Out

V

• M. Lemkin and B. E. Boser, “A three-axis micromachined accelerometer with a CMOS

position-sense interface and digital offset-trim electronics,“ IEEE J. Solid-State Circuits,

• vol. 34, pp. 456-468, April 1999.

Mechanical

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Offset

IN

a m k bs ms  

2

1 x x C   C

V C

A  V S/H Lead Compensator

mech

F Force- Balancing

Offset

C

Offset due to bond wire deformation

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Linear Feedback System with Two Inputs

1 2

1 1 y x x f af    

a y x1 f + _ b + x2

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Spring Constant Modulation

 The output due to Coff can be modulated to higher

frequencies by modulating the spring constant k

1

Out mech Off

k k V F C C FB FB x        

IN

a m k bs ms  

2

1 x x C   C

V C

A  V S/H Lead Compensator

mech

F Force- Balancing

Offset

C

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Spring softening effect

Acceleration Spring Acceleration Spring _ _ + _ _ + _ _ + _ _ + Electrostatic

 Can be used to modulate spring constant (k)

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Modulation through Multiplexed Feedback

Time-Multiplexed IN

a m k bs ms  

2

1 x x C   C

V C

A  V S/H PULSE

Out

V

mech

F Electrostatic Force Decimator x km 

k

f

Int Com

T T

MOD MOD Force-Balancing

Force-Balancing

Output Spectrum with 1-Tone Modulation

21 10

• 6

10

• 5

10

• 4

10

• 3

10

• 2

10

• 1
• 160
• 140
• 120
• 100
• 80
• 60
• 40
• 20

Frequency (MHz) Power/frequency (dB/Hz) 10

• 6

10

• 5

10

• 4

10

• 3

10

• 2

10

• 1
• 160
• 140
• 120
• 100
• 80
• 60
• 40
• 20

Frequency (MHz) Power/frequency (dB/Hz) 10

• 6

10

• 5

10

• 4

10

• 3

10

• 2

10

• 1
• 160
• 140
• 120
• 100
• 80
• 60
• 40
• 20

Frequency (MHz) Power/frequency (dB/Hz)

• 89 dB
• 32 dB
• 46 dB

DC Acceleration Offset Capacitance 0 fF 10 fF 50 fF 9.1 m/s^2 9.1 m/s^2 9.1 m/s^2

10 10

2

10

4

10

6

• 140
• 120
• 100
• 80
• 60
• 40
• 20

Frequency [Hz] Output Spectrum [dB] Modulating spring-constant with a pseudo-random sequence

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Pseudo-Random Modulation

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Parameter Convergence

0.5 1 1.5 2

• 0.2

0.2 0.4 0.6 0.8 1 1.2

Time [Sec] Feedback signal [x10 -15] Closed-loop system - Feeding back capacitance

Coff=0fF Coff=0.01fF Coff=0.1fF Coff=1fF

Chip Design in Progress

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CMOS MEMS C to V Integrator Compensator Quantizer Electrostatic Feedback State- Machine VOut Clk VRef Gnd FPGA Decimator Correlator DOut k-modulation Scan In/Out

Neural Prosthetics

 Cortical motor prosthetics



Neurons in the motor cortical areas of the brain encode information about intended movement

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Courtesy K.V. Shenoy Courtesy L.R. Hochberg Nature Magazine June ‘06

Neural Signal Acquisition

 Electrode signals consist of multiple sources



DC Offset, about 15mV from electrode/tissue interface



Local field potential (LFP), ≤3mV peak, 10Hz to 100Hz



Spikes from nearby neurons, 35μV – 1mV peak, 500Hz to 5kHz

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Courtesy C.L. Klaver Courtesy M. Sahani

Specs

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Spikes Local Field Potential

Gain

600 V/V 200 V/V

Lower Cutoff

300Hz 1Hz

Upper Cutoff

10kHz 1kHz

Input Referred Noise (total from sampling node)

2.0µVrms 1.0µVrms in 10-100Hz

Total Power (96x Array)

3mW 100µW

 Separate the fast and slow signal acquisition for DR



Custom front end design for each path

Spike Path Front-End

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Input Stage SC Bandpass Filter SAR ADC Input Cap Output Buffers

Sampling Phase

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

Integrate signal current on CB and sample



High-pass for DC block using Cac and Rbig (off- resistance)



A1 contains a pole that helps minimize noise folding

A1 Implementation Details

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ITAIL I<< ITAIL Voutp Voutm VB1 VB2 M1a M1b

Flicker noise reduction Anti-alias for thermal noise from M1a,b

Static Power

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Two-Channel Interface Pixel

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Frontend SAR ADC

Die Photo (96 channels, 5mm x 5mm)

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The Future?

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Organic Semiconductors

 Mechanically flexible  Suitable for solution processing



Cover large areas at low cost



Make disposable devices

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Orbital Energy Levels of Pentacene

22 carbon atoms 22 π orbitals LUMO

~3 eV

HOMO

~5 eV

Unoccupied Occupied

(highest occupied molecular orbital) (lowest unoccupied molecular orbital)

[Slide by Hagen Klauk]

P-Channel Transistor

Au Au

HOMO

~5 eV ~3 eV

LUMO

[Slide by Hagen Klauk]

Active Matrix OLED Displays

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http://www.youtube.com/watch?v=f8S8tbQMp2k&NR=1

Jellyfish Autonomous Node

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http://muri.mse.vt.edu/

Jellyfish Bell Prototype (Virginia Tech)

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A bio-inspired shape memory alloy composite (BISMAC) actuator A .A .Villanueva, et al., 2010 Smart Mater. Struct. 19 025013 (17pp)

Want to Make Plastic ADCs !

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6-bit A/D Converter Prototype

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• W. Xiong, U. Zschieschang, H. Klauk, and B.

Murmann, “A 3V, 6b Successive Approximation ADC using Complementary Organic Thin-Film Transistors

• n Glass,” ISSCC 2010.

Substrate Glass Interconnect Ti/Au evaporation, litho, wet etch Gate electrodes Al evaporation, shadow masking Source/Drain Au Evaporation, shadow masking Dielectric 5.7nm AlOx/SAM PFET DNTT, ~0.5 cm2/Vs NFET F16CuPc, ~0.02 cm2/Vs Area 28mm x 22mm Component count 74

Organic TFTs: Air Stability

S S dinaphto-thieno-thiophene (DNTT) pentacene

Yamamoto, J. Am. Chem. Soc. 129 2224 (2007) Klauk, Adv. Mater. 19 3882 (2007) Zschieschang, Adv. Mater. 22 982 (2010) Zschieschang, MRS Spring Meeting II-7.12 (2010) O O

air

 

Exposure to air (days)

30 60 90 120 150

Hole mobility (cm2/Vs)

0.1 1 10 stored and tested in air

[Slide by Hagen Klauk]

ADC Schematic

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VREFN

C/32 C/32 C/32

... ...

Bit 0 Bit 1 Bit 5 Bit 2, 3, 4

Input

SAR Logic (off-chip)

Output

To DAC

Comparator DAC with Sampler

C C C C 2C 2C

VREFN VREFN VREFP VREFN VREFP VREFP VMID VREFP VMID VREFN Calibration DAC Main DAC

Calibration enables 6-bit precision despite poorly matched capacitors C-2C structure possible due small stray caps (glass)

Comparator

45 CS1 CS2 CS3 CS4

CLK CLK CLK CLK CLK CLK CLK CLK

   

CF1 CF2 CF3 CF4

+

• Input

Output

Auto-zeroing cancels threshold voltage drift Anti-parallel PFET/NFET layout minimizes variations if CF due to misalignment

Cgdn Cgdp

8 16 24 32 40 48 56 63

• 4
• 2

2 4 DNL (LSB) Code 8 16 24 32 40 48 56 63

• 4
• 2

2 4 Code INL (LSB)

Measured DNL/INL

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Before calibration, 100 Hz clock rate

8 16 24 32 40 48 56 63

• 1
• 0.5

0.5 1 DNL (LSB) Code 8 16 24 32 40 48 56 63

• 1
• 0.5

0.5 1 Code INL (LSB)

Measured DNL/INL

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After calibration, 100 Hz clock rate

Organic ADC Summary

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Process 3 metal complementary

• rganic thin-film

Minimum feature size 20 m Chip area 28 mm x 22 mm Resolution 6 bits Full-scale range 2 V Max DNL / INL

• 0.6 LSB / 0.6 LSB

Clock rate / Update rate 100 Hz / 16.7 Hz Power consumption 3.6 W @ 3 V

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Conclusions

 Mixed-signal IC design remains a vibrant area of

research

 Changing boundary conditions



Ever-increasing need for higher performance, lower power



New applications



New device technologies

 A recurring theme in our research



Looking for new ways to overcome analog imperfections using DSP and calibration