Canonical Multi-Target Toffoli Circuits Hans-J org Kreowski, Sabine - - PowerPoint PPT Presentation

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Canonical Multi-Target Toffoli Circuits Hans-J org Kreowski, Sabine - - PowerPoint PPT Presentation

Canonical Multi-Target Toffoli Circuits Hans-J org Kreowski, Sabine Kuske and Aaron Lye University of Bremen, Department of Computer Science P.O.Box 33 04 40, 28334 Bremen, Germany { kreo,kuske,lye } @informatik.uni-bremen.de 18.03.2016 10th


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SLIDE 1

Canonical Multi-Target Toffoli Circuits

Hans-J¨

  • rg Kreowski, Sabine Kuske and Aaron Lye

University of Bremen, Department of Computer Science P.O.Box 33 04 40, 28334 Bremen, Germany {kreo,kuske,lye}@informatik.uni-bremen.de

18.03.2016 10th International Conference on Language and Automata Theory and Applications (LATA 2016)

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SLIDE 2

Reversible Circuits

◮ introduced by Toffoli at ICALP 1980 ◮ vivid research area in the last decade ◮ low power consumption ◮ relation to quantum circuits

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SLIDE 3

Reversible Computation

Definition (Reversible Function)

Let B = {0, 1}, and ID be a set of identifiers of Boolean variables. Let BX be the set of all mappings a: X → B for some X ⊆ ID where the elements of BX are called assignments. Then a bijective Boolean (multi-output) function f : BX → BX is called reversible.

Example (Reversible Circuit)

x1 x1 x2 x2 x3 x3 x4 x4

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SLIDE 4

Reversible Computation

x1 x1 x2 x2 x3 x3 x4 x4

Definition

  • 1. multi-target Toffoli gate

mtg = (T, c : T → 2X) with target lines T ⊆ X, T = ∅ and T ∩ c(T) = ∅ where c(T) =

t∈T

c(t) are control lines.

  • 2. parallel controlled negation

fmtg(a)(x) =

  • a(x)

if x ∈ T and a(y) = 1, ∀y ∈ c(x) a(x)

  • therwise
  • 3. multi-target Toffoli circuit mtc = mtg1 . . . mtgn
  • 4. fmtc = fmtgn ◦ · · · ◦ fmtg1

Toffoli circuits are universal

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SLIDE 5

Reversible Computation

Proposition

Let mtg = (T, c) be a multi-target Toffoli gate, let T ′ ⊆ T with ∅ = T ′ = T.

  • 1. Then mtg′ = (T ′, c′) with c′(t′) = c(t′) for t′ ∈ T ′ is a

multi-target Toffoli gate (denoted by mtg|T ′, called the restriction of mtg to T ′).

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SLIDE 6

Reversible Computation

Proposition

Let mtg = (T, c) be a multi-target Toffoli gate, let T ′ ⊆ T with ∅ = T ′ = T.

  • 1. Then mtg′ = (T ′, c′) with c′(t′) = c(t′) for t′ ∈ T ′ is a

multi-target Toffoli gate (denoted by mtg|T ′, called the restriction of mtg to T ′).

  • 2. Accordingly, mtg′′ = (T ′′, c′′) with T ′′ = T − T ′ and

c′′(t′′) = c(t′′) for t′′ ∈ T ′′ is also a multi-target Toffoli gate.

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SLIDE 7

Reversible Computation

Proposition

Let mtg = (T, c) be a multi-target Toffoli gate, let T ′ ⊆ T with ∅ = T ′ = T.

  • 1. Then mtg′ = (T ′, c′) with c′(t′) = c(t′) for t′ ∈ T ′ is a

multi-target Toffoli gate (denoted by mtg|T ′, called the restriction of mtg to T ′).

  • 2. Accordingly, mtg′′ = (T ′′, c′′) with T ′′ = T − T ′ and

c′′(t′′) = c(t′′) for t′′ ∈ T ′′ is also a multi-target Toffoli gate.

  • 3. The sequential composition mtg′mtg′′ is semantically

equivalent to mtg, i.e. fmtg = fmtg′mtg′′.

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SLIDE 8

Sequentialization and Parallelization

Definition

Let mtg = (T, c) and T ′ ⊆ T with ∅ = T ′ = T. Let mtg′ = mtg|T ′ and mtg′′ = mtg|T ′′ where T ′′ = T − T ′.

  • 1. Then mtg′mtg′′ is called sequentialization of mtg wrt T ′

and mtg parallelization of mtg′mtg′′ (denoted by mtg′ + mtg′′).

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SLIDE 9

Sequentialization and Parallelization

Definition

Let mtg = (T, c) and T ′ ⊆ T with ∅ = T ′ = T. Let mtg′ = mtg|T ′ and mtg′′ = mtg|T ′′ where T ′′ = T − T ′.

  • 1. Then mtg′mtg′′ is called sequentialization of mtg wrt T ′

and mtg parallelization of mtg′mtg′′ (denoted by mtg′ + mtg′′).

  • 2. Let mtc = mtc′mtgmtc′′ and mtg′mtg′′ be the

sequentialization of mtg wrt T ′. Let mtc = mtc′mtg′mtg′′mtc′′.

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SLIDE 10

Sequentialization and Parallelization

Definition

Let mtg = (T, c) and T ′ ⊆ T with ∅ = T ′ = T. Let mtg′ = mtg|T ′ and mtg′′ = mtg|T ′′ where T ′′ = T − T ′.

  • 1. Then mtg′mtg′′ is called sequentialization of mtg wrt T ′

and mtg parallelization of mtg′mtg′′ (denoted by mtg′ + mtg′′).

  • 2. Let mtc = mtc′mtgmtc′′ and mtg′mtg′′ be the

sequentialization of mtg wrt T ′. Let mtc = mtc′mtg′mtg′′mtc′′. Then mtc and mtc are

◮ in seq-relation wrt T ′ in gate i = |mtc′| + 1, denoted by

mtc − − − − − →

seq(i,T ′) mtc

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SLIDE 11

Sequentialization and Parallelization

Definition

Let mtg = (T, c) and T ′ ⊆ T with ∅ = T ′ = T. Let mtg′ = mtg|T ′ and mtg′′ = mtg|T ′′ where T ′′ = T − T ′.

  • 1. Then mtg′mtg′′ is called sequentialization of mtg wrt T ′

and mtg parallelization of mtg′mtg′′ (denoted by mtg′ + mtg′′).

  • 2. Let mtc = mtc′mtgmtc′′ and mtg′mtg′′ be the

sequentialization of mtg wrt T ′. Let mtc = mtc′mtg′mtg′′mtc′′. Then mtc and mtc are

◮ in seq-relation wrt T ′ in gate i = |mtc′| + 1, denoted by

mtc − − − − − →

seq(i,T ′) mtc

◮ in par-relation after gate i − 1 = |mtc′|, denoted by

mtc − − − − − →

par(i−1) mtc.

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SLIDE 12

Example

x1 x1 x2 x2 x3 x3 x4 x4

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SLIDE 13

Example

x1 x1 x2 x2 x3 x3 x4 x4

− − − − →

par(2)

x1 x1 x2 x2 x3 x3 x4 x4

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SLIDE 14

Example

x1 x1 x2 x2 x3 x3 x4 x4

− − − − →

par(2)

x1 x1 x2 x2 x3 x3 x4 x4

← − − − − − − −

s e q ( 3 , { x

2

} )

x1 x1 x2 x2 x3 x3 x4 x4

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SLIDE 15

Example

x1 x1 x2 x2 x3 x3 x4 x4

− − − − →

par(2)

x1 x1 x2 x2 x3 x3 x4 x4

← − − − − − − −

s e q ( 3 , { x

2

} )

x1 x1 x2 x2 x3 x3 x4 x4

− − − − →

par(1)

x1 x1 x2 x2 x3 x3 x4 x4

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SLIDE 16

Shift

Definition

Let mtc and mtc be two multi-target Toffoli circuits. Then mtc is a shift of mtc (for some i ≥ 1 and T ′ ⊆ X)1 if mtc − − − − − →

par(i−1)

  • mtc
  • r

mtc − − − − − − − →

seq(i+1,T ′)

mtc − − − − − →

par(i−1)

  • mtc

= = = mtc′mtg1mtg2mtc′′ mtc′mtg1mtg′

2mtg′′ 2 mtc′′

mtc′mtg1 + mtg′

2mtg′′ 2 mtc′′ 1where T ′ is the set of target lines of the gate i + 1 in case that the shift is

just a parallelization.

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SLIDE 17

Shift

Definition

Let mtc and mtc be two multi-target Toffoli circuits. Then mtc is a shift of mtc (for some i ≥ 1 and T ′ ⊆ X)1 if mtc − − − − − →

par(i−1)

  • mtc
  • r

mtc − − − − − − − →

seq(i+1,T ′)

mtc − − − − − →

par(i−1)

  • mtc

= = = mtc′mtg1mtg2mtc′′ mtc′mtg1mtg′

2mtg′′ 2 mtc′′

mtc′mtg1 + mtg′

2mtg′′ 2 mtc′′

denoted by mtc − − − − − →

sh(i,T ′)

  • mtc

1where T ′ is the set of target lines of the gate i + 1 in case that the shift is

just a parallelization.

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SLIDE 18

Example

x1 x1 x2 x2 x3 x3 x4 x4

− − − − →

par(2)

=

sh(3, {x2}) x1 x1 x2 x2 x3 x3 x4 x4

← − − − − − − −

s e q ( 3 , { x

2

} )

← − − − − − −

sh(2,{x2})

x1 x1 x2 x2 x3 x3 x4 x4

− − − − →

par(1)

x1 x1 x2 x2 x3 x3 x4 x4

What happens if one shifts as long as possible? Controlled negations move to the left

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SLIDE 19

Example

x1 x1 x2 x2 x3 x3 x4 x4

− − − − →

par(2)

=

sh(3, {x2}) x1 x1 x2 x2 x3 x3 x4 x4

← − − − − − − −

s e q ( 3 , { x

2

} )

← − − − − − −

sh(2,{x2})

x1 x1 x2 x2 x3 x3 x4 x4

− − − − →

par(1)

x1 x1 x2 x2 x3 x3 x4 x4

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SLIDE 20

Example

x1 x1 x2 x2 x3 x3 x4 x4

− − − − →

par(2)

=

sh(3, {x2}) x1 x1 x2 x2 x3 x3 x4 x4

← − − − − − − −

s e q ( 3 , { x

2

} )

← − − − − − −

sh(2,{x2})

x1 x1 x2 x2 x3 x3 x4 x4

− − − − →

par(1)

x1 x1 x2 x2 x3 x3 x4 x4

What happens if one shifts as long as possible?

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SLIDE 21

Example

x1 x1 x2 x2 x3 x3 x4 x4

− − − − →

par(2)

=

sh(3, {x2}) x1 x1 x2 x2 x3 x3 x4 x4

← − − − − − − −

s e q ( 3 , { x

2

} )

← − − − − − −

sh(2,{x2})

x1 x1 x2 x2 x3 x3 x4 x4

− − − − →

par(1)

x1 x1 x2 x2 x3 x3 x4 x4

What happens if one shifts as long as possible? Controlled negations move to the left

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SLIDE 22

Waiting Degree

Given mtc = (T1, c1) . . . (Tn, cn), then wait(mtc) =

n

  • j=1

(j − 1) · #Tj

Proposition

  • 1. If mtc −

− − − − →

par(i−1)

  • mtc, then wait(

mtc) = wait(mtc) −

n

  • j=i+1

#Tj.

  • 2. If mtc −

− − − − − − →

seq(i+1,T ′) mtc −

− − − − →

par(i−1)

  • mtc, then

wait( mtc) = wait(mtc) − #T ′.

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SLIDE 23

Waiting Degree

Given mtc = (T1, c1) . . . (Tn, cn), then wait(mtc) =

n

  • j=1

(j − 1) · #Tj

Proposition

  • 1. If mtc −

− − − − →

par(i−1)

  • mtc, then wait(

mtc) = wait(mtc) −

n

  • j=i+1

#Tj.

  • 2. If mtc −

− − − − − − →

seq(i+1,T ′) mtc −

− − − − →

par(i−1)

  • mtc, then

wait( mtc) = wait(mtc) − #T ′.

◮ The lengths of shift sequences are bounded by m(m−1) 2

where m =

n

  • i=1

#Ti

◮ Shifting as long as possible always terminates ◮ Resulting in a reduced (canonical) circuit

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SLIDE 24

Canonical Circuits

◮ Shift defines an equivalence relation on circuits (∼) ◮ Each equivalence class contains at least one canonical circuit

(as Corollary of the waiting degree results)

◮ Moreover, each canonical circuit is a unique representative of

its shift equivalence class, i.e. global optimum within its class

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SLIDE 25

Canonical Circuits

◮ Shift defines an equivalence relation on circuits (∼) ◮ Each equivalence class contains at least one canonical circuit

(as Corollary of the waiting degree results)

◮ Moreover, each canonical circuit is a unique representative of

its shift equivalence class, i.e. global optimum within its class

Theorem

Shift-equivalent canonical circuits are equal.

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SLIDE 26

Canonical Circuits

Theorem

Shift-equivalent canonical circuits are equal.

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SLIDE 27

Canonical Circuits

Theorem

Shift-equivalent canonical circuits are equal.

◮ One can prove that shift equivalence is confluent ◮ mtc ∼ mtc implies

  • mtc

mtc

sh ∗

mtc

sh ∗

for some mtc.

◮ i.e. each two equivalence circuits can be shifted into a

common circuits.

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SLIDE 28

Canonical Circuits

Theorem

Shift-equivalent canonical circuits are equal.

◮ One can prove that shift equivalence is confluent ◮ mtc ∼ mtc implies

  • mtc

mtc

sh ∗

mtc

sh ∗

for some mtc.

◮ i.e. each two equivalence circuits can be shifted into a

common circuits.

◮ mtc ∼ mtc iff there is a zigzag of shifts, i.e. a sequence

zz = mtc0 . . . mtcn such that (for all i = 0, . . . , n − 1) mtc0 = mtc, mtcn = mtc, mtci − →

sh mtci+1 or mtci+1 −

sh mtci ◮ problem:

mtc mtc1

sh

mtc2

sh ◮ The problem can be resolve by means of the local

Church-Rosser property

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SLIDE 29

Local Church-Rosser

Proposition

The shift relation has the local Church-Rosser property meaning that two shifts on a circuit mtc mtc mtc1

sh

mtc2

sh

imply mtc mtc1

sh ∗

mtc2

sh ∗

for some circuit mtc where

− →

sh is the reflexive and transitive

closure of the shift relation sh.

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SLIDE 30

Conclusion and Open Problems

◮ We have introduced multi-target Toffoli gates which perform

controlled negations in parallel

◮ Gates can be shifted to reduce the waiting degree ◮ Shifting as long as possible always terminates ◮ Reduced circuit is unique wrt shifting equivalence ◮ Generalize to mixed polarity Toffoli gates ◮ Combine with other optimization ◮ Consider exclusive sum of products circuits ◮ Consider mappings to quantum circuits ◮ Kreowski proved a normal form result for parallel derivations

  • n graphs of similar structure with similar proof techniques in

1976. What is the relation?

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SLIDE 31

Thank you

Questions?