Bit Error Rate Test of DHPT 1.0 Gigabit Serial Link Leonard Germic , - - PowerPoint PPT Presentation

bit error rate test of dhpt 1 0 gigabit serial link
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Bit Error Rate Test of DHPT 1.0 Gigabit Serial Link Leonard Germic , - - PowerPoint PPT Presentation

Bit Error Rate Test of DHPT 1.0 Gigabit Serial Link Leonard Germic , Carlos Marinas, Hans Krger and Norbert Wermes germic@physik.uni-bonn.de University of Bonn today, 2014 Content Gigabit Serial Link 1 Test Setup 2 Results 3


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SLIDE 1

Bit Error Rate Test of DHPT 1.0 Gigabit Serial Link

Leonard Germic, Carlos Marinas, Hans Krüger and Norbert Wermes germic@physik.uni-bonn.de

University of Bonn

today, 2014

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SLIDE 2

Content

1

Gigabit Serial Link

2

Test Setup

3

Results

germic@physik.uni-bonn.de 2 / 12

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SLIDE 3

Gigabit Serial Link of DHPT 1.0

Facts: 1.6 GHz differential output programmable preemphasis

  • ff-chip 100 Ω matching resistors

1.2 V domain (VDD_CML, core voltage)

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SLIDE 4

Why preemphasis

Compensation of the attenuation of high frequency regime in the signals spectrum due to long distance transmission

Increasing bandwidth Preventing single bit error Figure: Signal spectrum with preephasis.

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SLIDE 5

Signal generation

Preemphasis realization: Subtraction of signal S1 with delayed signal S2. Two 8 bit DACs IDAC_CML_TX_BIAS and IDAC_CML_TX_BIASD One 2 bit DAC pll_cml_dly_sel S1(t) S2(t) S2(t + dt) S1 − S2(t + dt)

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SLIDE 6

Implementation

Current Mode Logic Driver with programmable preemphasis Three parameters:

IDAC_CML_TX_BIAS, IDAC_CML_TX_BIASD, pll_cml_dly_sel Same values of IDAC_CML_TX_BIAS and IDAC_CML_TX_BIASD do not correspond to same currents/differential voltage swing (differently sized current mirrors)

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SLIDE 7

BERT Test setup

1x Evaluation board XUPV5 − LX110t as DHH emulator 1x Evaluation board XUPV5 − LX110t as Bit Error Rate Tester (IBERT, Xilinx) 2x 15 m Infini band cables ... and a crazy ’handmade’ script

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SLIDE 8

Figure: BERT Test system. Top board = DHH emulator, Buttom board = IBERT (Xilinx).

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SLIDE 9

BERT Results - Good A and bad B case

A B

Figure: Red line indicates the BERthr of 10−6

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SLIDE 10

Optimal Working Point

A B

Figure: Sweep results at a threshold of BERthr = 10−6. Higher is better - wider opening at BERthr

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SLIDE 11

Optimal Working Point

BEST

Optimal working point BIAS = 15, BIASD = 150, dly = 0.

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SLIDE 12

Thank you for your attention!

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SLIDE 13

Sweep test

These are NOT absolute BER values. NMOS of current mirrors saturate above DAC values ∼ 150 (Design bug)

Figure: Plateau due to saturation of the current mirrors.

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