BCD Smart Power Roadmap Trends and Challenges Giuseppe Croce NEREID WORKSHOP ‘Smart Energy’ Bertinoro, October 20 th
Outline 2 • Introduction • Major Trends in Smart Power ASICs • An insight on (some) differentiating enablers • Power Devices evolution • Enhanced Programmability (ePCM) • High Voltage applications • Challenges & Conclusions
Outline 3 • Introduction • Major Trends in Smart Power ASICs • An insight on (some) differentiating enablers • Power Devices evolution • Enhanced Programmability (ePCM) • High Voltage applications • Challenges & Conclusions
What is BCD ? 4 A concept introduced by ST in the mid-80s [1][2][3] widely used today in the industry [1] Single Chip Carries Three technologies , Electronics Week, December 10, 1984 [2] C. Cini, C. Contiero, C. Diazzi, P. Galbiati, D. Rossi, " A New Bipolar, CMOS, DMOS Mixed Technology for Intelligent Power Applications" , ESSDERC '85 Proceedings, Aachen (Germany), September 1985 [3] A. Andreini, C. Contiero, P. Galbiati, " A New Integrated Silicon Gate Technology Combining Bipolar Linear, CMOS Logic and DMOS Power Parts ", IEEE Transactions on Electron Devices, Vol. ED-33 No.12, December 1986
Analog + Digital + Power & HV on one chip 5 HV & Power High Voltage & Power section (DMOS) to drive external loads Analog Analog blocks to interface the external world to the digital systems Digital Digital core (CMOS) for signal processing
ST BCD Roadmap Strategy 6 Process customization by application & Differentiation Introduction of innovative modules and materials Performance Improvement & Area Saving : Power Evolution New power architectures to maintain best-in-class performances Leverage Power Discrete experience Performance Improvement & Area Saving Lithography Nodes Evolution Area reduction trend from lithography and increased wafer size thanks to ST’s experience in Advanced CMOS System Miniaturization & Area Saving: Assembly & Packaging Secure optimized finishing solution compatible with state of the Art assembly/Packaging technology
Outline 7 • Introduction • Major Trends in Smart Power ASICs • An insight on (some) differentiating enablers • Power Devices evolution • Enhanced Programmability (ePCM) • High Voltage applications • Challenges & Conclusions
Trends in modern Smart Power ASICs 8 - Junction Isolation ISOLATION & - Deep Trench Isolation INTEGRATION - SOI SCHEMES SCALING BENEFIT LOGIC CORES from - CMOS density Litho Node Evolution - Optimize Analog CMOS ANALOG - Enrich Basic Device Offer FEATURES (NVM, Active, Passive) LARGE - Thick Copper Metallization CURRENT - Bonding over Active Areas ROUTING Innovative POWER DEVICES POOR IMPROVEMENT Architecture - Specific ON resistance from to - Specific Gate Charge Geometry Scaling Optimize - Robustness Performance
Thick Cu Metallization schemes for High Current, High Power, Robust Bonding over Active Areas 9 • Ni/Pd Pad Finishing for • Ni/Pd Pad Finishing for Cu-Damascene + Al-cap • • Robust Bonding over Active Areas Robust Bonding over Active Areas Au • • Extended Temperature (>>150C) Reliability Extended Temperature (>>150C) Reliability Al-cap WIRE (Pad finishing) Al Cu-Damascene + Ni/Pd METAL3 Cu Pd Ni Cu Ni/Pd WIRE Cu (Pad finishing) Pd Ni METAL3 Cu Cu-RDL (Cu + Ni/Pd) Cu Ni/Pd WIRE (Metal Interconnect finishing) • Thick Cu Metallization • Thick Cu Metallization Pd Ni for High Current / High Power for High Current / High Power • • Cu-Damascene: Cu-Damascene: PI Cu Cu • • lower thickness lower thickness • • finer pitches finer pitches • • Cu-RDL: Cu-RDL: • • higher thickness higher thickness • • larger Cu-wire diameter on active Areas larger Cu-wire diameter on active Areas • • Lower Process Complexity Lower Process Complexity
Roadmap Evolution : Full Copper BEOL Thin Damascene-Cu + Thick Cu-RDL 10 Thick Cu-RDL (Cu+Ni/Pd ) Thick Cu-RDL (Cu+Ni/Pd ) 0.16µm FEOL & BEOL 3 thin Al + 1 thick Cu metals Al BEOL CMOS: 100Kgates/mm2 0.16µm FEOL & 0.11µm BEOL Cu BEOL 3 thin Cu + 1 thick Cu metals Thin Cu-Damascene Thin Cu-Damascene CMOS: 130Kgates/mm2 • +25% Increase of Logic Gate Density Increase of Energy Capability Robustness Al BEOL Cu BEOL in Repetitive Power Pulsing working condition (ex.: Automotive ABS, Injector Valve driver ICs) where: • High temperature gradients are generated inside power components • The associated thermo-mechanical stress produces plastic deformation of metal layers and risk of loss of integrity of dielectrics
Outline 11 • Introduction • Major Trends in Smart Power ASICs • An insight on (some) differentiating enablers • Power Devices evolution • Enhanced Programmability (ePCM) • High Voltage applications • Challenges & Conclusions
Power Device Performance vs Lithography 12 POWER DEVICES AREA scaling down depends more and more on DEVICE ARCHITECTURE than on Lithography Feature Reduction Relative Gain to Normalized R ON X Area Improvement Specific ON-resistance Gain from DEVICE ARCHITECTURE (R ON X Area) Gain from LITHOGRAPHY REDUCTION 100% 1.2 18-20 V LDMOS 90% 1 example 80% 70% 0.8 60% - 72 % 0.32 50% 0.6 µ m 40% 0.18 0.4 µ m 30% 20% 0.2 0.16 10% µ m 0 0% 0.6µm 0.16µm 0.32µm 0.18µm BCD6s BCD8A BCD8sP
Evolution of Integrated Power Device Architecture 13 BCD1 BCD2-5 electrons flow G BCD6 G D S G S D D S BCD8-9 G S D TAPERED FOX LOCOS RECESSED LOCOS STI BCD8-9 Plus BCD9-10 Next SOURCE DRAIN SELECTIVE TAPERED FOX in STI “POWER” LOCOS GATE G SOURCE DRAIN STI D S G D P-BODY S GATE N-DRAIN P-BODY N-DRAIN Evolution to STI: Current crowding Mitigation of � Negative Impact Straight current path Current crowding on performance � Improvement from Source to Drain � Low ON-resistance on performance
Enhanced Programmability: embedded Phase Change Memory(PCM) value 14 • Microcontroller integration on Advanced Power ASIC (Motor Controller, Digital Power Managemnt, Wireless Chargers, Automotive Body) requiring ‘cheap’ NVM solution • Novel Memory cell has been developed based on Phase Change Memory (PCM) materials Fully integrated Motor Driver GST ePCM ePCM (Phase Change Memory) in 110nm/90 nm BCD Platforms for SOC applications
Differentiation in Advanced BCD Technology ….…not only Power & Litho…….. 15 HV on SOI (200V to 300V) HV (600V to 1200V) Gate Drivers on 0.16um BCD Platforms on 0.32um BCD Platforms Galvanic Isolation (4KV to 6KV) on 0.32um – 0.16um BCD Platforms
Outline 16 • Introduction • Major Trends in Smart Power ASICs • An insight on (some) differentiating enablers • Power Devices evolution • Enhanced Programmability (ePCM) • High Voltage applications • Challenges & Conclusions
Next BCD development Challenges 17 Lithography Scaling Power: R ON X Q G • VLSI materials compatibility • New architectures ? • 300mm fabs availability • New Materials ? • Process complexity • SOA tailoring? Aging models? Future System Needs High Efficiency High switching f Galvanic Isolation Wide and different voltage rating COST, COST COST! Differentiation System Partitioning • New Memory • SiP: cost or performance? • High Performance Passives • Thermal management • Logic or Power intensive? • ‘Very’ High Voltage applications
Conclusions 18 • Smart Power BCD Technology is ‘slowly’ evolving towards Advanced CMOS Platforms • Process customization and differentiation are key to boost technology platform competitiveness • New Specific Modules (Cu RDL and DTI) in volume production • New Power device architecture as cost redution enabler and to meet high efficiency/ high frequency Power management • New features availability to enable new function integration
1/10/2017
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