An ultra-low-cost antenna array frontend for GNSS application Thuan - - PowerPoint PPT Presentation

International Collaboration Centre for Research and Development

• n Satellite Navigation Technology in South East Asia

An ultra-low-cost antenna array frontend for GNSS application

Thuan D. Nguyen, Vinh T. Tran Tung H. Ta, Letizia Lo Presti

NAVIS Centre, Hanoi University of Science and Technology, Vietnam

Australian Centre for Space Engineering Research, School of Electrical Engineering and Telecommunication, UNSW Politecnico di Torino, Italy

IGNSS 2016

Outline

• Motivation of design a low-cost antenna array frontend
• Proposed design for a low-cost antenna array frontend
• Problems and Solution in designing the low-cost frontend
• Synchronizing the received data
• Mitigating clock drift
• Verification of the antenna array frontend
• Phase offset among antenna elements
• Carrier to noise ratio improvement
• Conclusion and further works

Motivation of design a low-cost antenna array frontend

• Threats to GNSS signals:
• Jamming (prevent GNSS receivers track GNSS signals)
• Spoofing (provide the false position to GNSS receivers)

⇒Detect and locate the source of interference

Receiver/ Spoofer

Counterfeit signal is much stronger than authentic signal

Motivation of design a low-cost antenna array frontend

Antenna array based technique is the most effective technique to detect and mitigate interference because it is able to:

• Control the reception pattern
• f the array
• Increase signal-to-noise ratio
• Suppress interference
• Determine the DOA of GNSS

satellites and interference

• 𝑡𝑛 𝑢 = 𝑡1 𝑢 − 𝜐𝑛 = 𝑡1 𝑢 − Δ𝜍𝑛

𝑑

• Δ𝜍𝑛 = 𝒒𝑛 ⋅ 𝒃𝑡 𝜄, 𝜚 = 𝑌𝑛 sin 𝜄 cos 𝜚 +

𝑍𝑛 sin 𝜄 sin 𝜚 + 𝑎𝑛 cos 𝜄

Overview of antenna array frontend for GNSS

• Limitations of the existing antenna array frontend for GNSS:
• Cumbersome
• Costly
• Difficult for expansion (synchronization is performed in hardware

part)  Difficult to deployment

× BPF ADC ~ × BPF ADC × BPF ADC ~ Interleaving samples

Proposed antenna array frontend

• In our design, the synchronization block is carried out by our

specialized algorithm

×

BPF ADC

~ ×

BPF ADC

×

BPF ADC

~

USB/Ethernet USB/Ethernet USB/Ethernet

Synchronization

Master Element (Equipped TCXO) Slave Elements (Shared Master TCXO) USB Hub

Problems and Solution in designing the low-cost frontend

Synchronization Problem: Element signals are collected separately, they must be synchronized prior to use Solution: Due to the use of a common clock for ADC Time difference among elements is a product of a multiple of samples and the sampling period. The number of samples can be evaluated based on GNSS SDR

Subframe X Subframe X Subframe X Subframe X Element 1 Element 2 Element 3 Element 4 𝜐1 𝜐2 𝜐3

Problems and Solution in designing the low-cost frontend

Clock phase shift Problem: Regardless of the use of a common clock for all elements, the tuned frequency of Local Oscillator (LO) is slightly different in each element  corrupt the phase offset completely.

1000 2000 3000 4000 5000 6000 7000 8000 9000 10000

• 8
• 6
• 4
• 2

2 4 6 8 x 10

4

the tracking output of SV 9 Time (ms) Amplitude Inphase Prompt Quadrature Prompt

• 1
• 0.8
• 0.6
• 0.4
• 0.2

0.2 0.4 0.6 0.8 1

• 1
• 0.8
• 0.6
• 0.4
• 0.2

0.2 0.4 0.6 0.8 1 Inphase Prompt Quadrature Prompt the tracking output of SV 9

Problems and Solution in designing the low-cost frontend

100 200 300 400 500 600

• 0.02

0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.16 0.18 seconds Hz Shift Frequency

Clock phase shift Solution:

Δ𝑔 = ∠ 𝐽𝑅𝑛(𝑙) − ∠ 𝐽𝑅𝑛 𝑙 − 1 2𝜌𝑈𝑒

Problems and Solution in designing the low-cost frontend

Tracking loop RTL2832 dongle RTL2832 dongle RTL2832 dongle Code & Carrier replica Clock phase shift mitigation Clock phase shift mitigation carrier phase Carrier phase

~

TCXO

GPS Simulator

• 1
• 0.8
• 0.6
• 0.4
• 0.2

0.2 0.4 0.6 0.8 1

• 1
• 0.8
• 0.6
• 0.4
• 0.2

0.2 0.4 0.6 0.8 1 Normalized inphase prompt Normalized quadrature prompt Scatter plot of SV 9

Clock phase shift Solution (continue):

Represent the delay between this element and the first element

Antenna Array Frontend Verification

• Experiment setup schematic

Tracking loop RTL2832 dongle RTL2832 dongle RTL2832 dongle Code & Carrier replica Clock phase shift mitigation Clock phase shift mitigation Carrier phase offset Carrier phase offset

~

TCXO

GPS Simulator

The phase difference among the elements should be the same for all satellites

Antenna Array Frontend Verification

• 1.5
• 1
• 0.5

0.5 1 1.5

• 1.5
• 1
• 0.5

0.5 1 1.5 Normalized I-channel amplitude Normalized Q-channel amplitude Tracking Output of Element 2 PRN 17 PRN 5 PRN 13 PRN 9

• 1.5
• 1
• 0.5

0.5 1 1.5

• 1.5
• 1
• 0.5

0.5 1 1.5 Normalized I-channel amplitude Normalized Q-channel amplitude Tracking Output of Element 3 PRN 17 PRN 5 PRN 13 PRN 9

Achieved results:

Phase offset between element 2 and element 1 Phase offset between element 3 and element 1

Antenna Array Frontend Verification

Achieved result: The C/N0 increase when using antenna array:

1000 2000 3000 4000 5000 6000 7000 8000 9000 10000 36 38 40 42 44 46 48 ms dBHz Element 1 Element 2 Element 3 Beamed signal

Conclusion

• The preliminary results are very promising for not only GNSS

application but also the other field.

• In the future, such antenna array frontend will be used to

suppress interference, point to the source of the interference and spoofing to benchmark the performance of the frontend .

THA HANK Y YOU F FOR Y YOUR ATTENTION!!! !!!