An Anti-Aliasing Multi-Rate Modulator Anthony Chan Carusone Franco - - PowerPoint PPT Presentation

An Anti-Aliasing Multi-Rate Σ∆ Modulator

May 26, 2009

Anthony Chan Carusone

• Depart. of Elec. and Comp. Eng.

University of Toronto, Canada Franco Maloberti Department of Electronics University of Pavia, Italy

Outline

• Motivation and background
• Anti-aliasing multi-rate modulator front-end
• Practical considerations

– Mismatch – Mismatch – Clocking – Opamp settling requirements

• Simulation results
• Conclusions

2

Aliasing in Discrete-Time Σ∆ Modulators

Desired signal Alias

… …

fs f 2f s

fs 2OSR

… …

3

Anti-Aliasing in Discrete-Time Σ∆ Modulators

fs f

Desired signal Alias

2fs

fs

… …

fs f

Desired signal Alias

2fs

fs

… …

fs 2fs

s

2OSR

4

Σ∆ fs

AAF

DSP

fs 2fs

s

2OSR

AAF may be either a continuous-time filter or a discrete-time filter operating at a higher sampling rate [6,7], Mfs

Discrete-Time Σ∆ Modulator with Discrete-Time Anti-Aliasing Filter

Σ∆

M

L(z)

5

Basic idea is to incorporate L(z) into the front- end of the Σ∆ modulator with minimal circuit overhead Mfs fs

“Hybrid” Σ∆ Modulators

Ci

to modulator from DAC in

6

There are several examples of modulators incorporating a continuous-time front-end to provide an anti-aliasing STF [1-5], but these are still susceptible to clock jitter, like all CT modulators.

Conventional Σ∆ Modulator Front-end

Ci C

to modulator in

φi φi φ1 φ1

from DAC

7

C Ci ⁄ 1 z

1 –

–

• from DAC

to modulator in

Σ∆ Modulator with Anti-Aliasing Front-end Sampler

Ci C

φ φ

from DAC

Ci C1

to modulator in φ1 1

,

φ1 1

,

φ1 2

,

φ2 φ2 φ2

from SC-DAC

fs C2

8

Ci C

to modulator in

φi φi φ1 φ1 φ1 2

,

φ2 φ1 1

,

φ1 2

,

φ2 φ 2 1

,

φ2 1

,

φ1 φ2 1

,

φ1 φ1 φ2 2

,

φ1 φ2 2

,

φ2 2

,

φ1

Σ∆ Modulator with Anti-Aliasing Front-end Sampler

Ci C1

to modulator in φ1 1

,

φ1 1

,

φ1 2

,

φ2 φ2 φ2

from SC-DAC

fs C2

9

φ1 2

,

φ2 φ1 1

,

φ1 2

,

φ2 φ 2 1

,

φ2 1

,

φ1 φ2 1

,

φ1 φ1 φ2 2

,

φ1 φ2 2

,

φ2 2

,

φ1

Ck C

• 

  z

k – k 1 = M

∑

M

from DAC to modulator in

Mfs fs

C Ci ⁄ ( )z 1

–

1 z 1

–

–

Σ∆ Modulator with Anti-Aliasing Front-end Sampler

Σ∆

M L(z) Mfs fs

Similar approach has been applied to integrate anti-

10

Ck C

• 

  z

k – k 1 = M

∑

M

from DAC to modulator in

Mfs fs

C Ci ⁄ ( )z 1

–

1 z 1

–

–

• Mfs

fs

integrate anti- aliasing into the front-end of a discrete-time filter [8,9] and SAR ADC [10]

Other “Multi-Rate” Σ∆ Modulators

∫

Mfs fs

∫

↑M H(z)

e.g. [11]:

11

2

↓M

Other “Multi-Rate” Σ∆ Modulators

∫

Mfs fs

∫

↑M H(z)

e.g. [11]:

12

2

↓M

Multi-bit quantizer is replaced by a single-bit modulator + decimator operating at increased sampling rate

Choice of capacitor values, Ck

Zeros of L(z) with M = 5 :

13

1 1

Ck = (C/M) Ck chosen to maximize anti-aliasing around fs

Choice of capacitor values, Ck

Ck = (C/M) Ck “optimized”

14

Increased width of the anti-aliasing notch is particularly important in low-OSR modulators

Capacitor Mismatch

Ck = (C/M)

Alias frequency band for OSR = 24

15

Ck “optimized”

100 Monte-Carlo frequency responses with capacitor value standard deviation of 0.2%

Clocking

Ci C1

to modulator in φ1 1

,

φ1 1

,

φ1 2

,

φ2 φ2 φ2 φ1 2

,

φ2

from SC-DAC

fs

φ1 1

,

φ

C2

• This scheme requires the

generation of multiple clock phases [2]

• Faster settling of the

sampling capacitors necessitates larger

16

φ1 2

,

φ2 φ 2 1

,

φ2 1

,

φ1 φ2 1

,

φ1 φ1 φ2 2

,

φ1 φ2 2

,

φ2 2

,

φ1

switches and, hence, some overhead in the clock distribution

• Skew between the clock

phases results in harmonic at fs ± fin, which will be filtered by the following digital decimation filter

Opamp Settling Time

Ci C Ci C ≈ 2 ⁄

Conventional Σ∆ Σ∆ Σ∆ Σ∆ modulator front-end during the integration phase: Anti-aliasing multi-rate Σ∆ Σ∆ Σ∆ Σ∆ modulator front-end during the integration phase:

17

Cin Cin

Since only ½ of the total sampling capacitance is integrated at any time, the feedback factor in the integration phase is increased, thus permitting the use of an opamp with lower GBW.

Simulation Results

• 3rd-oder modulator
• OSR = 24
• Two-tone input:

– -2 dBFS in-band – -30 dBFS at 0.98fs

(a) (b)

SNDR = 28.5 dB SNDR = 62.3 dB Aliased tone

s

a) Conventional front-end b) Anti-aliasing multi-rate front-end with M = 5 and Ck = C/M c) Anti-aliasing multi-rate front-end with M = 5 and optimized Ck

18

(c)

SNDR = 84.3 dB

Simulation Results

19

35 dB 30 dB

Conclusions

• Splitting the input sampling capacitor in a

discrete-time Σ∆ modulator into multiple parallel branches sampled at increased rate enables the STF to be shaped by an FIR transfer function, here used for anti-aliasing used for anti-aliasing

• Example 3rd-order modulator with OSR=24 and

M=5 demonstrates:

– 35 dB of anti-aliasing is provided by a uniformly segmented input sampling capacitor, Ck = C/5 – An additional 30 dB of anti-aliasing is provided when the values of Ck are optimized for a total of 65 dB of anti-aliasing

20

EXTRAS

21

Simulation Model

22

Table of optimized capacitor values

23