Amorphous silicon thin-film transistors for flexible electronics - - PowerPoint PPT Presentation

▶
amorphous silicon thin film transistors for flexible
SMART_READER_LITE
LIVE PREVIEW

Amorphous silicon thin-film transistors for flexible electronics - - PowerPoint PPT Presentation

Sep 16, 2023 593 likes •833 views

Amorphous silicon thin-film transistors for flexible electronics Helena Gleskova, I-Chun Cheng, Ke Long, Sigurd Wagner, James Sturm Department of Electrical Engineering and Princeton Institute for the Science and Technology of Materials

slide-1
SLIDE 1

Amorphous silicon thin-film transistors for flexible electronics

Helena Gleskova, I-Chun Cheng, Ke Long, Sigurd Wagner, James Sturm Department of Electrical Engineering and Princeton Institute for the Science and Technology of Materials Princeton University Zhigang Suo Division of Engineering and Applied Sciences, Harvard University The work at Princeton University is supported by the United States Display Consortium.

Berkeley, April 13, 2007

slide-2
SLIDE 2

http://www.eink.com/iim/sale.html

Flexible displays

Lucent, E-Ink

slide-3
SLIDE 3

Encapsulation

1 μm - 1 mm

Substrate 10 μm - 1 mm Transistor layer ~ 1 μm Display layer (LCD, PLED..) Schematic cross section

  • f a display
  • TFT backplane is generic for all flat panel technologies
  • Add display layer on top

Transistor “backplane” and display “frontplane”

Amorphous silicon thin film transistor generic backplane SiNx a-Si:H Cr Substrate: glass, steel, plastic Source Drain Gate

Passivation layer Passivation layer

Backplane | Frontplane

Gleskova H., Wagner S., IEEE Electron Device Letters 20 (1999), pp. 473-475.

slide-4
SLIDE 4
  • Metal versus plastic foil substrate
  • a-Si:H TFT deposition temperature
  • Overlay alignment

Outline

slide-5
SLIDE 5

Steel versus plastic

polymer foil substrate steel foil substrate process temperature dimensional stability visually clear permeable to O2 or H2O surface roughness inert to chemicals electrical conductor up to ~1000°C > 10 times higher no no rough yes yes < 280°C low some yes moderate some no

Kattamis A.Z., Princeton University Cheng I-C. et al., IEEE EDL 27 (2006) 166.

slide-6
SLIDE 6

Steel versus plastic

polymer foil substrate steel foil substrate

process temperature

dimensional stability visually clear permeable to O2 or H2O surface roughness inert to chemicals electrical conductor up to ~1000°C > 10 times higher no no rough yes yes < 280°C low some yes moderate some no

Kattamis A.Z., Princeton University Cheng I-C. et al., IEEE EDL 27 (2006) 166.

slide-7
SLIDE 7

Ion/Ioff > 107, μlin ~ 0.45 cm2/Vs, VT ~ 2 V

Tdep = 150ºC

10-13 10-11 10-9 10-7 10-5 10-13 10-11 10-9 10-7 10-5

  • 10
  • 5

5 10 15 20 Drain-to-source current Ids (A) Gate-to-source current Igs (A) Gate-to-source voltage Vgs (V) Vds = 10 V 0.1 V Ids Igs Acceptable TFT performance, but …

a-Si:H TFTs made at 150ºC on Kapton

Gate Source Drain

Gleskova H. et al., J. Electrochem. Society 148 (2001), pp. G370-G374. Gleskova H. et al., J. Appl. Phys. 92 (2002), pp. 6224-6229.

slide-8
SLIDE 8
  • 10
  • 5

5 10 15 20 10

  • 12

10

  • 11

10

  • 10

10

  • 9

10

  • 8

10

  • 7

10

  • 6

10

  • 5

10

  • 4

Drain Current ID(A) Gate-to-Source Voltage VGS (V)

Stress time: 600 sec Initial After stress of Vg = 20 V

Bias-stress instability of a-Si:H TFTs

Long K. et al., IEEE Electron Device Lett. 27 (2006), pp. 111-113.

slide-9
SLIDE 9

⇒ Must make a-Si:H TFTs at high process temperature

[1] Gleskova, IEEE TED, 2001 [2] Cheng, IEEE Proc. Solid-State and Integrated Circuit Tech., 1998 [3] Kanicki, APL, 1993 [4] Tsukada, JAP, 1991 [5] Long, Princeton Univ.

10 0.1 1 10

Threshold Change ΔVΤ (V)

Stress Field (*10

7 V/m)

Stress time: 600sec

Glass (300°C-350°C) [2] Glass (350°C) [3] Kapton-E (150°C) [1] Glass (300°C-360°C) [4] Glass (150°C) [5]

a-Si TFT stability rises with process temperature

slide-10
SLIDE 10

a-Si:H TFTs made on clear plastic at 280ºC

Cherenack K., Princeton University

slide-11
SLIDE 11

a-Si:H TFT stability on clear plastic substrates

10 0.1 1 10

Threshold Change ΔVΤ (V)

Stress Field (*10

7 V/m)

Clear plastic (150ºC) Clear Plastic (250ºC)

Stress time: 600sec

Glass (300°C-350°C) Glass (350°C) Kapton-E (150°C) Glass (300°C-360°C) Glass (150°C) ΔVT depends only on process T, not on substrate material

Long K. et al., IEEE Electron Device Lett. 27 (2006), pp. 111-113.

slide-12
SLIDE 12

Steel versus plastic

polymer foil substrate steel foil substrate process temperature

dimensional stability

visually clear permeable to O2 or H2O surface roughness inert to chemicals electrical conductor up to ~1000°C > 10 times higher no no rough yes yes < 280°C low some yes moderate some no

Kattamis A.Z., Princeton University Cheng I-C. et al., IEEE EDL 27 (2006) 166.

slide-13
SLIDE 13

thick substrate (large ds) thin film (small df) Ys⋅ds versus Yf ⋅df OTFT / polymer substrate Ys⋅ds >> Yf ⋅df OLED / steel substrate Ys⋅ds >> Yf ⋅df compliant (small Yf) stiff (large Yf) poly-Si TFT / steel substrate Ys⋅ds >> Yf ⋅df stiff (large Ys) compliant (small Ys) a-Si TFT / polymer substrate Ys⋅ds ≈ Yf ⋅df

Substrate stiffness affects dimensional stability

Wu C.C. et al., IEEE EDL 18 (1997) 609 Gleskova H., Princeton University Jackson T., Penn State Univ. Wu M. et al., APL 75 (1999) 2244

slide-14
SLIDE 14
  • 3. Cr gate metal deposition

80 nm

a-Si:H TFT process

  • 1. Front SiNx passivation
  • 2. Back SiNx passivation

SiNx Kapton 500 nm

  • 4. Cr gate patterning - mask 1

80 nm

Cheng I-C. et al., J. SID 13 (2005), pp. 563-568.

slide-15
SLIDE 15

Cr 80 nm (n+) a-Si:H 50 nm undoped a-Si:H 200 nm

  • 5. PECVD TFT stack: 5 W SiNx

(i) a-Si:H (n+) a-Si:H

  • 6. Cr S/D deposition
  • 5. PECVD TFT stack: 12 W SiNx

(i) a-Si:H (n+) a-Si:H

  • 6. Cr S/D deposition
  • 7. S/D patterning – mask 2
  • 7. S/D patterning – mask 2

a-Si:H TFT process – cont.

SiNx Substrate 300 nm

Cheng I-C. et al., J. SID 13 (2005), pp. 563-568.

slide-16
SLIDE 16

Location of alignment marks

roll axis

mask 1 & 2

1 2 3 4 5

52 mm 52 mm 70 mm 70 mm

40 μm

feature of mask 2: S/D layer feature of mask 1: bottom gate metal layer

Cheng I-C. et al., J. SID 13 (2005), pp. 563-568.

slide-17
SLIDE 17

3 4

40 μm 40 μm

shrinkage ~ 30 μm shrinkage ~ 28 μm

  • shrink. ~ 25 μm
  • shrink. ~ 20 μm

5W gate SiNx

40 μm

1

40 μm

5 2

40 μm

~ 52 mm ~ 52 mm ~ 52 mm ~ 52 mm Average shrinkage ~ 500 ppm

Cheng I-C. et al., J. SID 13 (2005), pp. 563-568.

slide-18
SLIDE 18

~ 52 mm ~ 52 mm ~ 52 mm ~ 52 mm

40 μm 40 μm

5

Average change ~ 100 ppm

12W gate SiNx

stretching ~ 6 μm stretching ~ 3 μm

  • shrink. ~ 10 μm
  • shrink. ~ 1 μm

40 μm

1

40 μm 40 μm

3

40 μm 40 μm

4

40 μm 40 μm

2

40 μm

Cheng I-C. et al., J. SID 13 (2005), pp. 563-568.

slide-19
SLIDE 19

Substrate at room temperature Tr Workpiece at Tr when held flat εs(Tr ) εf (Tr ) Workpiece at Td after film growth εs(Td ) εf (Td ) Substrate at deposition temperature Td αs (Td –Tr )

Film grown on foil substrate at elevated temperature

Film and substrate at Tr if they were separated αf (Td –Tr ) αs > αf

( ) (

)

[ ]

f f s s bi d r s f r s

d Y d Y T T T + + − ⋅ − = 1 ) ( ε α α ε

s f

ν ν =

εbi Free-standing film at Td εbi < 0

Gleskova H. et al., Appl. Phys. Lett. 88 (2006), 011905. Gleskova H. et al., in Flexible Electronics: Materials and Applications,

  • Eds. Wong W.S., Salleo A., Springer-Verlag – to be published.
slide-20
SLIDE 20

Workpiece at Tr when released from the substrate holder R Workpiece at Tr when held flat

Film release from the substrate holder

( )(

) (

)

[ ]

⎟ ⎟ ⎠ ⎞ ⎜ ⎜ ⎝ ⎛ + ⎟ ⎟ ⎠ ⎞ ⎜ ⎜ ⎝ ⎛ + + ⎟ ⎟ ⎟ ⎠ ⎞ ⎜ ⎜ ⎜ ⎝ ⎛ − ⋅ + − ⋅ − + =

s f s f s s f f s s f f bi d r s f s s f f s

d d d d d Y d Y d Y d Y T T d Y d Y d R 1 1 4 1 1 6

2 2 2 2

ε α α ν

40 mW/cm2 8 Bare 19 24 SiNx

Cheng I-C. et al., J. SID 13 (2005), pp. 563-568. Suo Z. et al., Appl. Phys. Lett. 74 (1999), pp. 1177-1179.

slide-21
SLIDE 21

Steel foil A rigid substrate foil is not changed much by CTE mismatch Possible to maintain reasonable overlay accuracy

  • 0.1
  • 0.05

0.05 0.1

  • 60
  • 40
  • 20

20 40 60

  • 0.01
  • 0.005

0.005 0.01 150oC 200oC 250oC

Steel

Td Curvature 1/R (cm-1) Substrate strain after film deposition εs(Tr) (ppm) tensile built-in stress compressive built-in stress SiNx built-in strain

Gleskova H. et al., in Flexible Electronics: Materials and Applications, Eds. Wong W.S., Salleo A., Springer-Verlag – to be published.

slide-22
SLIDE 22

Kapton foil Stress built into the SiNx can compensate thermal mismatch and eliminate curvature and misalignment

  • 1
  • 0.5

0.5 1

  • 1000
  • 500

500 1000

  • 0.01
  • 0.005

0.005 0.01 150oC 200oC 250oC

Kapton

Td Curvature 1/R (cm-1) Substrate strain after film deposition εs(Tr) (ppm) tensile built-in stress compressive built-in stress SiNx built-in strain

Gleskova H. et al., in Flexible Electronics: Materials and Applications, Eds. Wong W.S., Salleo A., Springer-Verlag – to be published.

slide-23
SLIDE 23

Summary

  • Deposition at elevated temperature changes in-plane dimensions
  • Changes are small if (steel) or (Kapton)

05 . <

s f

d d

~

001 . <

s f

d d

~

~ 20 ppm for a-Si:H TFTs on 100-μm steel foil ~ 500 ppm for a-Si:H TFTs on 100-μm Kapton foil

  • CTE mismatch change in in-plane dimensions is
  • Tailor built-in stress in the film to compensate CTE mismatch

⇒ possible to eliminate misalignment ⇒ possible to eliminate curvature of the workpiece

  • Higher deposition temperatures needed for good TFT stability