Advanced FinFET Process Technology M. Masahara National Institute - - PowerPoint PPT Presentation
National Institute of Advanced Industrial Science and Technology Advanced FinFET Process Technology M. Masahara National Institute of AIST 1 National Institute of Advanced Industrial Science and Technology Contents 1. 1. Introduction
National Institute of Advanced Industrial Science and Technology
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National Institute of Advanced Industrial Science and Technology
1. Introduction 2. Advanced FinFET Process Technology 3. Summary
1. Introduction 2. Advanced FinFET Process Technology 3. Summary
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National Institute of Advanced Industrial Science and Technology
S G D S G D
1st FinFET Patent in 1980 from AIST FinFET Proposed by AIST in 1980
(named “FinFET” by UCB in 1999)
Ultrathin and undoped channel and self-aligned double gate Extremely high short channel effect (SCE) immunity
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National Institute of Advanced Industrial Science and Technology
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FinFETs show the smallest DIBL (=highest SCE immunity)
National Institute of Advanced Industrial Science and Technology
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However, several technological issues still exist…
S G D S G D
Fin Formation Vth Tuning Low Resistive Source/Drain Stress Eng. SOI or Bulk Compact Model (110) Channel Cpara Variation I/O, ESD
National Institute of Advanced Industrial Science and Technology
1. Introduction 2. Advanced FinFET Process Technology 3. Summary
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National Institute of Advanced Industrial Science and Technology
0.2 0.4 0.6 0.8 1 4 4.2 4.4 4.6 4.8 5 5.2 5.4 VthDG(NMOS), -VthDG(PMOS) (V) Gate Workfunction (eV)
n+-Si (4.17eV) p+-Si (5.25eV) 0.4V(LSTP) 0.2V(LOP) 4.6eV 4.9eV 4.75eV
Vth has a linear relationship with Gate Workfunction For low Vth, dual metal gate (dual WF) is needed
AIST, IEEE TED 2007
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National Institute of Advanced Industrial Science and Technology
0.5 1 1.5 10-12 10-11 10-10 10-9 10-8 10-7 10-6 10-5 10-4 10-3
Gate Voltage, V g [ V ] Drain Current, Id [ A ]
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0.5 1 1.5 10-12 10-11 10-10 10-9 10-8 10-7 10-6 10-5 10-4 10-3
Gate Voltage, V g [ V ] Drain Current, I d [ A ]
Weff =7.5 m NMOS PMOS |Vd | = 1 V 0.05 V
Almost symmetrical Vth’s (normally off) are obtained thanks to the midgap work function of TiN (4.75 eV)
n+ poly-Si gate TiN-gate Symmetric Vth Asymmetric Vth
NMOS PMOS |Vd | = 1 V 0.05 V Weff =17 m Lg = 21 m Weff =7.5 m Lg = 21 m Weff =17 m
National Institute of Advanced Industrial Science and Technology
TiN nMOS TaCN pMOS
Integration of TiN and TaCN gate FinFETs
Etching residue
“Deposition and etching”
General approach:
“Metal Inter-diffusion”
(No metal etching)
For PMOS Mo(4.95 eV) For NMOS Ta(4.25 eV)/Mo stack Ta Inter-diffusion in Mo
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National Institute of Advanced Industrial Science and Technology
10-3 10-2 10-1 100 5 10 15 Ta ion count [arb. unit] Depth [nm]
Ta layer Mo layer SiO2 Ta diffusion
Annealed (700oC 1 h) As depo.
O2+
Back-side SIMS Ta diffuses in Mo and piles-up at Mo/SiO2 interface after annealing Thus WF for NMOS is determined by Ta (4.25eV)
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National Institute of Advanced Industrial Science and Technology
SiO2 HM etchback in nMOS region Ta and SiO2 HM etchback in pMOS region Patterning of Mo and Ta/Mo gates
No metal residue
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National Institute of Advanced Industrial Science and Technology
AIST, IEEE EDL 2008
For NMOS, low Vth can be achieved by Ta diffusion in Mo For PMOS, low Vth can be achieved by Mo Off leakage Negligible PMOS
Mo (high WF) Ta (low WF) low gate WF by Ta diffusion Mo (high WF)
NMOS
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National Institute of Advanced Industrial Science and Technology
G1 G2 S D G1 G2 S D Vth control gate Drive gate
4T-FinFET = Independent DG FinFET
Ioff Ion Vg1 Ioff Ion Vg1 log Id VthDG Vth(G1)
log Id
+Vg2
DG separation
S G D S G D
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Vth for FinFET can be controlled flexibly and individually by separating the DG
National Institute of Advanced Industrial Science and Technology
G S D CMP G1 S D G2 CMP Stopper
ＳＥＭ Image after CMP
FinFET Formation DG Separation by CMP
Gate1 Gate2 Source Drain
Fin Top
100nm Side Wall
ＳＥＭ Image after LEB
FinFET Formation and Lithography DG Separation by LEB Resist BOX sub Fin Gate Stopper
CMP Process Local Etch-back Process
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0.2 0.4 0.6 0.8 50 100 150 200 250 300 350
Vg2 [ V ] Vth [ V ] S-Slope [ mV/decade ]
& Tsi = 8.5-nm, = 0.79 & Tsi = 13-nm, = 0.66 & Tsi = 23-nm, = 0.42 & Tsi = 43-nm, = 0.24
G1 G2 S D G1 G2 S D
Vth can be tuned from LSTP to HP flexibly by selecting a proper Vg2 (The Second Gate)
National Institute of Advanced Industrial Science and Technology
1. Introduction 2. Advanced FinFET Process Technology 3. Summary
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National Institute of Advanced Industrial Science and Technology
(1) (2) (3) (5) (4)
(2) Fin Thickness (TSi) (3) Oxide Thickness (Tox) (4) RDF (5) Work Function WFV (m) (1) Gate Length (Lg)
Possible Vth Variation Sources
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FinFET variability sources were systematically analyzed
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Negligible
Dimension Variation sources
5 10 15 20 25 30 35
Measured Vth TFin Source LG Source Tox Source m Source
LG=6.7 nm (measured) TFin=2.9 nm (measured) Tox=0.032 nm (measured)
Vth [mV]
LG= 100 nm TFin= 40 nm <Vth>= 0.42 V
AIST, IEEE EDL 2010
Main Cause
Dimension variation sources are negligible Main cause of the Vth variation is the Workfunction Variation
National Institute of Advanced Industrial Science and Technology
Rough etched side wall causes randomly aligned metal grain and thus higher WF variation If side wall is flat, uniformly aligned metal grain and thus lower WF variation can be expected
S D
RIE Ideal Randomly aligned Metal Higher WF variation Uniformly aligned Metal Lower WF variation
Si 1-Metal SiO2 Si SiO2 G 2-Metal 1-Metal
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National Institute of Advanced Industrial Science and Technology
AIST, IEDM 2006
5 10 15 1000 2000 3000 4000 5000
Etching time [ min ] Etching Depth [ nm ]
214 nm/min
2.38% TMAH 50oC
(110) (111) (100) 359 nm/min 9 nm/min
5 10 15 1000 2000 3000 4000 5000
Etching time [ min ] Etching Depth [ nm ]
214 nm/min
2.38% TMAH 50oC
(110) (111) (100) 359 nm/min 9 nm/min
Extremely low ER of (111) in TMAH Flat (111) side wall
Etchant： 2.38% TMAH (Resist Developer) (Tetramethylammonium hydroxide)
CH3 CH3 CH3 CH3 N
+
OH - CH3 CH3 CH3 CH3 N
+
OH -
fin-mask Si-fin TMAH
BOX SOI
<110> <111> 20
National Institute of Advanced Industrial Science and Technology
Source Drain Si-fin 20 nm Gate Hfin = 45 nm TSi = 12 nm Tox
Min.Lg = 20 nm, TSi = 17.8 nm, HSi = 45 nm Nano-Wet-Etched FinFET Undoped channel Tox(CET) = 2.3 nm by C-V Gate Stack : PVD-TiN/SiO2
AIST, VLSI Symp. 2010
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National Institute of Advanced Industrial Science and Technology
5 10 15 20 25 30 35 40 5 10 15 20 25 Vth [ mV ] 1/(WL)1/2 [ mm-1 ]
PVD-TiN Gate CET = 2. 3 nm
AVt was significantly lowered by flattening the side channel
AIST, VLSI Symp. 2010
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National Institute of Advanced Industrial Science and Technology
Structure Gate Stack Author. Organi- zation Reference 1 FDSOI Poly/SiO2 A.Cathignol ST ESSDERC2006 2 FDSOI TiN/HfO2
Beranger ST IEDM2007 3 FDSOI (SOTB) NiSi/ Y.Morita Hitachi VLSI2008 4 Bulk-planar Poly/SiON T.Tsunomura Selete VLSI2008 5 Bulk-planar MG/HK F.Arnaud ST IEDM2008 6 Bulk-planar MG/HK S.Hasegawa Toshiba IEDM2008 7 Bulk-planar s-Si/SiON H.Fukutome Fujitsu IEDM2009 8 Bulk-planar HK/MG M.Goto Toshiba VLSI2009 9 FinFET Mo/SiO2 T.Matsukawa AIST VLSI2009 10 Bulk-planar MG/HK F.Arnaud ST IEDM2009 11 Bulk-planar MG/HK L.A.Ragnarsso n IMEC IEDM2009 12 Bulk-planar MG/HK L.A.Ragnarsso n IMEC IEDM2009 13 FDSOI MG/HK K.Cheng IBM IEDM2009 14 FinFET TiN/HfSiO T.Chiarella IMEC ESSDERC2009 15 FinFET TiN/SiO2 Y.Liu AIST VLSI2010
1 2 3 4 1 2 3 4 Bulk-planar FDSOI FinFET Avt =Vt(LW)1/2 [mV-um] Tox [nm]
1 2 3 4 5 6 7 8 9 10 11 12 13 15 14
List of reported AVt values
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LSTP15nm LSTP22nm
Obtained Avt meets 22-nm-node SRAM requirement For 15nm and beyond, Avt should be further reduced
National Institute of Advanced Industrial Science and Technology
1. Introduction 2. Advanced FinFET Process Technology 3. Summary
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National Institute of Advanced Industrial Science and Technology
By introducing Ta/Mo dual metal gate technology, low Vth (±0.2V) can be obtained for CMOS FinFETs. By separating the DG, Vth can be tuned from 0.2V to 0.4V flexibly. Flattening of Si-fin sidewall channel is very promising for reducing Vth variations.
This work was supported in part by NEDO
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