Administrivia Mini project deadline: today Attach the capture of - - PowerPoint PPT Presentation

Administrivia

• Mini project deadline: today

– Attach the capture of the evaluation run output

• Guest lecture on Friday

– Algorithmic Verification of Stability of Hybrid Systems by Dr. Pavithra Prabhakar. K-State

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Administrivia

• Project proposal due: 2/27

– Original research

• Related to real-time embedded systems/CPS

– Building a cyber-physical system (robot)

• Must include real-time performance evaluation on a

selected hardware platform

– Repeating the evaluation of a chosen paper

• Any one of the suggested papers.

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Real-Time DRAM Controller

Heechul Yun

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Multicore for Embedded Systems

• Benefits of multicore processors

– Lots of sensor data to process – More performance, less cost – Save space, weight, power (SWaP)

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Challenges: Shared Resources

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CPU Memory Hierarchy

Unicore

T1 T2 Core 1 Memory Hierarchy Core 2 Core 3 Core 4

Multicore

T 1 T 2 T 3 T 4 T 5 T 6 T 7 T 8

Performance Impact

Why is DRAM Important?

• Why do we need bigger and faster memory?
• Data intensive computing

– Bigger, more complex application – Large amount of data processing

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Why is DRAM Important?

• Parallelism

– Out-of-order core

• A single core can generate many memory requests

– Multicore

• Multiple cores share DRAM

– Accelerator

• GPU

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Memory Performance Isolation

• Q. How to guarantee predictable memory

performance?

Part 1 Part 2 Part 3 Part 4

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Core1 Core2 Core3 Core4 DRAM Memory Controller LLC LLC LLC LLC

Memory System Architecture

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CORE 1

L2 CACHE 0

SHARED L3 CACHE DRAM INTERFACE

CORE 0 CORE 2 CORE 3

L2 CACHE 1 L2 CACHE 2 L2 CACHE 3

DRAM BANKS

DR DRAM MEM EMORY CONTRO ROLLER

This slide is from Prof. Onur Mutlu

DRAM Organization

• Channel
• Rank
• Chip
• Bank
• Row
• Row/Column

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The DRAM subsystem

Memory channel Memory channel DIMM (Dual in-line memory module) Processor “Channel”

This slide is from Prof. Onur Mutlu

Breaking down a DIMM

DIMM (Dual in-line memory module) Side view Front of DIMM Back of DIMM

This slide is from Prof. Onur Mutlu

Breaking down a DIMM

DIMM (Dual in-line memory module) Side view Front of DIMM Back of DIMM Rank 0: collection of 8 chips Rank 1

This slide is from Prof. Onur Mutlu

Rank

Rank 0 (Front) Rank 1 (Back) Data <0:63> CS <0:1> Addr/Cmd <0:63> <0:63> Memory channel

This slide is from Prof. Onur Mutlu

Breaking down a Rank

Rank 0 <0:63> Chip 0 Chip 1 Chip 7

. . .

<0:7> <8:15> <56:63> Data <0:63>

This slide is from Prof. Onur Mutlu

Breaking down a Chip

Chip 0 <0:7> Bank 0

<0:7> <0:7> <0:7>

...

<0:7>

This slide is from Prof. Onur Mutlu

Breaking down a Bank

Bank 0 <0:7>

row 0 row 16k-1

...

2kB

1B

1B (column)

1B

Row-buffer

1B

...

<0:7>

This slide is from Prof. Onur Mutlu

Example: Transferring a cache block

0xFFFF…F 0x00 0x40

...

64B cache block Physical memory space

Channel 0 DIMM 0 Rank 0

This slide is from Prof. Onur Mutlu

Example: Transferring a cache block

0xFFFF…F 0x00 0x40

...

64B cache block Physical memory space

Rank 0

Chip 0 Chip 1 Chip 7

<0:7> <8:15> <56:63> Data <0:63>

. . .

This slide is from Prof. Onur Mutlu

Example: Transferring a cache block

0xFFFF…F 0x00 0x40

...

64B cache block Physical memory space

Rank 0

Chip 0 Chip 1 Chip 7

<0:7> <8:15> <56:63> Data <0:63>

Row 0 Col 0

. . .

This slide is from Prof. Onur Mutlu

Example: Transferring a cache block

0xFFFF…F 0x00 0x40

...

64B cache block Physical memory space

Rank 0

Chip 0 Chip 1 Chip 7

<0:7> <8:15> <56:63> Data <0:63>

8B Row 0 Col 0

. . .

8B

This slide is from Prof. Onur Mutlu

Example: Transferring a cache block

0xFFFF…F 0x00 0x40

...

64B cache block Physical memory space

Rank 0

Chip 0 Chip 1 Chip 7

<0:7> <8:15> <56:63> Data <0:63>

8B Row 0 Col 1

. . .

This slide is from Prof. Onur Mutlu

Example: Transferring a cache block

0xFFFF…F 0x00 0x40

...

64B cache block Physical memory space

Rank 0

Chip 0 Chip 1 Chip 7

<0:7> <8:15> <56:63> Data <0:63>

8B 8B Row 0 Col 1

. . .

8B

This slide is from Prof. Onur Mutlu

Example: Transferring a cache block

0xFFFF…F 0x00 0x40

...

64B cache block Physical memory space

Rank 0

Chip 0 Chip 1 Chip 7

<0:7> <8:15> <56:63> Data <0:63>

8B 8B Row 0 Col 1

A 64B cache block takes 8 I/O cycles to transfer. During the process, 8 columns are read sequentially.

. . .

This slide is from Prof. Onur Mutlu

DRAM Organization

L3 DRAM DIMM Memory Controller (MC) Bank 4 Bank 3 Bank 2 Bank 1

Core1 Core2 Core3 Core4

• Have multiple banks
• Different banks can be

accessed in parallel

Best-case

L3 DRAM DIMM Memory Controller (MC) Bank 4 Bank 3 Bank 2 Bank 1

Core1 Core2 Core3 Core4

Fast

• Peak = 10.6 GB/s

– DDR3 1333Mhz

Best-case

L3 DRAM DIMM Memory Controller (MC) Bank 4 Bank 3 Bank 2 Bank 1

Core1 Core2 Core3 Core4

• Peak = 10.6 GB/s

– DDR3 1333Mhz

• Out-of-order processors

Fast

Most-cases

L3 DRAM DIMM Memory Controller (MC) Bank 4 Bank 3 Bank 2 Bank 1

Core1 Core2 Core3 Core4

Mess

• Performance = ??

Worst-case

• 1bank b/w

– Less than peak b/w – How much?

Slow

L3 DRAM DIMM Memory Controller (MC) Bank 4 Bank 3 Bank 2 Bank 1

Core1 Core2 Core3 Core4

Bank 4

DRAM Chip

Row 1 Row 2 Row 3 Row 4 Row 5 Bank 1 Row Buffer Bank 2 Bank 3 activate precharge Read/write

• State dependent access latency

– Row miss: 19 cycles, Row hit: 9 cycles

(*) PC6400-DDR2 with 5-5-5 (RAS-CAS-CL latency setting)

READ (Bank 1, Row 3, Col 7)

Col7

DDR3 Timing Parameters

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Kim et al., “Bounding Memory Interference Delay in COTS-based Multi-Core Systems,” RTAS’14

DRAM Controller

• Service DRAM requests (from CPU) while obeying

timing/resource constraints

– Translate requests to DRAM command sequences – Timing constraints: e.g., minimum write-to-read delay, activation time, … – Resource conflicts: bank, bus, channel

• Maximize performance

– Buffering, reordering, pipelining in scheduling requests

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DRAM Controller

• Request queue

– Buffer read/write requests from CPU cores – Unpredictable queuing delay due to reordering

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Bruce Jacob et al, “Memory Systems: Cache, DRAM, Disk” Fig 13.1.

Request Reordering

• Improve row hit ratio and throughput
• Unpredictable queuing delay

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Core1: READ Row 1, Col 1 Core2: READ Row 2, Col 1 Core1: READ Row 1, Col 2 Core1: READ Row 1, Col 1 Core1: READ Row 1, Col 2 Core2: READ Row 2, Col 1

DRAM DRAM Initial Queue Reordered Queue 2 Row Switch 1 Row Switch

Row Management Policy

• Open row

– Keep the row open after an access

• If next access targets the same row: CAS
• If next access targets a different row: PRE + ACT + CAS
• Close row

– Close the row after an access

• always pay the same (longer) cost: ACT + CAS
• Adaptive policies

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Real-Time Memory Controllers

• Provided guaranteed performance in

accessing DRAM.

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Real-Time Memory Controllers

• Bank grouping

– Each mem req. access ALL banks

• Private banking

– Each core has dedicated DRAM banks

• Scheduling

– Use analysis friendly scheduling (e.g., round-robin)

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Real-Time Memory Controllers (RTMC)

• Predator
• AMC
• PRET-MC
• DcMc
• MEDUSA
• Bundling

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RTMC References

• Predator: a predictable sdram memory controller”.

CODES+ISSS 2007.

• An analyzable memory controller for hard real-time CMPs,

IEEE Embedded Systems Letters, 2009

• PRET DRAM controller: Bank privatization for predictability

and temporal isolation, CODES+ISSS, 2011

• A dual-criticality memory controller (dcmc): Proposal and

evaluation of a space case study, RTAS, 2015

• Improved DRAM Timing Bounds for Real-Time DRAM

Controllers with Read/Write Bundling, 2016

• A Comprehensive Study of DRAM Controllers in Real-Time
• Systems. Danlu Guo, MS Thesis, University of Waterloo,

2016

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