SLIDE 1
Overview
¨ Announcement
¤ Homework 3 submission deadline: Nov. 11th
¨ This lecture
¤ Virtual memory ¤ Page tables and address translation ¤ Translation look-aside buffer (TLB)
ADDRESS TRANSLATION AND TLB Mahdi Nazm Bojnordi Assistant Professor - - PowerPoint PPT Presentation
ADDRESS TRANSLATION AND TLB Mahdi Nazm Bojnordi Assistant Professor - - PowerPoint PPT Presentation
ADDRESS TRANSLATION AND TLB Mahdi Nazm Bojnordi Assistant Professor School of Computing University of Utah CS/ECE 6810: Computer Architecture Overview Announcement Homework 3 submission deadline: Nov. 11 th This lecture Virtual
SLIDE 2
SLIDE 3
Recall: Memory Hierarchy
Secondary Memory Main Memory Cache Capacity: 8MB Time: ~20 ns Capacity: 8GB Time: ~250 ns Capacity: 500GB Time: ~10 ms
Greater Capacity
¨ Lower levels provide greater capacity longer time
¤ Does the program fit in main memory? ¤ What if running multiple programs?
SLIDE 4
Virtual Memory
¨ Use the main memory as a “cache” for secondary
memory
¤ Placement policy? Disk Main Memory
for(i=0; i<100;++i) { a[i]++; }
SLIDE 5
Virtual Memory
¨ Use the main memory as a “cache” for secondary
memory
¤ Placement policy?
¨ Allow efficient and safe sharing the physical main memory
among multiple programs
¤ Replacement policy? Disk Main Memory
for(i=0; i<100;++i) { a[i]++; } for(i=0; i<200;++i) { a[i]=a[i]+i; }
SLIDE 6
Virtual Memory Systems
¨ Provides illusion of very large memory
¤ Address space of each program larger than the
physical main memory
Secondary Memory App Virtual Address Space
¨ Memory management unit (MMU)
¤ Between main and secondary mem. ¤ Address translation
n Virtual address space used by the
program
n Physical address space is provided by
the physical main memory
SLIDE 7
Virtual Memory Systems
¨ Provides illusion of very large memory
¤ Address space of each program larger than the
physical main memory
Secondary Memory App Virtual Address Space Main Memory Translation
¨ Memory management unit (MMU)
¤ Between main and secondary mem. ¤ Address translation
n Virtual address space used by the
program
n Physical address space is provided by
the physical main memory
SLIDE 8
Virtual Address
¨ Every virtual address is translated to a physical
address with the help of hardware
¨ Data granularity
Physical Memory Virtual Address Physical Address 1G 29 31
SLIDE 9
Virtual Address
¨ Every virtual address is translated to a physical
address with the help of hardware
¨ Data granularity
Physical Memory
Page Frame 0 Page Frame 1 Page Frame 2 Page Frame N-1 …
Virtual Address Physical Address 1G 29 31
SLIDE 10
Virtual Address
¨ Every virtual address is translated to a physical
address with the help of hardware
¨ Data granularity
Physical Memory
Page Frame 0 Page Frame 1 Page Frame 2 Page Frame N-1 …
Virtual Address Physical Address
- ffset
- ffset
1G 29 31
SLIDE 11
Virtual Address
¨ Every virtual address is translated to a physical
address with the help of hardware
¨ Data granularity
Physical Memory
Page Frame 0 Page Frame 1 Page Frame 2 Page Frame N-1 …
Virtual Address Physical Address
- ffset
- ffset
Virtual Page No Page frame No Translator
1G 29 31
SLIDE 12
Virtual Address
¨ Every virtual address is translated to a physical
address with the help of hardware
¨ Data granularity
Physical Memory
Page Frame 0 Page Frame 1 Page Frame 2 Page Frame N-1 …
Virtual Address Physical Address
- ffset
- ffset
Virtual Page No Page frame No
Page Table 1G 29 31
What is the table size?
SLIDE 13
Address Translation Issues
¨ Where to store the table?
¤ Too big for on-chip cache ¤ Should be maintained in the main memory
SLIDE 14
Address Translation Issues
¨ Where to store the table?
¤ Too big for on-chip cache ¤ Should be maintained in the main memory
¨ What to do on a page table miss (page fault)?
¤ No valid frame assigned to the virtual page ¤ OS copies the page from disk to page frame
SLIDE 15
Address Translation Issues
¨ Where to store the table?
¤ Too big for on-chip cache ¤ Should be maintained in the main memory
¨ What to do on a page table miss (page fault)?
¤ No valid frame assigned to the virtual page ¤ OS copies the page from disk to page frame
¨ What is the cost of address translation?
¤ Additional accesses to main memory per every access ¤ Optimizations?
SLIDE 16
Address Translation Cost
¨ Page walk: look up the physical address in the page
table
¤ How many pages to store the page table?
Virtual Address Physical Address
12 12 20 Page frame No Page Table baseà
SLIDE 17
Multi-Level Page Table
¨ The virtual (logical) address space is broken down
into multiple pages
¤ Example: 4KB pages
Virtual Address Physical Address
12 12 10 Page frame No baseà 10
SLIDE 18
Translation Lookaside Buffer
¨ Exploit locality to reduce address translation time
¤ Keep the translation in a buffer for future references
Physical Memory
Page Frame 0 Page Frame 1 Page Frame 2 Page Frame N-1 …
Virtual Address Physical Address
- ffset
- ffset
Virtual Page No Page frame No
Page Table
SLIDE 19
Translation Lookaside Buffer
¨ Exploit locality to reduce address translation time
¤ Keep the translation in a buffer for future references
Physical Memory
Page Frame 0 Page Frame 1 Page Frame 2 Page Frame N-1 …
Virtual Address Physical Address
- ffset
- ffset
Virtual Page No Page frame No
Page Table
1 1
TLB
SLIDE 20
Translation Lookaside Buffer
¨ Just like any other cache, the TLB can be organized
as fully associative, set associative, or direct
¨ TLB access is typically faster than cache access
¤ Because TLBs are much smaller than caches ¤ TLBs are typically not more than 128 to 256 entries
even on high-end machines
V Virtual Page # Physical Page # Dirty Status
SLIDE 21
CAM Based TLB
¨ Content addressable memory (CAM)
¤ Unlike RAM, data in address out Address in Data in Data out match address RAM: Read Operation CAM: Search Operation Decoder
SLIDE 22
CAM Based TLB
¨ Content addressable memory (CAM)
¤ Unlike RAM, data in address out
¨ CAM based TLB
¤ Both CAM and RAM are used Virtual Page No Physical Page No Dirty Status CAM RAM What if multiple rows match?
SLIDE 23
TLB in Memory Hierarchy
¨ On a TLB miss, is the page loaded in memory?
¤ Yes: takes 10’s cycles to update the TLB ¤ No: page fault
n Takes 1,000,000’s cycles to load the page and update TLB
Processor Core TLB Lookup Cache Main Memory VA hit PA miss Data hit
SLIDE 24
TLB in Memory Hierarchy
¨ On a TLB miss, is the page loaded in memory?
¤ Yes: takes 10’s cycles to update the TLB ¤ No: page fault
n Takes 1,000,000’s cycles to load the page and update TLB
Processor Core TLB Lookup Cache Main Memory VA hit PA miss Translaltion miss Data hit
SLIDE 25
TLB in Memory Hierarchy
¨ On a TLB miss, is the page loaded in memory?
¤ Yes: takes 10’s cycles to update the TLB ¤ No: page fault
n Takes 1,000,000’s cycles to load the page and update TLB
Processor Core TLB Lookup Cache Main Memory VA hit PA miss Translaltion miss Data hit Physically indexed, physically tagged: TLB on critical path!
SLIDE 26
Physically Indexed Caches
¨ Problem: increased critical path due to sequential
access to TLB and cache
Virtual Page No Page Offset TLB Physical Frame Page Offset
SLIDE 27
Physically Indexed Caches
¨ Problem: increased critical path due to sequential
access to TLB and cache
Virtual Page No Page Offset TLB Physical Frame Page Offset Tag Array Data Array = Data Block hit/miss* Tag Index Byte
SLIDE 28
Physically Indexed Caches
¨ Problem: increased critical path due to sequential
access to TLB and cache
Virtual Page No Page Offset TLB Physical Frame Page Offset Tag Array Data Array = Data Block hit/miss* Tag Index Byte
Observation: lower address bits (page offset) are not translated
SLIDE 29
Virtually Indexed Caches
¨ Idea: Index into cache in parallel with page number
translation in TLB
Virtual Page No Page Offset TLB Tag Array Data Array = Data Block hit/miss* Tag Index Byte
SLIDE 30
Virtually Indexed Caches
¨ Idea: Index into cache in parallel with page number
translation in TLB
Virtual Page No Page Offset TLB Tag Array Data Array = Data Block hit/miss* Tag Index Byte